FAN2306MPX [ONSEMI]
6A,18V 高能效 PoL 稳压器;型号: | FAN2306MPX |
厂家: | ONSEMI |
描述: | 6A,18V 高能效 PoL 稳压器 稳压器 |
文件: | 总22页 (文件大小:2079K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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September 2015
FAN2306 / FAN2306M
6 A Synchronous Buck Regulator
Description
Features
The FAN2306
/
FAN2306M are highly efficient
.
.
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.
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.
.
.
.
VIN Range: 4.5 V to 18 V
synchronous buck regulators. They are capable of
operating with an input range from 4.5 V to 18 V,
supporting 6 A continuous load currents.
High Efficiency: Over 96% Peak
Continuous Output Current: 6 A
PFM Mode for Light-Load Efficiency
Ultrasonic or No-Ultrasonic Mode Options
Excellent Line and Load Transient Response
Precision Reference: ±1% Over Temperature
Output Voltage Range: 0.6 to 5.5 V
Programmable Frequency: 200 kHz to 1.5 MHz
Programmable Soft-Start
These devices utilize Fairchild’s constant on-time
control architecture to provide excellent transient
response and to maintain a relatively constant switching
frequency. The FAN2306 / FAN2306M utilize Pulse
Frequency Modulation (PFM) mode to maximize light-
load efficiency by reducing switching frequency when
the inductor is operating in Discontinuous Conduction
Mode (DCM) at light loads. The FAN2306 includes an
ultrasonic mode with minimum frequency clamp to keep
the switching frequency above the audible range, while
the FAN2306M does not include the minimum frequency
clamp to maximize efficiency to extremely light loads.
Low Shutdown Current
Switching frequency and over-current protection can
be programmed to provide a flexible solution for
various applications. Output over-voltage, under-
voltage, over-current, and thermal shutdown protections
help prevent damage to the device during fault
conditions. After thermal shutdown is activated, a
hysteresis feature restarts the device when normal
operating temperature is reached.
Adjustable Sourcing Current Limit
Internal Boot Diode
Thermal Shutdown
Halogen and Lead Free, RoHS Compliant
Applications
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Servers and Desktop Computers
NVDC Notebooks, Netbooks
Game Consoles
Telecommunications
Storage
Base Stations
Ordering Information
Operating
Output
Part Number
Configuration
Temperature
Range
Package
Current (A)
FAN2306MPX
PFM with Ultrasonic Mode
PFM, No Ultrasonic Mode
-40 to 125°C
6
6
34-Lead, PQFN,
5.5 mm x 5.0 mm
FAN2306MMPX
-40 to 125°C
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
Typical Application Diagram
VBIAS = 5V
VIN = 12V
R11
10Ω
C10
2.2µF
C9
0.1µF
CIN
CIN
0.1µF
2x10µF
PVCC
VIN
PVIN
VCC
EN
Ext
EN
C3
0.1µF
VOUT = 1.2V
IOUT=0-6A
BOOT
SW
L1
1.2µH
FAN2306
FAN2306M
PGOOD
ILIM
SOFT START
R2
1.5kΩ
C4
0.1µF
COUT
4x47µF
R5 1.5kΩ
R3
10kΩ
C5
100pF
C7
15nF
FREQ
FB
R9
54.9kΩ
R4
10kΩ
AGND
PGND
Figure 1. Typical Application
Functional Block Diagram
VIN
BOOT PVIN
PVCC
PVCC
VCC
VCC
EN
VCC UVLO
0.8V/
2.0V
PVCC
ENABLE
VCC
VCC
10µA
Modulator
HS Gate
Driver
SS
FB
FB
Comparator
VREF
SW
PFM
Comparator
FREQ
Control
Logic
2nd Level Over
Voltage Comparator
x1.2
PVCC
1st Level Over
Voltage Comparator
x1.1
x0.9
LS Gate
Driver
Under Voltage
Comparator
VCC
PGOOD
Thermal
10µA
Shutdown
Current Limit
Comparator
AGND
ILIM
PGND
Figure 2. Block Diagram
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
2
Pin Configuration
5
7
6
4
2
9
8
3
5
1
1
3
4
6
8
2
7
9
PVIN 10
PVIN 11
34 NC
33 NC
NC
34
33
10 PVIN
PVIN
(P2)
11
12
13
NC
PVIN
FREQ
SS
32
31
FREQ
SW 12
SW 13
32
31
SW
SW
SS
AGND
(P1)
SW
(P3)
SW 14
SW 15
SW 16
SW 17
PGOOD 30
SW
SW
SW
SW
30 PGOOD
14
15
EN
29
28
27
EN
29
28
27
16
17
NC
FB
NC
FB
21
20
19
18
25
24
23
22
18
19
20
21
22
23
24
25
26
26
Figure 3. Pin Assignments, Bottom View
Figure 4. Pin Assignments, Top View
Pin Definitions
Name
Pad / Pin
Description
PVIN
VIN
P2, 5-11
1
Power input for the power stage
Input to the modulator for input voltage feed-forward
Power input for the low-side gate driver and boot diode
Power supply input for the controller
PVCC
VCC
25
26
PGND
AGND
SW
18-21
P1, 4, 23
Power ground for the low-side power MOSFET and for the low-side gate driver
Analog ground for the analog portions of the IC and for substrate
P3, 2, 12-17, 22 Switching node; junction between high-and low-side MOSFETs
Supply for high-side MOSFET gate driver. A capacitor from BOOT to SW supplies the
charge to turn on the N-channel high-side MOSFET. During the freewheeling interval
(low-side MOSFET on), the high-side capacitor is recharged by an internal diode
connected to PVCC.
BOOT
3
ILIM
FB
24
27
Current limit. A resistor between ILIM and SW sets the current limit threshold.
Output voltage feedback to the modulator
Enable input to the IC. Pin must be driven logic HIGH to enable, or logic LOW to
disable.
EN
SS
29
31
32
Soft-start input to the modulator
On-time and frequency programming pin. Connect a resistor between FREQ and
AGND to program on-time and switching frequency.
FREQ
PGOOD
NC
30
Power good; open-drain output indicating VOUT is within set limits.
Leave pin open or connect to AGND.
28, 33-34
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VPVIN
Parameter
Power Input
Conditions
Referenced to PGND
Min. Max. Unit
-0.3 25.0
-0.3 25.0
-0.3 26.0
-0.3 30.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
VIN
Modulator Input
Referenced to AGND
Referenced to PVCC
VBOOT
Boot Voltage
Referenced to PVCC, <20 ns
Referenced to PGND, AGND
Referenced to PGND, AGND < 20 ns
Referenced to SW
-1
25
25
VSW
SW Voltage to GND
-5
Boot to SW Voltage
Boot to PGND
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
6.0
VBOOT
Referenced to PGND
30
VPVCC
VVCC
VILIM
VFB
Gate Drive Supply Input
Controller Supply Input
Current Limit Input
Output Voltage Feedback
Enable Input
Referenced to PGND, AGND
Referenced to PGND, AGND
Referenced to AGND
6.0
6.0
6.0
Referenced to AGND
6.0
VEN
Referenced to AGND
6.0
VSS
Soft Start Input
Referenced to AGND
6.0
VFREQ
Frequency Input
Referenced to AGND
6.0
VPGOOD Power Good Output
Referenced to AGND
6.0
Human Body Model, JESD22-A114(1)
Charged Device Model, JESD22-C101(2)
2000
2500
+150
ESD
Electrostatic Discharge
TJ
Junction Temperature
Storage Temperature
TSTG
-55 +150
Note:
1. Exception for FB pin up to 350V
2. Exception for FB pin up to 500V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Power Input
Conditions
Referenced to PGND
Referenced to AGND
Min.
Max.
Unit
VPVIN
VIN
4.5
4.5
-40
18.0
18.0
+125
9
V
V
Modulator Input
TJ
Junction Temperature
Load Current
°C
A
ILOAD
VPVCC
TA=25°C, No Airflow
Gate Drive Supply Input
Referenced to PGND, AGND
4.5
5.5
V
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
4
Thermal Characteristics
The thermal characteristics were evaluated on a 4-layer pcb structure (1 oz/1 oz/1 oz/1 oz) measuring 7 cm x 7 cm).
Symbol
JA
Parameter
Typ.
35
Unit
°C/W
°C/W
°C/W
Thermal Resistance, Junction-to-Ambient
ψJC
Thermal Characterization Parameter, Junction-to-Top of Case
Thermal Characterization Parameter, Junction-to-PCB
2.7
ψJPCB
2.3
Electrical Characteristics
Unless otherwise noted; VIN=12 V, VOUT=1.2 V, TA = TJ = -40 to +125°C. (4)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Supply Current
IVCC,SD
IVCC,Q
Shutdown Current
Quiescent Current
EN=0 V
10
µA
mA
mA
EN=5 V, Not Switching
EN=5 V, fSW=500 kHz
1.8
IVIN,GateCharge Gate Charge Current
10
Reference, Feedback Comparator
VFB
IFB
FB Voltage Trip Point
FB Pin Bias Current
590
596
0
602
100
mV
nA
-100
Modulator
RFREQ=56.2 kΩ,
VIN=10 V, tON=250 ns,
No Load
tON
On-Time Accuracy
-20
20
%
tOFF,MIN
DMIN
Minimum SW Off-Time
Minimum Duty Cycle
320
0
374
ns
%
FB=1 V
fMINF
Minimum Frequency Clamp
FAN2306 Only
18.2
25.4
32.7
kHz
Soft-Start
ISS
Soft-Start Current
SS=0 V
7
10
13
µA
%
tON,SSMOD
SS On-Time Modulation
SS<0.6 V
VFB=0.6 V
25
100
VSSCLAMP,NOM Nominal Soft-Start Voltage Clamp
400
40
mV
Soft-Start Voltage Clamp in Overload
VSSCLAMP,OVL
Condition
VFB=0.3 V, OC Condition
mV
PFM Zero-Crossing Detection Comparator
VOFF
Current Limit
ILIM
ZCD Offset Voltage
TA=TJ=25°C
-6
0
mV
%
Valley Current Limit Accuracy
ILIM Set-Point Scale Factor
Temperature Coefficient
TA=TJ=25°C, IVALLEY =7 A
FAN2306
-10
10
KILIM
233
ILIMTC
4000
ppm/°C
Enable
VTH+
Rising Threshold
2.0
V
V
VTH-
Falling Threshold
Enable Pin Leakage
Enable Pin Leakage
0.8
IENLK
VEN=1.2 V
VEN=5 V
100
76
nA
µA
IENLK
UVLO
VON
VCC Good Threshold Rising
Hysteresis Voltage
4.4
V
VHYS
160
mV
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
5
Electrical Characteristics (Continued)
Unless otherwise noted; VIN=12 V, VOUT=1.2 V, TA = TJ = -40 to +125°C. (4)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Fault Protection
VUVP
VVOP1
VOVP2
RPGOOD
PGOOD UV Trip Point
PGOOD OV Trip Point
On FB Falling
86
89
92
115
125
125
2.03
1
%
%
On FB Rising
108
118
111
122
Second OV Trip Point
On FB Rising; LS=On
IPGOOD=2 mA
%
PGOOD Pull-Down Resistance
Ω
tPG,SSDELAY PGOOD Soft-Start Delay
IPG,LEAK PGOOD Leakage Current
Thermal Shutdown
0.82
1.42
ms
µA
TOFF
THYS
Thermal Shutdown Trip Point(3)
Hysteresis(3)
155
15
°C
°C
Internal Bootstrap Diode
VFBOOT Forward Voltage
IR Reverse Leakage
Note:
IF=10 mA
VR=5 V
0.6
V
1000
µA
3. Guaranteed by design; not production tested.
4. Device is 100% production tested at TA=25°C. Limits over that temperature are guaranteed by design.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
6
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, VOUT=1.2 V, fSW=500 kHz, TA=25°C, and no
airflow; unless otherwise specified.
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
Vo=5V, L=3.3uH
Fsw=300kHz, L=1.8uH
Fsw=500kHz, L=1.2uH
Fsw=1MHz, L=0.56uH
Fsw=1.5MHz, L=0.4uH
Vo=3.3V, L=2.4uH
Vo=1.2V, L=1.2uH
Vo=1.05V, L=1.2uH
0.01
0.1
1
10
0.01
0.1
1
10
Load Current (A)
Load Current (A)
Figure 5. FAN2306 Efficiency vs. Load Current with Figure 6. FAN2306 Efficiency vs. Load Current with
VIN=12 V and fSW=500 kHz VIN=12 V and VOUT=1.2 V
100
90
80
70
60
50
40
30
100
90
80
70
60
50
Vo=5V, L=3.3uH
Vo=3.3V, 2.4uH
Vo=1.2V, L=1.2uH
Vo=1.05V, L=1.2uH
Vin=12V, L=1.2uH
Vin=8V, L=1.2uH
Vin=5V, L=1.2uH
0.01
0.1
1
10
0.01
0.1
1
10
Load Current (A)
Load Current (A)
Figure 7. FAN2306 Efficiency vs. Load Current with
VOUT=1.2 V and fSW=500 kHz
Figure 8. FAN2306M Efficiency vs. Load Current
VIN=12 V and fSW=500 kHz
100
100
90
90
80
80
70
Fsw=300kH, L=1.8uH
Vin=12V, L=1.2uH
Vin=8V, L=1.2uH
Vin=5V, L=1.2uH
Fsw=500kHz, L=1.2uH
Fsw=1MHz, L=0.56uH
Fsw=1.5MHz, L=0.4uH
50
70
60
60
0.01
0.1
1
10
0.01
0.1
1
10
Load Current (A)
Load Current (A)
Figure 9. FAN2306M Efficiency vs. Load Current
with VIN=12 V and VOUT=1.2 V
Figure 10. FAN2306M Efficiency vs. Load Current
with VOUT=1.2 V and fSW=500 kHz
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
7
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, VOUT=1.2 V, fSW=500 kHz, TA=25°C, and no
airflow; unless otherwise specified.
1.220
35
12Vi/1.2Vo/500kHz
1.215
30
12Vi/1.2Vo/1MHz
1.210
25
12Vi/1.2Vo/1.5MHz
1.205
20
1.200
15
1.195
10
1.190
5
1.185
1.180
0
0
1
2
3
4
5
6
0
5
10
Output Current (A)
Load Current (A)
Figure 11. Case Temperature Rise vs. Load Current
Figure 12. Load Regulation
1.220
1.215
1.210
1.205
1.200
1.195
1.190
Vout (20mV/div)
Vin=12V
Iout=0.1A
VSW (5V/div)
Load=0A
Load = 6A
5
7
9
11
13
15
Input Voltage (V)
Figure 13. FAN2306M Static Output Ripple with No
Load
Figure 14. Line Regulation
EN (5V/div)
EN (5V/div)
Soft Start (0.5V/div)
Vout (0.5V/div)
Vin=12V
Iout=0A
Vin=12V
Iout=6A
Soft Start (0.5V/div)
Vout (0.5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
Time (500µs/div)
Figure 15. Startup Waveforms with 0 A Load Current Figure 16. Startup Waveforms with 6 A Load Current
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
8
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, VOUT=1.2 V, fSW=500 kHz, TA=25°C, and no
airflow; unless otherwise specified.
Vout (20mV/div)
Vout (20mV/div)
Vin=12V
Vout=1.2V
Vin=12V
Vout=1.2V
Iout (1A/div)
Iout (1A/div)
Figure 17. FAN2306M Transition from DCM to CCM
Figure 18. FAN2306M Transition from CCM to DCM
EN (5V/div)
EN (5V/div)
Soft Start (0.5V/div)
Vin=12V
Iout=0A
Soft Start (0.5V/div)
Vout (0.5V/div)
Vin=12V
Iout=6A
Vout (0.5V/div)
Vout Prebias
PGOOD (5V/div)
PGOOD (5V/div)
Figure 19. Shutdown Waveforms with 6 A Load
Current
Figure 20. Startup Waveforms with Pre-Bias Voltage
on Output
Vout (20mV/div)
Vout (20mV/div)
Vin=12V
Iout=6A
Vin=12V
Iout=0.1A
VSW (5V/div)
VSW (5V/div)
Figure 21. FAN2306 Static Output Ripple at Light Load
Figure 22. Static Output Ripple at Full Load
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
9
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, VOUT=1.2 V, fSW=500 kHz, TA=25°C, and no
airflow; unless otherwise specified.
Vout (20mV/div)
Vout (20mV/div)
Vin=12V
Vout=1.2V
Vin=12V
Vout=1.2V
Iout (1A/div)
Iout (1A/div)
Figure 23. FAN2306 Transition from DCM to CCM
Figure 24. FAN2306 Transition from CCM to DCM
Vin=12V, Vout=1.2V
Iout from 0A to 3A, 2.5A/us
Vout (20mV/div)
Iout (2A/div)
Vout (20mV/div)
Vin=12V, Vout=1.2V
Iout from 0A to 3A, 2.5A/us
Iout (2A/div)
Figure 25. FAN2306 Load Transient from 0% to 50%
Load Current
Figure 26. Load Transient from 50% to 100%
Load Current
Vout (20mV/div)
Vin=12V, Vout=1.2V
Iout from 0A to 3A, 2.5A/us
Iout (2A/div)
Figure 27. FAN2306M Load Transient from 0% to 50%
Load Current
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
10
Typical Performance Characteristics
Tested using evaluation board circuit shown in Figure 1 with VIN=12 V, VOUT=1.2 V, fSW=500 kHz, TA=25°C, and no
airflow; unless otherwise specified.
Pull Vout to 1.4V
through 10Ω resistor
PGOOD (5V/div)
Vout (1V/div)
Vfb (0.5V/div)
Vout (1V/div)
Soft Start (1V/div)
Level
1
Level
2
PGOOD (5V/div)
Vsw (10V/div)
IL (5A/div)
Iout=0A then short output
Figure 28. Over-Current Protection with Heavy Load
Figure 29. Over-Voltage Protection Level 1
and Level 2
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
11
Circuit Operation
The FAN2306 uses a constant on-time modulation
where ItON is:
architecture with
a
VIN feed-forward input to
ꢐ
ꢃ
ꢇꢈ
accommodate a wide VIN range. This method provides
fixed switching frequency (fSW) operation when the
inductor operates in Continuous Conduction Mode
(CCM) and variable frequency when operating in Pulse
Frequency Mode (PFM) at light loads. Additional
benefits include excellent line and load transient
response, cycle-by-cycle current limiting, and eliminated
need for loop compensation.
ꢎꢍꢄꢈ
ꢂ
ꢉ
ꢋꢋꢋꢋꢋ
(3)
ꢐꢑ ꢒꢓꢔꢕꢖ
where RFREQ is the frequency-setting resistor
described in the Setting Switching Frequency section;
CtON is the internal 2.2 pF capacitor; and ItON is the VIN
feed-forward current that generates the on-time.
The FAN2306 implements open-circuit detection on the
FREQ pin to protect the output from an infinitely long
on-time. In the event the FREQ pin is left floating,
switching of the regulator is disabled. The FAN2306 is
designed for VIN input range 4.5 to 18 V, fSW 200 kHz to
1.5 MHz, resulting in an ItON ratio of 1 to 25.
At the beginning of each cycle, FAN2306 turns on the
high-side MOSFET (HS) for a fixed duration (tON). At the
end of tON, HS turns off for a duration (tOFF) determined
by the operating conditions. Once the FB voltage (VFB)
falls below the reference voltage (VREF), a new switching
cycle begins.
As the ratio of VOUT to VIN increases, tOFF,min introduces a
limit on the maximum switching frequency as calculated
in the following equation, where the factor 1.2 is
included in the denominator to add some headroom for
transient operation:
The modulator provides a minimum off-time (tOFF-MIN) of
320 ns to provide a guaranteed interval for low-side
MOSFET (LS) current sensing and PFM operation. tOFF-
is also used to provide stability against multiple
MIN
ꢃꢄꢅꢆ
ꢇꢈꢚꢛꢜꢝ
pulsing and limits maximum switching frequency during
transient events.
ꢘꢐ ꢙ
ꢞ
ꢃ
(4)
ꢀꢁ
ꢗ
ꢐꢟꢏ ꢉ ꢊꢄꢓꢓꢚꢛꢜꢝ
Enable
Soft-Start (SS)
The enable pin is TTL compatible, which supports low-
shutdown-current applications, such as notebooks. VCC
should be applied after VIN / PVIN is applied to the
circuit.
A conventional soft-start ramp is implemented to provide
a controlled startup sequence of the output voltage. A
current is generated on the SS pin to charge an external
capacitor. The lesser of the voltage on the SS pin and
the reference voltage is used for output regulation.
The EN pin can be directly driven by logic voltages of
5 V, 3.3 V, 2.5 V, etc. If the EN pin is driven by 5V logic,
a small current flows into the pin when the EN pin
voltage exceeds the internal clamp voltage of 4.3 V. To
eliminate clamp current flowing into the EN pin use a
voltage divider to limit the EN pin voltage to < 4 V.
To reduce VOUT ripple and achieve a smoother ramp of
the output voltage, tON is modulated during soft-start. tON
starts at 50% of the steady-state on-time (PWM Mode)
and ramps up to 100% gradually.
During normal operation, the SS voltage is clamped to
400 mV above the FB voltage. The clamp voltage drops
to 40 mV during an overload condition to allow the
converter to recover using the soft-start ramp once the
overload condition is removed. On-time modulation
during SS is disabled when an overload condition exists.
Constant On-time Modulation
The FAN2306 uses a constant on-time modulation
technique, in which the HS MOSFET is turned on for a
fixed time, set by the modulator, in response to the input
voltage and the frequency setting resistor. This on-time
is proportional to the desired output voltage, divided by
the input voltage. With this proportionality, the frequency
is essentially constant over the load range where
inductor current is continuous.
To maintain a monotonic soft-start ramp, the regulator is
forced into PFM Mode during soft-start. The minimum
frequency clamp is disabled during soft-start.
The nominal startup time is programmable through an
internal current source charging the external soft-start
For buck converter in Continuous-Conduction Mode
(CCM), the switching frequency fSW is expressed as:
capacitor CSS
:
ꢎꢀꢀ ꢉ ꢊꢀꢀ
ꢃꢔꢕꢓ
ꢃꢄꢅꢆ
ꢌꢀꢀ
ꢂ
ꢋꢋꢋꢋꢋ
ꢀꢁ
ꢂ
ꢋꢋꢋꢋꢋ
(5)
(1)
ꢃ
ꢇꢈ ꢉ ꢊꢄꢈ
The on-time generator sets the on-time (tON) for the
high-side MOSFET, which results in the switching
frequency of the regulator during steady-state operation.
To maintain a relatively constant switching frequency
over a wide range of input conditions, the input voltage
information is fed into the on-time generator.
where:
External soft-start programming capacitor;
CSS
ISS
=
=
Internal soft-start charging current source,
10 A;
Soft-start time; and
tSS
=
=
600 mV
tON is determined by:
VREF
ꢌꢍꢄꢈ
ꢊꢄꢈ
ꢂ
ꢉ ꢏꢃꢋꢋꢋꢋꢋ
(2)
ꢎꢍꢄꢈ
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
12
For example; for 1 ms startup time, CSS=15 nF.
Minimum Frequency Clamp
To maintain a switching frequency above the audible
range, the FAN2306 clamps the switching frequency to
a minimum value of 18 kHz. The LS MOSFET is turned
on to discharge the output and trigger a new PWM
cycle. The minimum frequency clamp is disabled during
soft-start. The minimum frequency clamp is not enabled
in the FAN2306M, allowing this device to operate at
lower frequencies as the load decreases to extremely
small levels, delivering higher efficiency operation.
The soft-start option can be used for ratiometric tracking.
When EN is LOW, the soft-start capacitor is discharged.
Startup on Pre-Bias
FAN2306 allows the regulator to start on a pre-bias
output, VOUT, and ensures VOUT is not discharged during
the soft-start operation
To guarantee no glitches on VOUT at the beginning of the
soft-start ramp, the LS is disabled until the first positive-
going edge of the PWM signal. The regulator is also
forced into PFM Mode during soft-start to ensure the
inductor current remains positive, reducing the
possibility of discharging the output voltage.
Protection Features
The converter output is monitored and protected against
over-current, over-voltage, under-voltage, and high-
temperature conditions.
Over-Current Protection (OCP)
PVCC
The FAN2306 uses current information through the LS
to implement valley-current limiting. While an OC event
is detected, the HS is prevented from turning on and the
LS is kept on until the current falls below the user-
defined set point. Once the current is below the set
point, the HS is allowed to turn on.
The FAN2306 requires an external source connected to
PVCC to supply power to the internal gate drivers. The
PVCC pin should be bypassed with a 2.2 µF ceramic
capacitor. PVCC should be applied after the input voltage
is applied to the circuit.
VCC Bias Supply and UVLO
During an OC event, the output voltage may droop if the
load current is greater than the current the converter is
providing. If the output voltage drops below the UV
threshold, an overload condition is triggered. During an
overload condition, the SS clamp voltage is reduced to
40 mV and the on-time is fixed at the steady-state
duration. By nature of the control method; as VOUT drops,
the switching frequency is lower due to the reduced rate
of inductor current decay during the off-time.
The VCC rail supplies power to the controller. It is
generally connected to the PVCC rail through a low-
pass filter of a 10 resistor and 0.1 F capacitor to
minimize any noise sources from the driver supply.
An Under-Voltage Lockout (UVLO) circuit monitors the
VCC voltage to ensure proper operation. Once the VCC
voltage is above the UVLO threshold, the part begins
operation after an initialization routine of 50 µs. There is
no UVLO circuitry on either the PVCC or VIN rails.
The ILIM pin has an open-detection circuit to provide
protection against operation without a current limit.
Pulse Frequency Modulation (PFM)
Under-Voltage Protection (UVP)
One of the key benefits of using a constant on-time
modulation scheme is the seamless transitions in and
out of Pulse Frequency Modulation (PFM) Mode. The
PWM signal is not slave to a fixed oscillator and,
therefore, can operate at any frequency below the target
steady-state frequency. By reducing the frequency
during light-load conditions, the efficiency can be
significantly improved.
If VFB is below the under-voltage threshold of -11% VREF
(534 mV), the part enters UVP and PGOOD pulls LOW.
Over-Voltage Protection (OVP)
There are two levels of OV protection: +11% and +22%.
During an OV event, PGOOD pulls LOW.
When VFB is > +11% of VREF (666 mV), both HS and LS
turn off. By turning off the LS during an OV event, VOUT
overshoot can be reduced when there is positive
inductor current by increasing the rate of discharge.
Once the VFB voltage falls below VREF, the latched OV
signal is cleared and operation returns to normal.
The FAN2306 provides a Zero-Crossing Detector (ZCD)
circuit to identify when the current in the inductor
reverses direction. To improve efficiency at light load,
the LS MOSFET is turned off around the zero crossing
to eliminate negative current in the inductor. For
predictable operation entering PFM mode the controller
waits for nine consecutive zero crossings before
allowing the LS MOSFET to turn off.
A second over-voltage detection is implemented to
protect the load from more serious failure. When VFB
rises +22% above the VREF (732 mV), the HS turns off,
but the LS is forced on until a power cycle on VCC.
In PFM Mode, fSW varies or modulates proportionally to
the load; as load decreases, fSW also decreases. The
switching frequency, while the regulator is operating in
PFM, can be expressed as:
Over-Temperature Protection (OTP)
FAN2306 incorporates an over-temperature protection
circuit that disables the converter when the die
temperature reaches 155°C. The IC restarts when the
die temperature falls below 140°C.
ꢏ ꢉ ꢠ ꢉ ꢎꢄꢅꢆ
ꢃꢄꢅꢆ
ꢀꢁ
ꢂ
ꢉ
ꢋꢋꢋꢋ
(6)
ꢊꢄꢡꢈ ꢉ ꢢꢃꢇꢈ ꢙ ꢃꢄꢅꢆ
ꢣ
ꢃ
ꢇꢈ
where L is inductance and IOUT is output load current.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
13
Power Good (PGOOD)
5 V PVCC
The PGOOD pin serves as an indication to the system
that the output voltage of the regulator is stable and
within regulation. Whenever VOUT is outside the
regulation window or the regulator is at over-
temperature (UV, OV, and OT), the PGOOD pin is
pulled LOW.
The PVCC is supplied from an external source to provide
power to the drivers and VCC. It is crucial to keep this pin
decoupled to PGND with a ≥1 µF X5R or X7R ceramic
capacitor. Because VCC powers internal analog circuit, it
is filtered from PVCC with a 10 Ω resistor and 0.1 µF X7R
decoupling ceramic capacitor to AGND.
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation or when OT is detected.
Setting the Output Voltage (VOUT
)
The output voltage VOUT is regulated by initiating a high-
side MOSFET on-time interval when the valley of the
divided output voltage appearing at the FB pin reaches
VREF. Since this method regulates at the valley of the
output ripple voltage, the actual DC output voltage on
VOUT is offset from the programmed output voltage by the
average value of the output ripple voltage. The initial VOUT
setting of the regulator can be programmed from 0.6 V to
5.5 V by an external resistor divider (R3 and R4):
Application Information
Stability
Constant on-time stability consists of two parameters:
stability criterion and sufficient signal at VFB.
Stability criterion is given by:
ꢊꢄꢈ
(7)
(8)
ꢒꢕꢀꢔ ꢉ ꢌꢄꢅꢆ
ꢤ
ꢋꢋꢋ
ꢒꢪ
ꢏ
ꢒꢩ ꢂ
(13)
ꢃ
ꢸ
ꢄꢅꢆꢹ ꢙ ꢐ
Sufficient signal requirement is given by:
ꢃꢔꢕꢓ
ꢥꢎꢇꢈꢦ ꢉ ꢒꢕꢀꢔ ꢧ ꢥꢃꢓꢨꢋꢋꢋꢋ
where VREF is 600 mV.
where IIND is the inductor current ripple and VFB is
the ripple voltage on VFB, which should be ≥12 mV.
For example; for 1.2 V VOUT and 10 k R3, then R4 is
10 k. For 600 mV VOUT, R4 is left open. VFB is
trimmed to a value of 596 mV when VREF=600 mV, so
the final output voltage, including the effect of the output
ripple voltage, can be approximated by the equation:
In certain applications, especially designs utilizing only
ceramic output capacitors, there may not be sufficient
ripple magnitude available on the feedback pin for
stable operation. In this case, an external circuit, such
as R2-C4-C5 shown in Figure 1, can be added to inject
ripple voltage into the FB pin.
ꢃ
ꢒꢪ
ꢃꢄꢅꢆꢋ ꢂ ꢃꢓꢨꢋ ꢉ ꢺꢐ ꢶ ꢻ ꢶ ꢺ ꢼꢜꢽꢻ
ꢒꢩ
(14)
ꢏ
There are some specific considerations when selecting
the RCC ripple injector circuit. For typical applications,
the value of C4 can be selected as 0.1 µF and
approximate values for R2 and C5 can be determined
using the following equations.
Setting the Switching Frequency (fSW)
fSW is programmed through external RFREQ as follows:
ꢃꢄꢅꢆ
ꢒꢓꢔꢕꢖ
ꢂ
ꢋ
(15)
ꢏꢑ ꢉ ꢌꢍꢄꢈ ꢉ
ꢀꢁ
R2 must be small enough to develop 12 mV of ripple:
where CtON=2.2 pF internal capacitor that generates
tON. For example; for fSW=500 kHz and VOUT=1.2 V,
select a standard resistor value for RFREQ=54.9 k.
ꢢ
ꢣ
ꢃ
ꢇꢈ ꢙ ꢃꢄꢅꢆ ꢉ ꢃꢄꢅꢆ
ꢒꢏ ꢗ
(9)
ꢃꢇꢈ ꢉ ꢑꢟꢑꢐꢏꢃ ꢉ ꢌꢩ ꢉ
ꢀꢁ
Inductor Selection
R2 must also be selected such that the R2C4 time
constant enables stable operation:
The inductor is typically selected based on the ripple
current (IL), which is approximately 25% to 45% of the
maximum DC load. The inductor current rating should
be selected such that the saturation and heating current
ratings exceed the intended currents encountered in the
application over the expected temperature range of
operation. Regulators that require fast transient
response use smaller inductance and higher current
ripple; while regulators that require higher efficiency
keep ripple current on the low side.
ꢑꢟꢪꢪ ꢉ ꢏꢫ ꢉ ꢀꢁ ꢉ ꢠꢄꢅꢆ ꢉ ꢌꢄꢅꢆ
(10)
ꢒꢏ ꢗ
ꢌꢩ
The minimum value of C5 can be selected to minimize
the capacitive component of ripple appearing on the
feedback pin:
ꢱꢲꢳꢴ ꢉ ꢬꢲꢳꢴ ꢉ ꢢꢵꢪ ꢶ ꢵꢩꢣ
(11)
ꢬꢭꢮꢯꢰ
ꢂ
ꢵꢏ ꢉ ꢵꢪ ꢉ ꢵꢩ ꢉ ꢬꢩ
The inductor value is given by:
Using the minimum value of C5 generally offers the best
transient response, and 100 pF is a good initial value in
many applications. Under some operating conditions,
excessive pulse jitter may be observed. To reduce jitter
and improve stability, the value of C5 can be increased:
ꢢꢃꢇꢈ ꢙ ꢃꢄꢅꢆꢣ ꢃꢄꢅꢆ
ꢠ ꢂ
ꢉ
ꢋ
(16)
ꢥꢎꢾ ꢉ
ꢃ
ꢇꢈ
ꢀꢁ
For example: for 12 V VIN, 1.2 V VOUT, 6 A load, 30%
IL, and 500 kHz fSW; L is 1.2 µH.
(12)
ꢌꢭ ꢷ ꢏ ꢉ ꢬꢭꢮꢯꢰ
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
14
requirements, the output capacitor value may be
reduced and comprised of low-cost 22 µF capacitors.
Input Capacitor Selection
Input capacitor CIN is selected based on voltage rating,
RMS current ICIN(RMS) rating, and capacitance. For
capacitors having DC voltage bias derating, such as
ceramic capacitors, higher rating is strongly
recommended. RMS current rating is given by:
Setting the Current Limit
Current limit is implemented by sensing the inductor
valley current across the LS MOSFET VDS during the LS
on-time. The current limit comparator prevents a new
on-time from being started until the valley current is less
than the current limit.
ꢎꢿꢇꢈꢢꢔꣀꢀꢣ ꢂ ꢎꢾꢄꣁꢦꣂꣀꣁꣃ ꢉ ꣄ꣅ ꢉ ꢢꢐ ꢙ ꣅꢣꢋꢋꢋꢋꢋꢋꢋ
(17)
where ILOAD-MAX is the maximum load current and D is
the duty cycle VOUT/VIN. The maximum ICIN(RMS) occurs
at 50% duty cycle.
The set point is configured by connecting a resistor from
the ILIM pin to the SW pin. A trimmed current is output
onto the ILIM pin, which creates a voltage across the
resistor. When the voltage on ILIM goes negative, an
over-current condition is detected.
The capacitance is given by:
ꢎꢾꢄꣁꢦꣂꣀꣁꣃ ꢉ ꣅ ꢉ ꢢꢐ ꢙ ꣅꢣ
ꢌꢇꢈ
ꢂ
ꢋꢋꢋꢋꢋꢋ
(18)
RILIM is calculated by:
ꢀꢁ ꢉ ꢥꢃ
ꢇꢈ
where VIN is the input voltage ripple, normally 1%
ꢒꢇꢾꢇꣀ ꢂ ꢐꢟꢑꢏ ꢉ ꢇꢾꢇꣀ ꢋꢎꣁꢾꢾꢕ
(20)
of VIN.
where KILIM is the current source scale factor, and
IVALLEY is the inductor valley current when the current
limit threshold is reached. The factor 1.02 accounts
for the temperature offset of the LS MOSFET
compared to the control circuit.
For example; for VIN=12 V, VIN=120 mV, VOUT=1.2 V,
6 A load, and fSW=500 kHz; CIN is 9 F and is ICIN(RMS) is
1.8 ARMS
.
Select two 10 F 25 V-rated ceramic
capacitors with X7R or similar dielectric, recognizing
that the capacitor DC bias characteristic indicates that
the capacitance value falls approximately 40% at
VIN=12 V. Also, the 10 µF X7R capacitor can carry over
3 ARMS in the frequency range from 100 kHz to 1 MHz,
exceeding the input capacitor current rating
requirements. An additional 0.1 F capacitor may be
needed to suppress noise generated by high frequency
switching transitions.
With the constant on-time architecture, HS is always
turned on for a fixed on-time; this determines the peak-
to-peak inductor current.
Current ripple I is given by:
ꢢꢃꢇꢈ ꢙ ꢃꢄꢅꢆꢣ ꢉꢋꢊꢄꢈ
ꢥꢎꢾ ꢂ
ꢋꢋꢋꢋꢋꢋ
(21)
ꢠ
From the equation above, the worst-case ripple occurs
during an output short circuit (where VOUT is 0 V). This
should be taken into account when selecting the current
limit set point.
Output Capacitor Selection
Output capacitor COUT is also selected based on voltage
rating, RMS current ICOUT(RMS) rating, and capacitance.
For capacitors having DC voltage bias derating, such as
The FAN2306 uses valley-current sensing, the current
limit (IILIM) set point is the valley (IVALLEY).
ceramic
capacitors,
higher
rating
is
highly
recommended.
The valley current level for calculating RILIM is given by:
When calculating COUT
,
usually the dominant
ꢥꢎꢾ
(22)
ꢎꣁꢾꢾꢕ ꢂ ꢎꢾꢄꣁꢦꢋꢢꢿꢾꢣ
ꢙ
ꢋꢋ
requirement is the current load step transient. If the
unloading transient requirement (IOUT transitioning from
HIGH to LOW), is satisfied, then the load transient (IOUT
transitioning LOW to HIGH), is also usually satisfied.
The unloading COUT calculation, assuming COUT has
negligible parasitic resistance and inductance in the
circuit path, is given by:
ꢏ
where ILOAD
is the DC load current when the
current-limit threshold is reached.
(CL)
For example: In a converter designed for 6 A steady-
state operation and 1.8 A current ripple, the current-limit
threshold could be selected at 120% of ILOAD,(SS) to
accommodate transient operation and inductor value
decrease under loading. As a result, ILOAD,(SS) is 7.2 A,
IVALLEY=6.3 A, and RILIM is selected as the standard
value of 1.50 kΩ
ꢎꣀꢡ ꣁꣃ ꢙ ꢎꣀꢡ ꢇꢈ
ꢢꢃꢄꢅꢆ ꢶ ꢥꢃꢄꢅꢆꢣꢡ ꢙ ꢃꢄꢡꢅꢆ
ꢌꢄꢅꢆ ꢂ ꢠ ꢉ
ꢋꢋꢋꢋꢋꢋꢋꢋ
(19)
where IMAX and IMIN are maximum and minimum load
steps, respectively and VOUT is the voltage
overshoot, usually specified at 3 to 5%.
Boot Resistor
In some applications, especially with higher input voltage,
the VSW ring voltage may exceed derating guidelines of
80% to 90% of absolute rating for VSW. In this situation, a
resistor can be connected in series with the boot
capacitor (C3 in Figure 1) to reduce the turn-on speed of
the high-side MOSFET to reduce the amplitude of the
VSW ring voltage.
For example: for VI=12 V, VOUT=1.2 V, 4 A IMAX, 2 A IMIN
,
fSW=500 kHz, LOUT=1.2 µH, and 3% VOUT ripple of
36 mV; the COUT value is calculated to be 164 F. This
capacitor requirement can be satisfied using four 47 µF,
6.3 V-rated X5R ceramic capacitors. This calculation
applies for load current slew rates faster than the
inductor current slew rate, which can be defined as
VOUT/L during the load current removal. For reduced
load current slew rates and / or reduced transient
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
15
PCB (Printed Circuit Board) Layout Guidelines
The following should be considered before beginning a
PCB layout using the FAN2306/FAN2306M. A sample
PCB layout from the evaluation board is shown in Figure
30 - Figure 33 following the layout guidelines.
from the input capacitor to PVIN, through the internal
MOSFETs, and returning to the input capacitor. The
input capacitor should be placed as close to the PVIN
terminals as possible.
Power components consisting of the input capacitors,
output capacitors, inductor, and FAN2306 or FAN2306M
device should be placed on a common side of the PCB
in close proximity to each other and connected using
surface copper.
The current return path from PGND at the low-side
MOSFET source to the negative terminal of the input
capacitor can be routed under the inductor and also
through vias that connect the input capacitor and low-
side MOSFET source to the PGND region under the
power portion of the IC.
Sensitive analog components including SS, FB, ILIM,
FREQ, and EN should be placed away from the high-
voltage switching circuits, such as SW and BOOT, and
connected to their respective pins with short traces.
The SW node trace that connects the source of the
high-side MOSFET and the drain of the low-side
MOSFET to the inductor should be short and wide.
The inner PCB layer closest to the device should have
power ground (PGND) under the power processing
portion of the device (PVIN, SW, and PGND). This inner
PCB layer should have a separate analog ground
(AGND) under the P1 pad and the associated analog
components. AGND and PGND should be connected
together near the IC between PGND pins 18-21 and
AGND pin 23, which connects to P1 thermal pad.
To control the voltage across the output capacitor, the
output voltage divider should be located close to the FB
pin, with the upper FB voltage divider resistor connected
to the positive side of the output capacitor, and the
bottom resistor should be connected to the AGND
portion of the device.
When using ceramic capacitor solutions with external
ramp injection circuitry (R2, C4, C5 in Figure 1), R2 and
C4 should be connected near the inductor and coupling
capacitor C5 should be placed near FB pin to minimize
FB pin trace length.
The AGND thermal pad (P1) should be connected to
AGND plane on inner layer using four 0.25mm vias
spread under the pad. No vias are included under PVIN
(P2) and SW (P3) to maintain the PGND plane under
the power circuitry intact.
Decoupling capacitors for PVCC and VCC should be
located close to their respective device pins.
Power circuit loops that carry high currents should be
arranged to minimize the loop area. Primary focus
should be directed to minimize the loop for current flow
SW node connections to BOOT, ILIM, and ripple
injection resistor R2 should be through separate traces.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
16
Figure 30. Evaluation Board Top Layer Copper
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
17
Figure 31. Evaluation Board Inner Layer 1 Copper
Figure 32. Evaluation Board Inner Layer 2 Copper
Figure 33. Evaluation Board Bottom Layer Copper
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN2306 / FAN2306M • Rev. 1.15
18
5.50±0.10
26
18
1.05±0.10
17
10
27
34
(30X)
0.25±0.05
5.00±0.10
0.25±0.05
0.025±0.025
1
9
SEATING
PLANE
PIN#1
INDICATOR
SEE
DETAIL 'A'
SCALE: 2:1
1.58±0.01
(0.43)
2.18±0.01
(0.35)
0.50±0.01
9
1
(0.25)
0.40±0.01 (30X)
(0.35) 34
10
0.68±0.01
(0.35)
3.50±0.01
2.58±0.01
(1.75)
17
(0.33)
(0.35)
(0.75)
27
0.43±0.01
18
26
(0.35)
(0.25)
(3X)
(0.28)
(0.24)
NOTES: UNLESS OTHERWISE SPECIFIED
A) NO INDUSTRY REGISTRATION APPLIES.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
1.75±0.01
E) DRAWING FILE NAME: MKT-PQFN34AREV2
F) FAIRCHILD SEMICONDUCTOR
5.70
2.18
2.10
1.58
(0.35)
0.55 (30X)
1.80
26
18
0.55
17
27
(1.75)
2.58
0.68
4.10 3.50
5.20
3.60
0.75
(1.85)
34
10
1
9
(0.30)
(0.35)
0.20
0.30 (30X)
0.50±0.05
0.43
(0.08)
4.10
LAND PATTERN
RECOMMENDATION
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