FAN3121CMX [ONSEMI]
CMOS 输入、单通道同相输入、11.4 A 峰值灌电流、10.6 A 源电流低端栅极驱动器;
| 型号： | FAN3121CMX |
| 厂家： | 
ONSEMI |
| 描述： | CMOS 输入、单通道同相输入、11.4 A 峰值灌电流、10.6 A 源电流低端栅极驱动器 栅极驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总21页 (文件大小：2112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Gate Drivers, High-Speed,
Low-Side, Single 9-A
FAN3121, FAN3122
Description
The FAN3121 and FAN3122 MOSFET drivers are designed to drive
N−channel enhancement MOSFETs in low−side switching
applications by providing high peak current pulses. The drivers are
available with either TTL input thresholds (FAN312xT) or
VDD−proportional CMOS input thresholds (FAN312xC). Internal
circuitry provides an under−voltage lockout function by holding the
output low until the supply voltage is within the operating range.
FAN312x drivers incorporate the MillerDrive™ architecture for the
final output stage. This bipolar / MOSFET combination provides the
highest peak current during the Miller plateau stage of the MOSFET
turn−on / turn−off process.
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WDFN8 3x3, 0.65P
CASE 511CD
1
8
SOIC8
CASE 751EB
1
The FAN3121 and FAN3122 drivers implement an enable function
on pin 3 (EN), previously unused in the industry−standard pin−out.
MARKING DIAGRAM
The pin is internally pulled up to V for active HIGH logic and can
DD
be left open for standard operation.
8
The commercial FAN3121/22 is available in a 3x3 mm 8−lead
thermally−enhanced MLP package or an 8−lead SOIC package with
the option for an exposed pad.
XXXXX
XXXXX
ALYWG
G
XXXXX
AYWWG
G
1
Features
WDFN8
SOIC8
• Industry−Standard Pin−out with Enable Input
• 4.5−V to 18−V Operating Range
A
L
Y
W
G
= Assembly Location
= Wafer Lot
• 11.4 A Peak Sink at V = 12 V
DD
= Year
= Work Week
= Pb−Free Package
• 9.7−A Sink / 7.1−A Source at V
= 6 V
OUT
• Inverting Configuration (FAN3121) and
• Non−Inverting Configuration (FAN3122)
• Internal Resistors Turn Driver Off if No Inputs
• 23−ns / 19−ns Typical Rise/Fall Times (10 nF Load)
• 18 ns to 23 ns Typical Propagation Delay Time
• Choice of TTL or CMOS Input Thresholds
• MillerDrive Technology
(Note: Microdot may be in either location)
*This information is generic. Please refer to device
data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of
this data sheet.
• Available in Thermally Enhanced 3x3 mm 8−Lead
• MLP or 8−Lead SOIC Package (Pb−Free Finish)
• Rated from –40°C to +125°C
• These are Pb−Free Devices
Applications
• Synchronous Rectifier Circuits
• High−Efficiency MOSFET Switching
• Switch−Mode Power Supplies
• DC−to−DC Converters
• Motor Control
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
July, 2020 − Rev. 2
FAN3121/D
FAN3121, FAN3122
PIN CONFIGURATIONS
VDD
IN
VDD
OUT
VDD
IN
VDD
OUT
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
EN
EN
OUT
GND
OUT
GND
GND
GND
Figure 1. FAN3121 Pin Configuration
Figure 2. FAN3122 Pin Configuration
PACKAGE OUTLINES
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
Figure 3. 3x3 mm MLP−8 (Top View)
Figure 4. SOIC−8 (Top View)
THERMAL CHARACTERISTICS (Note 1)
Q
JL
Q
JT
Q
JA
Y
JB
Y
JT
(Note 2)
(Note 3)
(Note 4)
(Note 5)
(Note 6)
Package
Unit
°C/W
°C/W
8−Lead 3x3 mm Molded Leadless Package (MLP)
8−Pin Small Outline Integrated Circuit (SOIC)
1.2
64
42
2.8
0.7
38
29
87
41
2.3
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (Q ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)
JL
that are typically soldered to a PCB.
3. Theta_JT (Q ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform
JT
temperature by a top−side heatsink.
4. Theta_JA (Q ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given
JA
is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51−2, JESD51−5, and JESD51−7,
as appropriate.
5. Psi_JB (Y ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application
JB
circuit board reference point for the thermal environment defined in Note 4. For the MLP−8 package, the board reference is defined as the
PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC−8 package, the board reference
is defined as the PCB copper adjacent to pin 6.
6. Psi_JT (Y ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of
JT
the top of the package for the thermal environment defined in Note 4.
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2
FAN3121, FAN3122
PIN DEFINITIONS
FAN3121 FAN3122 Name
Description
3
3
EN
Enable Input. Pull pin LOW to inhibit driver. EN has logic thresholds for both TTL and CMOS IN
thresholds.
4, 5
2
4, 5
2
GND Ground. Common ground reference for input and output circuits.
IN
Input.
Gate Drive Output. Held LOW unless required input is present and V is above the UVLO threshold.
6, 7
OUT
OUT
DD
6, 7
1, 8
Gate Drive Output (inverted from the input). Held LOW unless required input is present and V is
above the UVLO threshold.
DD
1, 8
V
DD
Supply Voltage. Provides power to the IC.
P1
Thermal Pad (MLP only). Exposed metal on the bottom of the package; it is recommended to connect
externally on the PCB the Exposed Pad together with the Ground. NOT suitable for carrying current.
VDD
IN
VDD
VDD
IN
VDD
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
OUT
OUT
GND
OUT
OUT
GND
EN
EN
GND
GND
Figure 5. FAN3121 Pin Assignments (Repeated)
Figure 6. FAN3122 Pin Assignments (Repeated)
OUTPUT LOGIC
FAN3121
FAN3122
EN
IN
OUT
EN
IN
OUT
0
0
0
0
1
0
0
0 (Note 7)
0
0
0
1
0
1 (Note 7)
0
0
1
0 (Note 7)
1
1 (Note 7)
1 (Note 7)
1 (Note 7)
1 (Note 7)
1 (Note 7)
7. Default input signal if no external connection is made.
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3
FAN3121, FAN3122
BLOCK DIAGRAM
VDD
1
2
8
VDD
Inverting
(FAN3121)
100 kW
UVLO
VDD_OK
IN
OUT (FAN3121)
OUT (FAN3122)
7
6
100k
OUT (FAN3121)
OUT (FAN3122)
Non−Inverting
(FAN3122)
100 kW
VDD
100 kW
EN
3
4
5
GND
GND
Figure 7. Block Diagram
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
Max
Unit
V
V
V
to GND
20.0
DD
EN
DD
V
EN to GND
IN to GND
GND − 0.3
GND − 0.3
GND − 0.3
−
V
V
V
+ 0.3
+ 0.3
+ 0.3
V
DD
DD
DD
V
V
IN
V
OUT
OUT to GND
V
T
Lead Soldering Temperature (10 Seconds)
Junction Temperature
+260
°C
°C
°C
L
T
−55
+150
+150
J
T
STG
Storage Temperature
−65
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
Supply Voltage Range
Enable Voltage EN
Input Voltage IN
18.0
DD
EN
V
V
DD
V
DD
V
V
IN
0
V
T
A
Operating Ambient Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
FAN3121, FAN3122
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to +125°C unless otherwise noted. Currents are defined as
DD
J
positive into the device and negative out of the device.)
Symbol
SUPPLY
Parameter
Test Condition
Min
Typ
Max
Unit
V
Operating Range
4.5
−
−
18.0
0.90
0.85
4.3
V
DD
DD
I
Supply Current, Inputs / EN Not Connected
TTL
CMOS (Note 8)
0.65
0.58
4.0
mA
−
V
ON
Device Turn−On Voltage (UVLO)
Device Turn−Off Voltage (UVLO)
3.5
3.30
V
V
V
OFF
3.75
4.10
INPUTS (TTL, FAN312XT) (Note 9)
V
INx Logic Low Threshold
INx Logic High Threshold
TTL Logic Hysteresis Voltage
0.8
−
1.0
1.7
−
V
V
V
IL_T
IH_T
V
2.0
V
HYS_T
0.40
0.70
0.85
FAN3121TMX, FAN3122TMX
I
I
Non−Inverting Input Current
IN from 0 to V
IN from 0 to V
−1
−
−
175
1
mA
mA
IN+
DD
Inverting Input Current
−175
IN−
DD
INPUTS (CMOS, FAN312xC) (Note 9)
V
INx Logic Low Threshold
30
−
38
55
17
−
%V
%V
%V
IL_C
IH_C
DD
DD
DD
V
INx Logic High Threshold
CMOS Logic Hysteresis Voltage
70
24
V
12
HYS_C
FAN3121CMX, FAN3122CMX
I
Non−Inverting Input Current
IN from 0 to V
IN from 0 to V
−1
−
−
175
1
mA
IN+
DD
I
Inverting Input Current
−175
mA
IN−
DD
ENABLE (FAN3121, FAN3122)
V
Enable Logic Low Threshold
EN from 5 V to 0 V
EN from 0 V to 5 V
1.2
1.8
0.2
68
8
1.6
2.2
0.6
100
17
2.0
2.6
0.8
134
27
V
V
ENL
ENH
V
Enable Logic High Threshold
V
HYS_T
TTL Logic Hysteresis Voltage
Enable Pull−up Resistance
V
R
kW
ns
ns
PU
t
t
, t
Propagation Delay, CMOS EN (Note 10)
Propagation Delay, TTL EN (Note 10)
D1 D2
, t
14
21
33
D1 D2
OUTPUTS
I
OUT Current, Mid−Voltage, Sinking (Note 11)
OUT at V / 2, C
= 1.0 mF,
= 1.0 mF,
−
−
9.7
7.1
−
−
A
A
SINK
DD
LOAD
f = 1 kHz
I
OUT Current, Mid−Voltage, Sourcing (Note 11)
OUT at V / 2, C
SOURCE
DD
LOAD
f = 1 kHz
I
OUT Current, Peak, Sinking (Note 11)
OUT Current, Peak, Sourcing (Note 11)
Output Rise Time (Note 10)
C
C
C
C
= 1.0 mF, f = 1 kHz
= 1.0 mF, f = 1 kHz
= 10 nF
−
−
11.4
10.6
23
−
−
A
A
PK_SINK
LOAD
LOAD
LOAD
LOAD
I
PK_SOURCE
t
t
18
11
9
29
27
28
35
−
ns
ns
ns
ns
mA
RISE
Output Fall Time (Note 10)
= 10 nF
19
FALL
t
t
t
Output Propagation Delay, CMOS Inputs (Note 10) 0 – 12 V , 1 V/ns Slew Rate
18
D1, D2
IN
t
Output Propagation Delay, TTL Inputs (Note 10)
Output Reverse Current Withstand (Note 11)
0 – 5 V , 1 V/ns Slew Rate
9
23
D1, D2
IN
I
1500
−
RVS
8. Lower supply current due to inactive TTL circuitry.
9. EN inputs have modified TTL thresholds; refer to the ENABLE section.
10.See Timing Diagrams of Figure 8 and Figure 9.
11. Not tested in production.
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FAN3121, FAN3122
TIMING DIAGRAMS
Input
or
Enable
V
Input
or
Enable
IH
V
IH
V
IL
VIL
tD1
tD2
tD1
tD2
tRISE
tFALL
tFALL
tRISE
90%
10%
90%
10%
Output
Output
Figure 8. Non−Inverting
Figure 9. Inverting
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted)
Figure 10. IDD (Static) vs. Supply Voltage (Note 12)
Figure 11. IDD (Static) vs. Supply Voltage (Note 12)
Figure 12. IDD (No−Load) vs. Frequency
Figure 13. IDD (No−Load) vs. Frequency
Figure 14. IDD (10 nF Load) vs. Frequency
Figure 15. IDD (10 nF Load) vs. Frequency
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
Figure 16. IDD (Static) vs. Temperature (Note 12)
Figure 18. Input Thresholds vs. Supply Voltage
Figure 20. Input Thresholds % vs. Supply Voltage
Figure 17. IDD (Static) vs. Temperature (Note 12)
Figure 19. Input Thresholds vs. Supply Voltage
Figure 21. Enable Thresholds vs. Supply Voltage
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
Figure 22. CMOS Input Thresholds vs. Temperature
Figure 23. TTL Input Thresholds vs. Temperature
Figure 24. TTL Input Thresholds vs. Temperature
Figure 25. UVLO Thresholds vs. Temperature
IN Fall to OUT Rise
IN Rise to OUT Fall
Figure 26. UVLO Hysteresis vs. Temperature
Figure 27. Propagation Delay vs. Supply Voltage
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
IN Fall to OUT Rise
IN Rise to OUT Rise
IN Rise to OUT Fall
IN Fall to OUT Fall
Figure 28. Propagation Delay vs. Supply Voltage
Figure 29. Propagation Delay vs. Supply Voltage
IN Rise to OUT Rise
EN Rise to OUT Rise
EN Fall to OUT Fall
IN Fall to OUT Fall
Figure 30. Propagation Delay vs. Supply Voltage
Figure 31. Propagation Delay vs. Supply Voltage
IN Rise to OUT Rise
IN Rise to OUT Rise
IN Fall to OUT Fall
IN Fall to OUT Fall
Figure 32. Propagation Delays vs. Temperature
Figure 33. Propagation Delays vs. Temperature
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
Figure 34. Propagation Delays vs. Temperature
Figure 35. Propagation Delays vs. Temperature
EN Rise to OUT Rise
EN Fall to OUT Fall
Figure 36. Propagation Delays vs. Temperature
Figure 37. Fall Time vs. Supply Voltage
Figure 38. Rise Time vs. Supply Voltage
Figure 39. Rise and Fall Time vs. Temperature
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FAN3121, FAN3122
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) (continued)
Figure 40. Rise / Fall Waveforms with 10 nF Load
Figure 41. Quasi−Static Source Current with
DD = 12 V (Note 13)
V
Figure 42. Quasi−Static Sink Current with
Figure 43. Quasi−Static Source Current with
V
DD = 12 V (Note 13)
VDD = 8 V (Note 13)
VDD
470 mF
Al. El.
(2) x 4.7 μF
ceramic
Current Probe
LACROU AP015
FAN3121/22
IOUT
IN
1 kHz
1 mF
ceramic
CLOAD
1 mF
VOUT
Figure 44. Quasi−Static Sink Current with
DD = 8 V (Note 13)
Figure 45. Quasi−Static IOUT / VOUT Test Circuit
V
12.For any inverting inputs pulled LOW, non−inverting inputs pulled HIGH, or outputs driven HIGH; static I increases by the current flowing
DD
through the corresponding pull−up/down resistor, shown in Figure 7.
13.The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current−measurement loop.
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12
FAN3121, FAN3122
APPLICATIONS INFORMATION
The FAN3121 and FAN3122 family offers versions in
either TTL or CMOS input configuration. In the FAN3121T
and FAN3122T, the input thresholds meet
industry−standard TTL−logic thresholds independent of the
voltage, and there is a hysteresis voltage of
The purpose of the Miller Drive architecture is to speed up
switching by providing high current during the Miller
plateau region when the gate−drain capacitance of the
MOSFET is being charged or discharged as part of the
turn−on / turn−off process.
V
DD
approximately 0.7 V. These levels permit the inputs to be
driven from a range of input logic signal levels for which a
voltage over 2 V is considered logic HIGH. The driving
signal for the TTL inputs should have fast rising and falling
edges with a slew rate of 6 V/ms or faster, so the rise time
from 0 to 3.3 V should be 550 ns or less.
For applications with zero voltage switching during the
MOSFET turn−on or turn−off interval, the driver supplies
high peak current for fast switching, even though the Miller
plateau is not present. This situation often occurs in
synchronous rectifier applications because the body diode is
generally conducting before the MOSFET is switched on.
The FAN3121 and FAN3122 output can be enabled or
disabled using the EN pin with a very rapid response time.
If EN is not externally connected, an internal pull−up
resistor enables the driver by default. The EN pin has logic
thresholds for parts with either TTL or CMOS IN thresholds.
In the FAN3121C and FAN3122C, the logic input
The output pin slew rate is determined by V voltage and
DD
the load on the output. It is not user adjustable, but a series
resistor can be added if a slower rise or fall time at the
MOSFET gate is needed.
V DD
thresholds are dependent on the V level and, with V of
DD
DD
12 V, the logic rising edge threshold is approximately 55%
of V and the input falling edge threshold is approximately
DD
38% of V . The CMOS input configuration offers a
DD
hysteresis voltage of approximately 17% of V . The
DD
CMOS inputs can be used with relatively slow edges
(approaching DC) if good decoupling and bypass techniques
are incorporated in the system design to prevent noise from
violating the input voltage hysteresis window. This allows
setting precise timing intervals by fitting an R−C circuit
between the controlling signal and the IN pin of the driver.
The slow rising edge at the IN pin of the driver introduces
a delay between the controlling signal and the OUT pin of
the driver.
Input
stage
V OUT
Static Supply Current
In the I (static) Typical Performance Characteristics,
DD
the curves are produced with all inputs / enables floating
Figure 46. Miller Drive Output Architecture
(OUT is LOW) and indicates the lowest static I current
DD
for the tested configuration. For other states, additional
current flows through the 100 kW resistors on the inputs and
outputs, as shown in the block diagram (see Figure 7). In
Under−Voltage Lockout (UVLO)
The FAN312x startup logic is optimized to drive
ground−referenced N−channel MOSFETs with an
under−voltage lockout (UVLO) function to ensure that the
these cases, the actual static I current is the value obtained
DD
from the curves, plus this additional current.
IC starts in an orderly fashion. When V
is rising, yet
DD
below the 4.0 V operational level, this circuit holds the
output low, regardless of the status of the input pins. After
the part is active, the supply voltage must drop 0.25 V before
the part shuts down. This hysteresis helps prevent chatter
MillerDrive Gate−Drive Technology
FAN312x gate drivers incorporate the MillerDrive
architecture shown in Figure 46. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the bulk of
when low V supply voltages have noise from the power
DD
switching. This configuration is not suitable for driving
high−side P−channel MOSFETs because the low output
voltage of the driver would turn the P−channel MOSFET on
the current as OUT swings between 1/3 to 2/3 V and the
MOS devices pull the output to the HIGH or LOW rail.
DD
with V below 4.0 V.
DD
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FAN3121, FAN3122
VDD
VDS
VDD Bypassing and Layout Considerations
The FAN3121 and FAN3122 are available in either 8−lead
SOIC or MLP packages. In either package, the V pins 1
DD
CBYP
and 8 and the GND pins 4 and 5 should be connected
together on the PCB.
FAN3121/2
In typical FAN312x gate−driver applications,
high−current pulses are needed to charge and discharge the
gate of a power MOSFET in time intervals of 50 ns or less.
A bypass capacitor with low ESR and ESL should be
PWM
connected directly between the V
and GND pins to
DD
provide these large current pulses without causing
unacceptable ripple on the V supply. To meet these
requirements in a small size, a ceramic capacitor of 1 mF or
larger is typically used, with a dielectric material such as
X7R, to limit the change in capacitance over the temperature
and / or voltage application ranges.
Figure 47 shows the pulsed gate drive current path when
the gate driver is supplying gate charge to turn the MOSFET
on. The current is supplied from the local bypass capacitor
Figure 48. Current Path for MOSFET Turn−Off
DD
Operational Waveforms
At power up, the FAN3121 inverting driver shown in
Figure 49 holds the output LOW until the V
voltage
DD
reaches the UVLO turn−on threshold, as indicated in
Figure 50. This facilitates proper startup control of low−side
N−channel MOSFETs.
VDD
C
BYP
and flows through the driver to the MOSFET gate and
to ground. To reach the high peak currents possible with the
FAN312x family, the resistance and inductance in the path
IN
OUT
should be minimized. The localized C
acts to contain the
BYP
high peak current pulses within this driver−MOSFET
circuit, preventing them from disturbing the sensitive analog
circuitry in the PWM controller.
Figure 49. Inverting Configuration
VDD
VDS
The OUT pulses’ magnitude follows V magnitude with
DD
the output polarity inverted from the input until steady−state
V
DD
is reached.
CBYP
FAN3121/2
VDD
Turn−on threshold
PWM
IN−
Figure 47. Current Path for MOSFET Turn−On
Figure 48 shows the path the current takes when the gate
driver turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn−off times, the resistance and
inductance in this path should be minimized.
IN+
(VDD
)
OUT
Figure 50. Inverting Startup Waveforms
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FAN3121, FAN3122
At power up, the FAN3122 non−inverting driver, shown
dynamic operating conditions, including pin pull−up /
pull−down resistors, can be obtained using graphs in
Typical Performance Characteristics to determine the
in Figure 51, holds the output LOW until the V voltage
DD
reaches the UVLO turn−on threshold, as indicated in
Figure 52. The OUT pulses magnitude follow V
current I
drawn from V under actual
DD
DYNAMIC
DD
magnitude until steady−state V is reached.
operating conditions:
DD
PDYMANIC + IDYNAMIC @ VDD
(eq. 3)
VDD
Once the power dissipated in the driver is determined, the
driver junction rise with respect to circuit board can be
evaluated using the following thermal equation, assuming
IN
OUT
y
was determined for a similar thermal design (heat
JB
sinking and air flow):
Figure 51. Non−Inverting Driver
TJ + PTOTAL @ YJB ) TB
(eq. 4)
where:
T = driver junction temperature;
J
y
= (psi) thermal characterization parameter relating
VDD
JB
Turn−on threshold
temperature rise to total power dissipation; and
= board temperature in location as defined in the
T
B
Thermal Characteristics table.
In a full−bridge synchronous rectifier application, shown
in Figure 53, each FAN3122 drives a parallel combination
of two high−current MOSFETs, (such as FDMS8660S). The
typical gate charge for each SR MOSFET is 70 nC with
IN−
IN+
V
GS
= V = 9 V. At a switching frequency of 300 kHz, the
DD
total power dissipation is:
PGATE + 2 @ 70 nC @ 9 V @ 300 kHz + 0.378 W
(eq. 5)
(eq. 6)
(eq. 7)
PDYNAMIC + 2 mA @ 9 V + 18 mW
PTOTAL + 0.396 W
OUT
The SOIC−8 has
a
junction−to−board thermal
characterization parameter of y = 42°C/W. In a system
Figure 52. Non−Inverting Startup Waveforms
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at high
frequencies can dissipate significant amounts of power. It is
important to determine the driver power dissipation and the
resulting junction temperature in the application to ensure
that the part is operating within acceptable temperature
limits.
JB
application, the localized temperature around the device is
a function of the layout and construction of the PCB along
with airflow across the surfaces. To ensure reliable
operation, the maximum junction temperature of the device
must be prevented from exceeding the maximum rating of
150°C; with 80% derating, T would be limited to 120°C.
J
Rearranging Equation 4 determines the board temperature
required to maintain the junction temperature below 120°C:
The total power dissipation in a gate driver is the sum of
TB,MAX + TJ * PTOTAL @ YJB
(eq. 8)
two components, P
and P
:
GATE
PTOTAL + PGATE ) PDYNAMIC
DYNAMIC
TB,MAX + 120°C * 0.396 W @ 42°CńW + 104°C
(eq. 1)
(eq. 9)
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit time)
to switch the load MOSFET on and off at the switching
frequency. The power dissipation that results from driving
For comparison, replace the SOIC−8 used in the previous
example with the 3x3 mm MLP package with
y
= 2.8°C/W. The 3x3 mm MLP package can operate at a
JB
PCB temperature of 118°C, while maintaining the junction
temperature below 120°C. This illustrates that the
physically smaller MLP package with thermal pad offers a
more conductive path to remove the heat from the driver.
Consider tradeoffs between reducing overall circuit size
with junction temperature reduction for increased
reliability.
a MOSFET at a specified gate−source voltage, V , with
GS
gate charge, Q , at switching frequency, f , is
G
SW
determined by:
PGATE + QG @ VGS @ fSW
(eq. 2)
Dynamic Pre−drive / Shoot−through Current: A power
loss resulting from internal current consumption under
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15
FAN3121, FAN3122
Typical Application Diagrams
VOUT
VIN
B2
B1
A2
A1
BIAS
FAN3122
SR EN
FAN3122
From A2
From A1
1
2
3
4
8
1
8
7
6
5
VDD
IN
VDD
VDD
VDD
2
7
6
5
OUT
OUT
OUT
OUT
IN
SR EN
3
EN
EN
4
PGND
AGND
PGND
AGND
Figure 53. Full−Bridge Synchronous Rectification
VOUT
VIN
PWM
VBIAS
FAN3121
1
2
3
4
8
7
6
5
VDD
IN
VDD
P1
(AGND)
OUT
SR Enable
Active HIGH
EN
OUT
AGND
PGND
Figure 54. Hybrid Synchronous Rectification in a Forward Converter
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16
FAN3121, FAN3122
ORDERING INFORMATION
Part Number
†
Logic
Input Threshold
Package
3x3 mm MLP−8
SOIC−8
Shipping
FAN3121CMPX
FAN3121CMX
Inverting Channels +
Enable
CMOS
3.000 / Tape & Reel
2.500 / Tape & Reel
3.000 / Tape & Reel
2.500 / Tape & Reel
3.000 / Tape & Reel
2.500 / Tape & Reel
3.000 / Tape & Reel
2.500 / Tape & Reel
FAN3121TMPX
FAN3121TMX
TTL
3x3 mm MLP−8
SOIC−8
FAN3122CMPX
FAN3122CMX
Non−Inverting
Channels + Enable
CMOS
TTL
3x3 mm MLP−8
SOIC−8
FAN3122TMPX
FAN3122TMX
3x3 mm MLP−8
SOIC−8
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
FAN3121, FAN3122
Table 1. RELATED PRODUCTS
Gate Drive
(Note 14) (Sink/Src)
Part Number
Type
Input Threshold
Logic
Package
FAN3111C Single 1 A
FAN3111E Single 1 A
+1.1 A / −0.9 A
CMOS
Single Channel of Dual−Input / Single−Output SOT23−5, MLP6
+1.1 A / −0.9 A
External
Single Non−Inverting Channel with External
SOT23−5, MLP6
Reference
FAN3100C Single 2 A
FAN3100T Single 2 A
+2.5 A / −1.8 A
+2.5 A / −1.8 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
CMOS
TTL
Single Channel of Two−Input / One−Output
Single Channel of Two−Input / One−Output
Single Non−Inverting Channel + 3.3 V LDO
Dual Inverting Channels
SOT23−5, MLP6
SOT23−5, MLP6
SOT23−5
FAN3180
FAN3216T
FAN3217T
FAN3226C
FAN3226T
FAN3227C
FAN3227T
FAN3228C
FAN3228T
FAN3229C
FAN3229T
FAN3268T
Single 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2 A
Dual 2A
Dual 2 A
Dual 2 A
Dual 2 A
TTL
TTL
SOIC8
TTL
Dual Non−Inverting Channels
SOIC8
CMOS
TTL
Dual Inverting Channels + Dual Enable
Dual Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Channels of Two−Input / One−Output
Dual Channels of Two−Input / One−Output
Dual Channels of Two−Input / One−Output
Dual Channels of Two−Input / One−Output
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8
CMOS
TTL
CMOS
TTL
CMOS
TTL
TTL
20 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
FAN3278T
Dual 2 A
+2.4 A / −1.6 A
TTL
30 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
SOIC8
FAN3223C
FAN3213T
FAN3214T
FAN3223T
FAN3224C
FAN3224T
FAN3225C
FAN3225T
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
Dual 4 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
> +12.0 A
CMOS
TTL
Dual Inverting Channels + Dual Enable
Dual Inverting Channels
SOIC8, MLP8
SOIC8
TTL
Dual Non−Inverting Channels
SOIC8
TTL
Dual Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Channels of Two−Input / One−Output
Dual Channels of Two−Input / One−Output
Single Inverting Channel + Enable
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8
CMOS
TTL
CMOS
TTL
FAN3121C Single 9 A
FAN3121T Single 9 A
FAN3122C Single 9 A
FAN3122T Single 9 A
CMOS
TTL
Single Inverting Channel + Enable
CMOS
TTL
Single Non−Inverting Channel + Enable
Single Non−Inverting Channel + Enable
Dual−Coil Relay Driver, Timing Config. 0
Dual−Coil Relay Driver, Timing Config. 1
FAN3240
FAN3241
Dual 12 A
Dual 12 A
TTL
> +12.0 A
TTL
SOIC8
14.Typical currents with OUT at 6 V and V = 12 V.
DD
15.Thresholds proportional to an externally supplied reference voltage.
MillerDrive is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3x3, 0.65P
CASE 511CD
ISSUE O
1
SCALE 2:1
DATE 29 APR 2014
NOTES:
A
B
E
L
L
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
PIN ONE
REFERENCE
ALTERNATE
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
0.80
0.05
2X
0.10
C
A
A1
A3
b
0.70
0.00
0.20 REF
A3
EXPOSED Cu
MOLD CMPD
2X
0.10
C
0.25
0.35
TOP VIEW
D
D2
E
3.00 BSC
2.05
2.25
DETAIL B
A
3.00 BSC
A1
0.05
0.05
C
E2
e
K
L
L1
1.10
0.65 BSC
0.20
0.30
0.00
1.30
DETAIL B
ALTERNATE
−−−
0.50
0.15
CONSTRUCTIONS
C
A3
SEATING
PLANE
NOTE 4
A1
C
SIDE VIEW
D2
GENERIC
MARKING DIAGRAM*
DETAIL A
8X
L
XXXXX
XXXXX
ALYWG
G
1
4
E2
A
L
= Assembly Location
= Wafer Lot
Y
= Year
W
G
= Work Week
= Pb−Free Package
K
5
8
8X
b
e/2
e
0.10
0.05
C
C
A
B
(Note: Microdot may be in either location)
NOTE 3
BOTTOM VIEW
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
RECOMMENDED
SOLDERING FOOTPRINT*
8X
0.63
2.31
PACKAGE
OUTLINE
3.30
1.36
1
8X
0.65
PITCH
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON84944F
WDFN8, 3X3, 0.65P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13735G
SOIC8
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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