FAN3229TMPX_技术文档

FAN3226 /FAN3227 /FAN3228 /FAN3229

Dual 2-A High-Speed, Low-SideGate Drivers

Features

Description

.

Industry-Standard Pinouts

The FAN3226-29 family of dual 2 A gate drivers is

designed to drive N-channel enhancement-mode

MOSFETs in low -side sw itching applications by

providing high peak current pulses during the short

sw itching intervals. The driver is available w ith either

TTL or CMOS input thresholds. Internal circuitry

provides an under-voltage lockout function by holding

the output low until the supply voltage is w ithin the

operating range. In addition, the drivers feature matched

internal propagation delays betw een A and B channels

for applications requiring dual gate drives w ith critical

timing, such as synchronous rectifiers. This enables

connecting tw o drivers in parallel to effectively double

the current capability driving a single MOSFET.

4.5-V to 18-V Operating Range

3-A Peak Sink/Source at V_DD= 12 V

2.4 A-Sink / 1.6-A Source at V_OUT= 6 V

Choice of TTL or CMOS Input Thresholds

Four Versions of Dual Independent Drivers:

-

Dual Inverting + Enable (FAN3226)

Dual Non-Inverting + Enable (FAN3227)

Dual Inputs in Tw o Pin-Out Configurations:

o Compatible w ith FAN3225x (FAN3228)

o Compatible w ith TPS2814D (FAN3229)

The FAN322X drivers incorporate MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize sw itching loss, w hile providing rail-

to-rail voltage sw ing and reverse current capability.

.

Internal Resistors Turn Driver Off If No Inputs

MillerDrive™ Technology

12-ns / 9-ns Typical Rise/Fall Times (1-nF Load)

Under 20-ns Typical Propagation Delay Matched

w ithin 1 ns to the Other Channel

The FAN3226 offers two inverting drivers and the

FAN3227 offers tw o non-inverting drivers. Each device

has dual independent enable pins that default to ON if

not connected. In the FAN3228 and FAN3229, each

channel has dual inputs of opposite polarity, w hich

allows configuration as non-inverting or inverting w ith an

optional enable function using the second input. If one

or both inputs are left unconnected, internal resistors

bias the inputs such that the output is pulled low to hold

the pow er MOSFET off.

.

Double Current Capability by Paralleling Channels

8-Lead 3x3 mm MLP or 8-Lead SOIC Package

Rated from –40°C to +125°C Ambient

Automotive Qualified to AEC-Q100 (F085 Version)

Applications

.

Sw itch-Mode Pow er Supplies

High-Efficiency MOSFET Sw itching

Synchronous Rectifier Circuits

DC-to-DC Converters

Related Resources

http://w w w.onsemi.com/pub/Collateral/AN-6069.pdf.pdf

Motor Control

Servers

Automotive-Qualified Systems (F085 version)

ENA

1

8

ENB

ENA

1

8

ENB

1

8

INA+

1

8

GND

INA-

+

-

+

-

INA

GND

INB

2

3

4

A

7

6

5

OUTA

VDD

INA

GND

INB

2

3

4

A

7

6

5

OUTA

VDD

INB+

GND

2

3

4

A

B

7

6

5

OUTA

VDD

2

3

4

A

B

7

6

5

OUTA

VDD

INA

-

INB+

+

-

+

-

OUTB

B

INB-

INB

-

FAN3226

FAN3227

FAN3228

FAN3229

Figure 1. Pin Configurations

October-2017, Rev. 2

Publication Order Number:

FAN3229T-F085/D

Ordering Information

Input

Threshold

Packing

Method

Quantity

per Reel

Part Number

Logic

Package

FAN3226CMPX

3x3 mm MLP-8

SOIC-8

Tape & Reel

3,000

2,500

3,000

2,500

3,000

2,500

3,000

2,500

FAN3226CMX

CMOS

TTL

(1)

SOIC-8

FAN3226CMX-F085

FAN3226TMPX

FAN3226TMX

Dual Inverting Channels+ Dual

Enable

3x3 mm MLP-8

SOIC-8

(1)

SOIC-8

FAN3226TMX-F085

FAN3227CMPX

FAN3227CMX

3x3 mm MLP-8

SOIC-8

CMOS

TTL

(1)

SOIC-8

FAN3227CMX-F085

FAN3227TMPX

FAN3227TMX

Dual Non-InvertingChannels+

Dual Enable

3x3 mm MLP-8

SOIC-8

(1)

FAN3227TMX-F085

SOIC-8

(1)

Dual Channelsof Two-Input /

One-Output Drivers, Pin

Configuration1

CMOS

TTL

SOIC-8

2,500

FAN3228CMX-F085

(1)

Tape & Reel

FAN3228TMX-F085

SOIC-8

2,500

3,000

2,500

3,000

2,500

FAN3229CMPX

FAN3229CMX

3x3 mm MLP-8

SOIC-8

Tape & Reel

CMOS

TTL

(1)

Dual Channelsof Two-Input /

One-Output Drivers, Pin

Configuration2

SOIC-8

FAN3229CMX-F085

FAN3229TMPX

FAN3229TMX

3x3 mm MLP-8

SOIC-8

(1)

FAN3229TMX-F085

SOIC-8

Note:

1. Qualified to AEC-Q100

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2

Package Outlines

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

Figure 2. 3x3 mm MLP-8 (Top View)

Figure 3. SOIC-8 (Top View)

Thermal Characteristics⁽²⁾

(3)

(4)

(5)

(6)

(7)

Package

8-Lead 3x3 mm Molded Leadless Package (MLP)

8-Pin Small Outline Integrated Circuit (SOIC)

Notes:

Unit

°C/W

Θ_JL

Θ_JT

Θ_JA

Ψ_JB

Ψ_JT

1.6

68

43

3.5

0.8

40

31

89

43

3.0

2. Estimates derived from thermal simulation; actual values depend on the application.

3. Theta_JL (Θ ): Thermal resistance betweenthe semiconductor junction andthe bottom surface of all the leads(including any

JL

thermal pad) that are typically solderedto a PCB.

4. Theta_JT (Θ ): Thermal resistance betweenthe semiconductor junction andthe top surface of the package,assuming it is

JT

held at a uniform temperature by a top-side heatsink.

5. Theta_JA (Θ_JA): Thermal resistance betweenjunction andambient,dependenton the PCB design, heat sinking, and airflow.

The value given isfor natural convection with noheatsinkusing a 2S2P board, asspecifiedin JEDEC standardsJESD51-2,

JESD51-5, and JESD51-7, asappropriate.

6. Psi _JB (Ψ_JB): Thermal characterizationparameter providingcorrelation betweensemiconductor junctiontemperature andan

application circuit board referencepoint for the thermal environment definedin Note 5. For the MLP-8package, the board

reference isdefined asthe PCB copper connectedto the thermal pad andprotrudingfrom either end of the package.For the

SOIC-8 package, the board reference isdefinedasthe PCB copper adjacent to pin 6.

7. Psi _JT (Ψ_JT): Thermal characterizationparameter providingcorrelation betweenthe semiconductor junction temperature and

the center of the top of the package for the thermal environmentdefined in Note5.

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3

ENA

1

8

ENB

ENA

1

8

ENB

1

8

INA+

1

8

GND

INA-

+

-

+

-

INA

GND

INB

2

3

4

A

7

6

5

OUTA

VDD

INA

GND

INB

2

3

4

A

7

6

5

OUTA

VDD

INB+

GND

2

3

4

A

B

7

6

5

OUTA

VDD

2

3

4

A

B

7

6

5

OUTA

VDD

INA

-

INB+

+

-

+

-

OUTB

B

INB-

INB

-

FAN3226

FAN3227

FAN3228

FAN3229

Figure 4. Pin Configurations (Repeated)

Pin Definitions

Name

Pin Description

Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and

CMOS INx threshold.

ENA

ENB

Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and

CMOS INx threshold.

GND

INA

Ground. Common ground reference for input and output circuits.

Input to Channel A.

INA+

INA-

INB

Non-Inverting Input to Channel A. Connect to VDD to enable output.

Inverting Input to Channel A. Connect to GND to enable output.

Input to Channel B.

INB+

INB-

Non-Inverting Input to Channel B. Connect to VDD to enable output.

Inverting Input to Channel B. Connect to GND to enable output.

OUTA Gate Drive Output A: Held LOW unless required input(s) are present and V_DDis above UVLO threshold.

OUTB Gate Drive Output B: Held LOW unless required input(s) are present and V_DDis above UVLO threshold.

Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V_DDis

OUTA

above UVLO threshold.

Gate Drive Output B (inverted from the input): Held LOW unless required input is present and V_DDis

above UVLO threshold.

OUTB

Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected

to GND; NOT suitable for carrying current.

P1

VDD

Supply Voltage. Provides pow er to the IC.

Output Logic

FAN3228 and FAN3229

FAN3226 (x=A or B)

FAN3227 (x=A or B)

(x=A or B)

ENx

INx

ENx

INx

OUTx

INx+

INx−

OUTx

0

1⁽⁸⁾

0

1⁽⁸⁾

0

1⁽⁸⁾

0⁽⁸⁾

0

1

0⁽⁸⁾

1

0

1⁽⁸⁾

0

1

0

1

0

1

0⁽⁸⁾

1

1⁽⁸⁾

1

1⁽⁸⁾

Note:

8. Default input signal if no external connection is made.

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4

Block Diagrams

V_DD

100kΩ

ENA

1

8

ENB

V_DD

INA

2

3

OUTA

VDD

7

6

100kΩ

GND

UVLO

V_{DD_OK}

V_DD

100kΩ

OUTB

5

INB

4

100kΩ

Figure 5. FAN3226 Block Diagram

V_DD

100kΩ

ENA

1

8

ENB

INA

2

7

6

OUTA

VDD

100kΩ

UVLO

GND

3

4

V_{DD_OK}

INB

5

OUTB

100kΩ

Figure 6. FAN3227 Block Diagram

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5

Block Diagrams

V_DD

INA+

INA-

8

1

100kΩ

OUTA

VDD

7

6

100kΩ

V_{DD_OK}

GND

INB+

3

2

UVLO

V_DD

100kΩ

OUTB

5

INB-

4

100kΩ

Figure 7. FAN3228 Block Diagram

V_DD

INA+

INA-

1

2

8

GND

OUTA

VDD

100kΩ

7

6

100kΩ

V_{DD_OK}

UVLO

V_DD

INB+

INB-

3

4

100kΩ

OUTB

5

100kΩ

Figure 8. FAN3229 Block Diagram

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6

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_DD

V_EN

Parameter

Min.

Max. Unit

VDD to PGND

-0.3

20.0

V

ENA and ENB to GND

GND - 0.3 V_DD+ 0.3

+260

V_IN

INA, INA+, INA–, INB, INB+ and INB– to GND

OUTA and OUTB to GND

V

V_OUT

T_L

V

Lead Soldering Temperature (10 Seconds)

Junction Temperature

ºC

T_J

-55

-65

+150

T_STG

Storage Temperature

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor

does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DD

Parameter

Min.

4.5

0

Max.

18.0

V_DD

Unit

V

Supply Voltage Range

V_EN

Enable Voltage ENA and ENB

V

V_IN

Input Voltage INA, INA+, INA–, INB, INB+ and INB–

Operating Ambient Temperature

0

V_DD

V

T_A

-40

+125

ºC

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7

Electrical Characteristics

Unless otherw ise noted, V_DD=12 V, T_J=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Supply

V_DD

Parameter

Conditions

Min. Typ. Max. Unit

Operating Range

4.5

18.0

1.20

1.05

4.3

V

mA

V

TTL

CMOS⁽⁹⁾

0.75

0.65

3.9

Supply Current Inputs / EN

Not Connected

I_DD

V_ON

Turn-On Voltage

Turn-Off Voltage

INA=ENA=V_DD, INB=ENB=0 V

3.5

3.3

V_OFF

3.7

4.1

V

FAN322xCMX_F085, FAN322xTMX_F085 (Automotive-Qualified Versions)

V_ON

Turn-On Voltage⁽¹⁴⁾

Turn-Off Voltage⁽¹⁴⁾

INA=ENA=V_DD, INB=ENB=0 V

3.3

3.1

3.9

3.7

4.5

4.3

V

V_OFF

Inputs (FAN322xT)⁽¹⁰⁾

V_{INL_T}INx Logic Low Threshold

V_{INH_T}INx Logic High Threshold

0.8

0.2

1.2

1.6

0.4

V

2.0

0.8

V_{HYS_T}TTL Logic Hysteresis Voltage

FAN322xT

I

Non-Inverting Input Current

Inverting Input Current

IN from 0 to V_DD

-1

175

1

µA

IN+

I

IN-

-175

FAN322xTMX_F085 (Automotive-Qualified Versions)

I

Non-inverting Input Current⁽¹⁴⁾

Inverting Input Current⁽¹⁴⁾

IN=0 V

IN=V_DD

IN=0 V

IN=V_DD

-1.5

90

1.5

µA

INx_T

I

120 175.0

INx_T

I

-175

-1.5

-120

-90

1.5

INx_T

I

INx_T

Inputs (FAN322xC)⁽¹⁰⁾

V_{INL_C}INx Logic Low Threshold

V_{INH_C}INx Logic High Threshold

30

38

55

17

%V_DD

70

V_{HYS_C}CMOS Logic Hysteresis Voltage

FAN322xC

I

Non-Inverting Input Current

Inverting Input Current

IN from 0 to V_DD

-1

175

1

µA

IN+

I

IN-

-175

FAN322xCMX_F085 (Automotive-Qualified Versions)

I

Non-inverting Input Current⁽¹⁴⁾

Inverting Input Current⁽¹⁴⁾

IN=0 V

IN=V_DD

IN=0 V

IN=V_DD

-1.5

90

1.5

µA

INx_T

I

120 175.0

INx_T

I

-175

-1.5

-120

-90

1.5

INx_T

I

INx_T

ENABLE (FAN3226C, FAN3226T, FAN3227C, FAN3227T)

V_ENL

V_ENH

Enable Logic Low Threshold

Enable Logic High Threshold

EN f rom 5 V to 0 V

EN f rom 0 V to 5 V

0.8

1.2

1.6

0.4

100

V

2.0

V_{HYS_T}TTL Logic Hysteresis Voltage⁽¹¹⁾

R_PU

Enable Pull-up Resistance⁽¹¹⁾

V

kΩ

Continued on the following page…

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8

Electrical Characteristics (Continued)

Unless otherw ise noted, V_DD=12 V, T_J=-40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

ENABLE (FAN3226C, FAN3226T, FAN3227C, FAN3227T) (continued)

t_D30 V to 5 V EN, 1 V/ns Slew Rate

t_D45 V to 0 V EN, 1 V/ns Slew Rate

10

19

18

34

32

ns

EN to Output Propagation Delay⁽¹²⁾

FAN3226CMX, FAN3226TMX, FAN3227CMX, FAN3227TMX_F085 (Automotive-Qualified Versions)

t_D3

t_D4

0 V to 5 V EN, 1 V/ns Slew Rate

5 V to 0 V EN, 1 V/ns Slew Rate

8

19

18

35

ns

EN to Output Propagation Delay^(12),(14)

Outputs

OUT at V_DD/2,

C_LOAD=0.1 µF, f=1 kHz

I_SINK

OUT Current, Mid-Voltage, Sinking⁽¹¹⁾

2.4

A

OUT Current, Mid-Voltage,

Sourcing⁽¹¹⁾

OUT at V_DD/2,

C_LOAD=0.1 µF, f=1 kHz

I_SOURCE

-1.6

I_{PK_SINK}

OUT Current, Peak, Sinking⁽¹¹⁾

OUT Current, Peak, Sourcing⁽¹¹⁾

Output Rise Time⁽¹³⁾

Output Fall Time⁽¹³⁾

Output Reverse Current Withstand⁽¹¹⁾

C_LOAD=0.1 µF, f=1 kHz

C_LOAD=1000 pF

3

-3

A

I_{PK_SOURCE}

t_RISE

t_FALL

I_RVS

12

9

22

17

ns

mA

C_LOAD=1000 pF

500

FAN322xT, FAN322xC

t_D1

CMOS Input

TTL Input

7

6

15

19

18

30

29

34

32

Output Propagation Delay, CMOS

ns

Inputs⁽¹³⁾

t_D2

t_D1

t_D2

10

Output Propagation Delay, TTL

Inputs⁽¹³⁾

ns

TTL Input

Propagation Matching Betw een

Channels⁽¹⁴⁾

INA=INB, OUTA and OUTB at

50% Point

t_DEL.MATCH

1

2

FAN322xTMX_F085, FAN322xCMX_F085 (Automotive-Qualified Versions)

CMOS Input

TTL Input

t_D1

t_D2

t_D1

t_D2

7

6

9

15

19

18

33

42

34

32

Output Propagation Delay, CMOS

Inputs^(13),(14)

ns

Output Propagation Delay, TTL

Inputs^(13),(14)

ns

TTL Input

Propagation Matching Betw een

Channels⁽¹⁴⁾

INA=INB, OUTA and OUTB at

50% Point

t_DEL.MATCH

V_OH

2

4

High Level Output Voltage⁽¹⁴⁾

Low Level Output Voltage⁽¹⁴⁾

V_OH=V_DD–V_OUT, I_OUT=–1 mA

15

10

35

25

mV

V_OL

I_OUT= 1 mA

Notes:

9. Low er supply current due to inactive TTL circuitry.

10. EN inputs have TTL thresholds; refer to the ENABLE section.

11. Not tested in production.

12. See Timing Diagrams of Figure 11 and Figure 12.

13. See Timing Diagrams of Figure 9 and Figure 10.

14. Apply to only F085 Version

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9

Timing Diagrams

90%

10%

Output

10%

V_INH

Input

V_INL

V_INH

V_INL

Input

t_D1

t_D2

t_D1

t_D2

t_FALL

t_RISE

t_FALL

Figure 9. Non-Inverting (EN HIGH or Floating)

Figure 10. Inverting (EN HIGH or Floating)

HIGH

Input

LOW

90%

Output

Enable

Output

Enable

10%

V

ENH

V

ENL

t_D3

t_D4

t_D3

t_D4

t_FALL

t_RISE

t_FALL

t_RISE

Figure 11. Non-Inverting (IN HIGH)

Figure 12. Inverting (IN LOW)

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10

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

TTL Input

FAN3226C, 27C

Inputs and Enables

Floating, Outputs

Inputs and Enables

Floating, Outputs Low

4

6

8

10

12

14

16

18

4

6

8

10

12

14

16

18

Supply Voltage (V)

Figure 13. I_DD(Static) vs. Supply Voltage⁽¹⁵⁾

Figure 14. I_DD(Static) vs. Supply Voltage⁽¹⁵⁾

1.6

1.4

FAN3228C, 29C

1.2

1.0

0.8

0.6

0.4

0.2

0.0

All Inputs Floating,

Outputs Low

4

6

8

10

12

14

16

18

V_DD- Supply Voltage (V)

Figure 15. I_DD(Static) vs. Supply Voltage⁽¹⁵⁾

Figure 16. I_DD(No-Load) vs. Frequency

Figure 17. I_DD(No-Load) vs. Frequency

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11

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 18. I_DD(1 nF Load) vs. Frequency

Figure 19. I_DD(1 nF Load) vs. Frequency

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

FAN3226C, 27C

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

TTL Input

Inputs and Enables

Floating, Outputs

Inputs and Enables

Floating,Outputs

-50

-25

0

25

50

75

100

125

-50 -25

0

25

50

75 100 125

Temperature (°C)

Figure 20. I_DD(Static) vs. Temperature⁽¹⁵⁾

Figure 21. I_DD(Static) vs. Temperature⁽¹⁵⁾

1.6

FAN3228C, 29C

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

All Inputs Floating,

Outputs Low

-50 -25

0

25

50

75 100 125

Temperature (°C)

Figure 22. I_DD(Static) vs. Temperature⁽¹⁵⁾

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12

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 23. Input Thresholds vs. Supply Voltage

Figure 24. Input Thresholds vs. Supply Voltage

Figure 25. Input Threshold % vs. Supply Voltage

Figure 26. Input Thresholds vs. Temperature

Figure 27. Input Thresholds vs. Temperature

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13

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 28. UVLO Thresholds vs. Temperature

Figure 29. UVLO Threshold vs. Temperature

Figure 30. Propagation Delays vs. Supply Voltage

Figure 31. Propagation Delays vs. Supply Voltage

Figure 32. Propagation Delays vs. Supply Voltage

Figure 33. Propagation Delays vs. Supply Voltage

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14

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 34. Propagation Delays vs. Temperature

Figure 35. Propagation Delays vs. Temperature

Figure 36. Propagation Delays vs. Temperature

Figure 37. Propagation Delays vs. Temperature

Figure 38. Fall Time vs. Supply Voltage

Figure 39. Rise Time vs. Supply Voltage

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15

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 40. Rise and Fall Times vs. Temperature

Figure 41. Rise/Fall Waveforms with 1 nF Load

Figure 42. Rise/Fall Waveforms with 10 nF Load

Figure 43. Quasi-Static Source Current with V_DD=12 V

Figure 44. Quasi-Static Sink Current with V_DD=12 V

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16

Typical Performance Characteristics

Typical characteristics are provided at 25°C and V_DD=12 V unless otherw ise noted.

Figure 45. Quasi-Static Source Current with V_DD=8 V

Figure 46. Quasi-Static Sink Current with V_DD=8 V

Note:

15. For any inverting inputs pulled low , non-inverting inputs pulled high, or outputs driven high, static I_DDincreases by

the current flow ing through the corresponding pull-up/dow n resistor show n in the block diagram.

Test Circuit

V_DD

120µF

Al. El.

4.7µF

ceramic

Current Probe

LECROY AP015

I_OUT

IN

1kHz

1µF

ceramic

C_LOAD

0.1µF

V_OUT

Figure 47. Quasi-Static I_OUT/ V_OUTTest Circuit

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17

Applications Information

Input Thresholds

MillerDrive™ Gate Drive Technology

FAN322x gate drivers incorporate the MillerDrive™

architecture show n in Figure 48. For the output stage, a

combination of bipolar and MOS devices provide large

currents over a w ide range of supply voltage and

temperature variations. The bipolar devices carry the

bulk of the current as OUT sw ings betw een 1/3 to 2/3

V_DDand the MOS devices pull the output to the high or

low rail.

Each member of the FAN322x driver family consists of

tw o identical channels that may be used independently

at rated current or connected in parallel to double the

individual current capacity. In the FAN3226 and

FAN3227, channels A and B can be enabled or disabled

independently using ENA or ENB, respectively. The EN

pin has TTL thresholds for parts w ith either CMOS or

TTL input thresholds. If ENA and ENB are not

connected, an internal pull-up resistor enables the driver

channels by default. If the channel A and channel B

inputs and outputs are connected in parallel to increase

the driver current capacity, ENA and ENB should be

connected and driven together.

The purpose of the MillerDrive™ architecture is to

speed up sw itching by providing high current during the

Miller plateau region w hen the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

The FAN322x family offers versions in either TTL or

CMOS input thresholds. In the FAN322xT, the input

thresholds meet industry-standard TTL-logic thresholds

For applications that have zero voltage sw itching during

the MOSFET turn-on or turn-off interval, the driver

supplies high peak current for fast sw itching even

though the Miller plateau is not present. This situation

often occurs in synchronous rectifier applications

because the body diode is generally conducting before

the MOSFET is sw itched on.

independent of the V_DDvoltage, and there is

a

hysteresis voltage of approximately 0.4 V. These levels

permit the inputs to be driven from a range of input logic

signal levels for w hich a voltage over 2 V is considered

logic high. The driving signal for the TTL inputs should

have fast rising and falling edges w ith a slew rate of

6 V/µs or faster, so a rise time from 0 to 3.3 V should be

550 ns or less. With reduced slew rate, circuit noise

could cause the driver input voltage to exceed the

hysteresis voltage and retrigger the driver input, causing

erratic operation.

The output pin slew rate is determined by V_DDvoltage

and the load on the output. It is not user adjustable, but

a series resistor can be added if a slow er rise or fall time

at the MOSFET gate is needed.

V_DD

In the FAN322xC, the logic input thresholds are

dependent on the V_DDlevel and, w ith V_DDof 12 V, the

logic rising edge threshold is approximately 55% of V_DD

and the input falling edge threshold is approximately

38% of V_DD. The CMOS input configuration offers a

hysteresis voltage of approximately 17% of V_DD. The

CMOS inputs can be used w ith relatively slow edges

(approaching DC) if good decoupling and bypass

techniques are incorporated in the system design to

prevent noise from violating the input voltage hysteresis

w indow . This allow s setting precise timing intervals by

fitting an R-C circuit betw een the controlling signal and

the IN pin of the driver. The slow rising edge at the IN

pin of the driver introduces a delay betw een the

controlling signal and the OUT pin of the driver.

Input

stage

V_OUT

Figure 48. MillerDrive™ Output Architecture

Under-Voltage Lockout

Static SupplyCurrent

The FAN322x startup logic is optimized to drive ground-

referenced N-channel MOSFETs w ith an under-voltage

lockout (UVLO) function to ensure that the IC starts up

in an orderly fashion. When V_DDis rising, yet below the

3.9 V operational level, this circuit holds the output low ,

regardless of the status of the input pins. After the part

is active, the supply voltage must drop 0.2 V before the

part shuts dow n. This hysteresis helps prevent chatter

when low V_DDsupply voltages have noise from the

pow er sw itching. This configuration is not suitable for

driving high-side P-channel MOSFETs because the low

output voltage of the driver w ould turn the P-channel

MOSFET on w ith V_DDbelow 3.9 V.

In the I_DD(static) typical performance characteristics

(see Figure 13 - Figure 15 and Figure 20 - Figure 22),

the curve is produced w ith all inputs / enables floating

(OUT is low ) and indicates the low est static I_DDcurrent

for the tested configuration. For other states, additional

current flows through the 100 kΩ resistors on the inputs

and outputs show n in the block diagram of each part

(see Figure 5 - Figure 8). In these cases, the actual

static I_DDcurrent is the value obtained from the curves

plus this additional current.

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18

V_DDBypass Capacitor Guidelines

To enable this IC to turn a device on quickly, a local high-

frequency bypass capacitor C_BYPw ith low ESR and ESL

should be connected betw een the VDD and GND pins

with minimal trace length. This capacitor is in addition to

bulk electrolytic capacitance of 10 µF to 47 µF commonly

found on driver and controller bias circuits.

best results, make connections to all pins as short

and direct as possible.

.

The FAN322x is compatible w ith many other

industry-standard drivers. In single input parts w ith

enable pins, there is an internal 100 kΩ resistor tied

to V_DDto enable the driver by default; this should be

considered in the PCB layout.

A typical criterion for choosing the value of C_BYPis to

keep the ripple voltage on the V_DDsupply to ≤5%. This

is often achieved w ith a value ≥20 times the equivalent

The turn-on and turn-off current paths should be

minimized, as discussed in the follow ing section.

load capacitance C_EQV, defined here as Q_GATE/V_DD

Ceramic capacitors of 0.1 µF to 1 µF or larger are

common choices, as are dielectrics, such as X5R and

X7R w ith good temperature characteristics and high

pulse current capability.

.

Figure 49 show s the pulsed gate drive current path

when the gate driver is supplying gate charge to turn the

MOSFET on. The current is supplied from the local

bypass capacitor, C_BYP, and flow s through the driver to

the MOSFET gate and to ground. To reach the high

peak currents possible, the resistance and inductance in

the path should be minimized. The localized C_BYPacts

to contain the high peak current pulses w ithin this driver-

MOSFET circuit, preventing them from disturbing the

sensitive analog circuitry in the PWM controller.

If circuit noise affects normal operation, the value of

C_BYPmay be increased to 50-100 times the C_EQV, or

C_BYPmay be split into tw o capacitors. One should be a

larger value, based on equivalent load capacitance, and

the other a smaller value, such as 1-10 nF mounted

closest to the VDD and GND pins to carry the higher

frequency components of the current pulses. The

bypass capacitor must provide the pulsed current from

both of the driver channels and, if the drivers are

sw itching simultaneously, the combined peak current

sourced from the C_BYPw ould be tw ice as large as w hen

a single channel is sw itching.

V_DD

V_DS

C_BYP

Layout and Connection Guidelines

FAN322x

The FA N3226-26 family of gate drivers incorporates

fast-reacting input circuits, short propagation delays,

and pow erful output stages capable of delivering current

peaks over 2 A to facilitate voltage transition times from

under 10 ns to over 150 ns. The follow ing layout and

connection guidelines are strongly recommended:

PWM

Figure 49. Current Path for MOSFET Turn-on

.

Keep high-current output and pow er ground paths

separate logic and enable input signals and signal

ground paths. This is espec ially critical w hen

dealing w ith TTL-level logic thresholds at driver

inputs and enable pins.

Figure 50 show s the current path w hen the gate driver

turns the MOSFET off. Ideally, the driver shunts the

current directly to the source of the MOSFET in a s mall

circuit loop. For fast turn-off times, the resistance and

inductance in this path should be minimized.

.

Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed sw itching, w hile reducing the loop area that

can radiate EMI to the driver inputs and

surrounding circuitry.

V_DD

V_DS

C_BYP

.

If the inputs to a channel are not externally

FAN322x

connected, the internal 100 kΩ resistors indicated

on block diagrams command a low output. In noisy

environments, it may be necessary to tie inputs of

an unused channel to VDD or GND using short

traces to prevent noise from causing spurious

output sw itching.

PWM

Many high-speed pow er circuits can be susceptible

to noise injected from their ow n output or other

external sources, possibly causing output re-

triggering. These effects can be obvious if the

circuit is tested in breadboard or non-optimal circuit

layouts w ith long input, enable, or output leads. For

Figure 50. Current Path for MOSFET Turn-off

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19

Truth Table of Logic Operation

OperationalWaveforms

The FAN3228/FAN3229 truth table indicates the

operational states using the dual-input configuration. In

a non-inverting driver configuration, the IN- pin should

be a logic low signal. If the IN- pin is connected to logic

high, a disable function is realized, and the driver output

remains low regardless of the state of the IN+ pin.

At pow er-up, the driver output remains low until the V_DD

voltage reaches the turn-on threshold. The magnitude of

the OUT pulses rises w ith V_DDuntil steady-state V_DDis

reached. The non-inverting operation illustrated in

Figure 53 show s that the output remains low until the

UVLO threshold is reached, the output is in-phase w ith

the input.

IN+

0

IN-

0

OUT

0

1

0

VDD

0

1

Turn-on threshold

1

0

1

IN-

In the non-inverting driver configuration in Figure 51, the

IN- pin is tied to ground and the input signal (PWM) is

applied to IN+ pin. The IN- pin can be connected to logic

high to disable the driver and the output remains low ,

regardless of the state of the IN+ pin.

IN+

VDD

IN+

PWM

OUT

FAN3228/9

IN-

Figure 53. Non-Inverting Startup Waveforms

GND

For the inverting configuration of Figure 52, startup

waveforms are show n in Figure 54. With IN+ tied to V_DD

and the input signal applied to IN–, the OUT pulses are

inverted w ith respect to the input. At pow er-up, the

inverted output remains low until the V_DDvoltage

reaches the turn-on threshold, then it follow s the input

w ith inverted phase.

Figure 51. Dual-Input Driver Enabled,

Non-Inverting Configuration

In the inverting driver application in Figure 52, the IN+

pin is tied high. Pulling the IN+ pin to GND forces the

output low , regardless of the state of the IN- pin.

VDD

Turn-on threshold

VDD

IN-

IN+

OUT

IN+

(VDD)

FAN3228/9

IN-

PWM

GND

OUT

Figure 52. Dual-Input Driver Enabled,

Inverting Configuration

Figure 54. Inverting Startup Waveforms

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20

Thermal Guidelines

Gate drivers used to sw itch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

pow er. It is important to determine the driver pow er

dissipation and the resulting junction temperature in the

application to ensure that the part is operating w ithin

acceptable temperature limits.

In the forw ard converter w ith synchronous rectifier

show n in the typical application diagrams, the

FDMS8660S is a reasonable MOSFET selection. The

gate charge for each SR MOSFET w ould be 60 nC w ith

V_GS= V_DD= 7V. At a sw itching frequency of 500 kHz,

the total pow er dissipation is:

The total pow er dissipation in a gate driver is the sum of

P_GATE= 60 nC • 7 V • 500 kHz • 2 = 0.42 W

_DYNAMIC= 3 mA • 7 V • 2 = 0.042 W

_TOTAL= 0.46 W

The SOIC-8 has

(5)

tw o components, P_GATEand P_DYNAMIC

:

P

(6)

(7)

P_TOTAL= P_GATE+ P_DYNAMIC

(1)

P

Gate Driving Loss: The most significant pow er loss

results from supplying gate current (charge per unit

time) to sw itch the load MOSFET on and off at the

sw itching frequency. The pow er dissipation that

results from driving a MOSFET at a specified gate-

source voltage, V_GS, w ith gate charge, Q_G, at

sw itching frequency, f_SW, is determined by:

a

junction-to-board thermal

ψ_JB

characterization parameter of

= 43°C/W. In a

system application, the localized temperature around

the device is a function of the layout and construction of

the PCB along w ith airflow across the surfaces. To

ensure reliable operation, the maximum junction

temperature of the device must be prevented from

exceeding the maximum rating of 150°C; w ith 80%

derating, T_Jw ould be limited to 120°C. Rearranging

Equation 4 determines the board temperature required

to maintain the junction temperature below 120°C:

P_GATE= Q_G• V_GS• f_SW• n

(2)

n is the number of driver channels in use (1 or 2).

Dynamic Pre-drive / Shoot-through Current: A

pow er loss resulting from internal current

consumption under dynamic operating conditions,

including pin pull-up / pull-dow n resistors, can be

obtained using the “I_DD( No-Load) vs. Frequency”

graphs in Typical Performance Characteristics to

determine the current I_DYNAMICdraw n from V_DD

under actual operating conditions:

ψ

T_B= T_J- P_TOTAL

•

(8)

(9)

JB

T_B= 120°C – 0.46 W • 43°C/W = 100°C

For comparison, replace the SOIC-8 used in the

previous example w ith the 3x3 mm MLP package w ith

ψ_JB

= 3.5°C/ W. The 3x3 mm MLP package could

operate at PCB temperature of 118°C, w hile

a

P_DYNAMIC= I_DYNAMIC• V_DD• n

(3)

maintaining the junction temperature below 120°C. This

illustrates that the physically smaller MLP package w ith

thermal pad offers a more conductive path to remove

the heat from the driver. Consider tradeoffs betw een

reducing overall circuit size w ith junction temperature

reduction for increased reliability.

Once the pow er dissipated in the driver is determined,

the driver junction rise w ith respect to circuit board can

be evaluated using the follow ing thermal equation,

ψ_JB

assuming

w as determined for a similar thermal

design (heat sinking and air flow ):

ψ

T_J= P_TOTAL

w here:

•

_JB+ T_B

(4)

T_J

= driver junction temperature

ψ_JB

= (psi) thermal characterization parameter

relating temperature rise to total pow er

dissipation

T_B

= board temperature in location defined in Note

2 under Thermal Resistance table.

www.onsemi.com

21

Typical Application Diagrams

V_IN

V_OUT

FAN3227

8

7

6

5

1

2

3

4

PWM

PWMA

GND

OUTA

VDD

1

2

3

4

8

7

6

5

PWMB

Vbias

Timing/

Isolation

OUTB

FAN3227

Figure 55. Forward Converter

with Synchronous Rectification

Figure 56.

Primary-Side Dual Driver

in a Push-Pull Converter

V_IN

FAN3227

8

7

6

5

1

2

3

4

ENA

ENB

PWM-A

A

B

GND

VDD

PWM-B

Vbias

FAN3227

8

7

6

5

1

2

3

4

ENA

ENB

PWM-C

PWM-D

A

B

Phase Shift

Controller

Vbias

GND

VDD

Figure 57. Phase-Shifted Full-Bridge with Two Gate Drive Transformers (Simplified)

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22

Table 1. Related Products

Part

Number

Gate Drive⁽¹⁶⁾

(Sink/Src) Threshold

Input

Type

Logic

Package

Single 1 A FAN3111C +1.1 A / -0.9 A CMOS

Single 1 A FAN3111E +1.1 A / -0.9 A External⁽¹⁷⁾

Single 2 A FAN3100C +2.5 A / -1.8 A CMOS

Single 2 A FAN3100T +2.5 A / -1.8 A TTL

Single Channel of Dual-Input/Single-Output

SOT23-5, MLP6

Single Non-Inverting Channel withExternal Reference SOT23-5, MLP6

Single Channel of Two-Input/One-Output

Single Non-Inverting Channel + 3.3-V LDO

Dual Inverting Channels

SOT23-5, MLP6

SOT23-5

Single 2 A FAN3180

+2.4 A / -1.6 A TTL

Dual 2 A FAN3216T +2.4 A / -1.6 A TTL

Dual 2 A FAN3217T +2.4 A / -1.6 A TTL

SOIC8

Dual Non-InvertingChannels

SOIC8

+2.4 A / -1.6 A CMOS

+2.4 A / -1.6 A TTL

+2.4 A / -1.6 A CMOS

+2.4 A / -1.6 A TTL

+2.4 A / -1.6 A CMOS

+2.4 A / -1.6 A TTL

+2.4 A / -1.6 A CMOS

+2.4 A / -1.6 A TTL

Dual Inverting Channels+ Dual Enable

Dual Non-InvertingChannels+ Dual Enable

SOIC8, MLP8

Dual 2 A FAN3226C

Dual 2 A FAN3226T

Dual 2 A FAN3227C

Dual 2 A FAN3227T

Dual 2 A FAN3228C

Dual 2 A FAN3228T

Dual 2 A FAN3229C

Dual 2 A FAN3229T

Dual Channelsof Two-Input/One-Output, Pin Config.1 SOIC8, MLP8

Dual Channelsof Two-Input/One-Output, Pin Config.2 SOIC8, MLP8

20 V Non-Inverting Channel (NMOS) and Inverting

SOIC8

Dual 2 A FAN3268T +2.4 A / -1.6 A TTL

Dual 2 A FAN3278T +2.4 A / -1.6 A TTL

Channel (PMOS) + Dual Enables

30 V Non-Inverting Channel (NMOS) and Inverting

SOIC8

Channel (PMOS) + Dual Enables

Dual 4 A FAN3213T +2.5 A / -1.8 A TTL

Dual 4 A FAN3214T +2.5 A / -1.8 A TTL

Dual 4 A FAN3223C +4.3 A / -2.8 A CMOS

Dual 4 A FAN3223T +4.3 A / -2.8 A TTL

Dual 4 A FAN3224C +4.3 A / -2.8 A CMOS

Dual 4 A FAN3224T +4.3 A / -2.8 A TTL

Dual 4 A FAN3225C +4.3 A / -2.8 A CMOS

Dual 4 A FAN3225T +4.3 A / -2.8 A TTL

Single 9 A FAN3121C +9.7 A / -7.1 A CMOS

Single 9 A FAN3121T +9.7 A / -7.1 A TTL

Single 9 A FAN3122T +9.7 A / -7.1 A CMOS

Single 9 A FAN3122C +9.7 A / -7.1 A TTL

Dual Inverting Channels

SOIC8

Dual Non-InvertingChannels

SOIC8

Dual Inverting Channels+ Dual Enable

Dual Non-InvertingChannels+ Dual Enable

Dual Channelsof Two-Input/One-Output

Single Inverting Channel + Enable

Single Non-Inverting Channel + Enable

Dual-Coil Relay Driver, TimingConfig. 0

Dual-Coil Relay Driver, TimingConfig. 1

SOIC8, MLP8

SOIC8

Dual 12 A FAN3240

+12.0 A

TTL

Dual 12 A FAN3241

SOIC8

Notes:

16. Typical currents w ith OUTx at 6 V and V_DD=12 V.

17. Thresholds proportional to an externally supplied reference voltage.

www.onsemi.com

23

Physical Dimensions

2X

0.8 MAX

2X

RECOMMENDED LAND PATTERN

0.05

0.00

SEATING

PLANE

A. CONFORMS TO JEDEC REGISTRATION MO-229,

VARIATION VEEC, DATED 11/2001

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994

D. FILENAME: MKT-MLP08Drev2

Figure 58. 3x3 mm, 8-Lead Molded Leadless Package (MLP)

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in

any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor representative to

verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms

and conditions, specifically the warranty therein,which covers ON Semiconductor products.

www.onsemi.com

24

Physical Dimensions (Continued)

5.00

4.80

A

0.65

3.81

8

5

B

1.75

6.20

5.80

4.00

3.80

5.60

1

4

PIN ONE

INDICATOR

1.27

(0.33)

M

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.10

0.25

0.19

C

1.75 MAX

0.10

C

0.51

0.33

OPTION A - BEVEL EDGE

0.50

0.25

x 45°

R0.10

GAGE PLANE

OPTION B - NO BEVEL EDGE

0.36

NOTES: UNLESS OTHERWISE SPECIFIED

8°

0°

0.90

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

SEATING PLANE

(1.04)

0.406

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

DETAIL A

SCALE: 2:1

Figure 59. 8-Lead, Small Outline Integrated Curcuit (SOIC)

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in

any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to

verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms

and conditions, specifically the warranty therein,which covers ON Semiconductor products.

www.onsemi.com

25

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listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make

changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

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actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.

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型号：	FAN3229TMPX
厂家：	ONSEMI
描述：	Dual 2-A High-Speed, Low-Side Gate Drivers 栅驱动光电二极管接口集成电路
文件：	总26页 (文件大小：1767K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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