FAN3852UC16X [ONSEMI]
麦克风预放大器，带数字输出;
| 型号： | FAN3852UC16X |
| 厂家： | 
ONSEMI |
| 描述： | 麦克风预放大器，带数字输出 放大器 商用集成电路 |
| 文件： | 总10页 (文件大小：757K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microphone Pre-Amplifier
with Digital Output
FAN3852
Description
The FAN3852 integrates a pre−amplifier, LDO, and ADC that
converts Electret Condenser Microphone (ECM) outputs to digital
Pulse Density Modulation (PDM) data streams. The pre−amplifier
accepts analog signals from the ECM and drives an over−sampled
sigma delta Analog−to−Digital Converter (ADC) and outputs PDM
data. The PDM digital audio has the advantage of noise rejection and
easy interface to mobile handset processors.
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The FAN3852 features an integrated LDO and is powered from the
system supply rails up to 3.63 V, with low power consumption of only
0.85 mW and less than 20 mW in Power−Down Mode.
WLCSP−6
CASE 567TS
Features
• Optimized for Mobile Handset and Notebook PC Microphone
Applications
SELECT
INPUT
VDD
A1
B1
C1
A2
B2
C2
CLOCK
GND
• Accepts Input from Electret Condenser Microphones (ECM)
• Pulse Density Modulation (PDM) Output
• Standard 5−Wire Digital Interface
• Low Input Capacitance, High PSR, 20 kHz Pre−Amplifier
• Low−Power 1.5 mA Sleep Mode
DATA
• Typical 420 mA Supply Current
Top View
• SNR of 62 dB (A) for 16 dB Gain
• Total Harmonic Distortion 0.02%
PIN CONFIGURATION
• Input Clock Frequency Range of 1−4 MHz
• Integrated Low Drop−Out Regulator (LDO)
MARKING DIAGRAM
• Small 1.242 mm × 0.842 mm 6−Ball, 0.400 mm pitch standard
WLCSP Package
VK&K
• 1.5 kV HBM ESD on MIC Input
&.&2&Z
Pin A1
Typical Applications
• Electret Condenser Microphones with Digital Output
• Mobile Handset
VK
K
.
2
Z
= Device Identifier
= Lot Run Code
= Pin A1 Mark
= Date Code
• Headset Accessories
• Personal Computer (PC)
= Plant Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2
of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
June, 2021 − Rev. 4
FAN3852/D
FAN3852
ORDERING INFORMATION
Part Number
†
Operating Temperature Range
−40°C to 85°C
Package
Packing Method
3000 Units/Tape & Reel
FAN3852UC16X
6 Ball, Wafer−Level
Chip−Scale Package (WLCSP)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
INTERNAL BLOCK DIAGRAM
V
DD
Sleep
Mode Ctrl
LDO
CLOCK
S−D
ADC
INPUT
Pre*Amp
DATA
SELECT
GND
Figure 1. Block Diagram
Table 1. PIN DEFINITIONS
Pin #
A1
Name
CLOCK
GND
Type
Input
Input
Output
Input
Input
Input
Description
Clock Input
B1
Ground Pin
C1
A2
DATA
PDM Output − 1 Bit ADC
Rising or Falling Clock Edge Select
Microphone Input
SELECT
INPUT
VDD
B2
C2
Device Power Pin
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
−0.3
−0.3
−0.3
8
Max.
Unit
V
V
DD
DC Supply Voltage
Digital I/O
4.0
V
IO
V
+ 0.3
V
DD
Microphone Input
2.2
ESD
Human Body Model, JESD22−A114, All Pins Except Microphone
kV
Input
Human Body Model, JESD2−A114 − Microphone Input
1.5
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device is fabricated using CMOS technology and is therefore susceptible to damage from electrostatic discharges. Appropriate
precautions must be taken during handling and storage of this device to prevent exposure to ESD.
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2
FAN3852
Table 3. RELIABILITY INFORMATION
Symbol
Rating
Min.
Typ.
Max.
+150
+125
+260
Unit
°C
T
J
Junction Temperature
T
STG
Storage Temperature Range
Peak Reflow Temperature
−65
°C
T
RFLW
°C
q
Thermal Resistance, JEDEC Standard, Multilayer
Test Boards, Still Air
90
°C/W
JA
2. T = 25°C unless otherwise specified
A
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
Operating Temperature Range
Supply Voltage Range
Min.
−40
Typ.
Max.
+85
3.63
10
Unit
°C
V
T
A
V
1.64
1.80
DD
RF−CLK
T
Clock Rise and Fall Time
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 5. DEVICE SPECIFIC ELECTRICAL CHARACTERISTICS
FAN3852UC16X
Min.
Typ.
Max.
Symbol
Value
Unit
SNR
Signal−to−Noise Ratio
= 1 kHz (1 Pa), A−Weighted
62
dB (A)
f
IN
e
Total Input RMS Noise
5.74
6.80
448
mV
RMS
N
20 Hz to 20 kHz, A−Weighted
V
IN
Maximum Input Signal
mV
PP
f
IN
= 1 kHz, THD + N < 10%, Level = 0 V
3. Guaranteed by characterization and/or design. Not production tested.
Table 6. ELECTRICAL CHARACTERISTICS
Unless otherwise specified, al limits are guaranteed for T = 25°C, V = 1.8 V, V = 94 dB (SPL) and f = 2.4 MHz.
A
DD
IN
CLK
Duty Cycle = 50% and C
= 15 pF
MIC
Symbol
Parameter
Condition
Min.
Typ.
1.80
420
Max.
Unit
V
V
Supply Voltage Range
Supply Current
1.64
3.63
DD
DD
I
INPUT = AC Coupled to GND,
CLOCK = On, No Load
mA
I
Sleep Mode Current
fCLK = GND
1.50
8.0
mA
SLEEP
PSR
Power Supply Rejection (Note 5)
INPUT = AC Coupled to GND,
−74
dBFS
Test Signal on V = 217 Hz,
DD
Square Wave and Broadband
Noise (Note 4), Both 100 mV
P−P
IN
Nominal Sensitivity (Note 6)
Total Harmonic Distortion (Note 7)
THD and Noise (Note 5)
INPUT = 94 dBSPL (1 Pa)
−26
0.02
0.2
dBFS
%
NOM
THD
f
IN
= 1 KHz, INPUT = −26 dBFS
0.20
1.0
THD+N
%
50 Hz ≤ f ≤ 1 kHz,
IN
INPUT = −20 dBFS
f
f
= 1 KHz, INPUT = −5 dBFS
1.0
5.0
1.3
5.0
IN
IN
= 1 KHz, INPUT = 0 dBFS
10.0
C
IN
R
IN
V
IL
Input Capacitance (Note 8)
Input Resistance (Note 8)
INPUT
INPUT
pF
GW
V
>10
CLOCK & SELECT Input Logic
LOW Level
0.3
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3
FAN3852
Table 6. ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, al limits are guaranteed for T = 25°C, V = 1.8 V, V = 94 dB (SPL) and f = 2.4 MHz.
A
DD
IN
CLK
Duty Cycle = 50% and C
= 15 pF
MIC
Symbol
Parameter
Condition
Min.
Typ.
Max.
+0.3
Unit
V
IH
CLOCK & SELECT Input Logic
HIGH Level
1.5
V
V
DD
V
Data Output Logic LOW Level
Data Output Logic HIGH Level
Acoustic Overload Point (Note 8)
0.35*V
V
V
OL
DD
V
OH
0.65*V
120
DD
V
OUT
THD+N < 10%
dBSPL
ns
t
t
t
t
Time from CLOCK Transition to
Data becoming Valid
On Falling Edge of CLOCK,
SELECT = GND, C = 15 pF
18
43
5
A
B
A
B
LOAD
Time from CLOCK Transition to
Data becoming HIGH−Z
On Rising Edge of CLOCK,
SELECT = GND, C = 15 pF
0
18
0
16
16
ns
ns
ns
LOAD
Time from CLOCK Transition to
Data becoming Valid
On Rising Edge of CLOCK,
SELECT = VDD, C = 15 pF
58
5
LOAD
Time from CLOCK Transition to
Data becoming HIGH−Z
On Falling Edge of CLOCK,
SELECT = VDD, C
= 15 pF
LOAD
f
Input CLOCK Frequency (Note 9)
CLOCK Duty Cycle (Note 5)
Wake−Up Time (Note 10)
Active Mode
1.0
40
2.4
50
4.0
60
MHz
%
CLK
CLK
dc
WAKEUP
t
f
f
= 2.4 MHz
= 2.4 MHz
0.35
0.01
2.00
1.00
100
ms
ms
pF
CLK
t
Fall−Asleep Time (Note 11)
Load Capacitance on Data
0
FALLASLEAP
CLK
C
LOAD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pseudo−random noise with triangular probability density function. Bandwidth up to 10 MHz.
5. Guaranteed by characterization. Not production tested.
6. Assuming that 120 dB (SPL) is mapped to 0 dBFS.
7. Assuming an input of −45 dBV.
8. Guaranteed by design. Not production tested.
9. All parameters are tested at 2.4 MHz. Frequency range guaranteed by characterization.
10.Device wakes up when f
≥ 300 kHz.
CLK
CLK
11. Device falls asleep when f
≤ 70 kHz.
CLK
Data
Valid
HIGH−Z
DATA1
t
A
t
B
DATA2
(For possible 2 Mic)
Data
Valid
HIGH−Z
nd
t
A
t
t
Microphone delay from clock edge to data assertion.
Microphone delay from clock edge to high−impedance state.
A −
B −
t > t to have interim HIGH−Z state in both signals.
A
B
Figure 2. Interface Timing
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4
FAN3852
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, all limits are guaranteed for T = 25°C, V = 1.8 V, V = 94 dB (SPL), f = 2.4 MHz and duty Cycle = 50%.
A
DD
IN
CLK
Amplitude Spectrum [dBFS], Fo = 1000.2135 Hz, Fs = 2.400000 MHz, SNR = 56.89 dB, SNR = 60.88 dB(A), THD = 0.008 %
Noise
Noise(A)
Signal
−20
−40
−60
−80
← Fo(0)= −26.15 dBFS
THD = 81.95 dB
SNR = 60.88 dBc(A)
SINAD = 56.87 dB
ENOB = 13.50
N = 2097152 pts
Blackman Window
↓ Integrated Noise = −87.03 dBFS(A)
Spur = −101.34 dBFS, SFDR = 75.19 dBc
↓
−100
−120
−140
−160
← Fo(1)= −110.28 dBFS
← Fo(2)= −116.40 dBFS
← Fo(3)= −120.45 dBFS
← Fo(4)= −125.03 dBFS
1
2
3
4
5
6
10
10
10
10
10
10
Frequency [Hz]
Figure 3. Noise vs. Frequency
Figure 4. THD, SINDA, and SNR vs. Input Amplitude
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5
FAN3852
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, all limits are guaranteed for T = 25°C, V = 1.8 V, V = 94 dB (SPL), f = 2.4 MHz and duty Cycle = 50%.
A
DD
IN
CLK
Figure 5. THD, SINAD and SNR vs. Output Level
Temp (°C)
−40
Delta (dB)
0.1971
−30
−20
−10
0
0.1644
0.1260
0.0954
0.0657
0.0359
0.0139
0.0000
−0.0097
−0.0344
−0.0514
−0.0739
−0.0998
−0.1183
−0.1271
10
20
25
30
40
50
60
70
80
85
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Figure 6. ꢀ Gain vs. Temperature (Nominal Temperature = 255C)
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6
FAN3852
APPLICATIONS INFORMATION
VDD
Audio
SPEAKER
Output
CLOCK
INPUT
Pre *
Amp
ADC
DATA
SELECT
L/R
CLK SDI SDO
Serial Port
Noise Shaper
Interpolation
Low Pass Filter
Decimation
Applications Software
Figure 7. Mono Microphone Application Circuit
VDD
Audio
SPEAKER
Output
CLOCK
INPUT
*
Pre
Amp
ADC
DATA
SELECT
Serial Port
CLK SDI SDO L/R
Noise Shaper
Interpolation
Low Pass Filter
Decimation
VDD
CLOCK
Applications Software
INPUT
*
Pre
Amp
ADC
DATA
SELECT
Figure 8. Stereo Microphone Application Circuit
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7
FAN3852
APPLICATIONS INFORMATION (continued)
Diaphragm
Airgap
Electret
Backplate
INPUT
FAN3852
V
DD
CLOCK
DATA
SELECT
GND
Figure 9. MIC Element Drawing
A 0.1 mF decoupling capacitor is required for VDD. It can
be located inside the microphone or on the PCB very close
to the VDD pin.
A 100 W resistance is recommended on the clock output
of the device driving the FAN3852 to minimize ringing and
improve signal integrity.
Due to high input impedance, care should be taken to
remove all flux used during the reflow soldering process.
For optimal PSR, route a trace to the VDD pin. Do not
place a VDD plane under the device.
1.64 V − 3.63 V
C2
C3
R
2.2 k
BIAS
VDD
SELECT
CLOCK
1−4 MHz
PDM Clock
PDM
Codec
C1
+
DATA
PDM Data
INPUT
GND
ECM
U1
FAN3852
Figure 10. Example Hardware Implementation
Table 7. RECOMMENDED COMPONENTS
Ref Des
Qty
Description of Options
Package
Manufacturer
Mfg PIN
U1
1
FAN3852 Microphone Pre−Amplifier
WLCSP6
ON
FAN3852UC16X
with Digital Output
Semiconductor
C1
1
Input AC Coupling Capacitor;
1 nF/1000 pF, ≥ 6.3 V, low−leakage
0402
Johansen
Dielectrics
500R07W102KV4T
0402
0603
0402
0402
0603
0402
0402
0603
Murata
Taiyo Yuden
Samsung
Yageo
GCM155R71H102KA37D
UMK107SD102KA−T
CL05B104KO5NNNC
CC0402KRX7R7BB104
06033C104KAT4A
C2
C3
1
1
Primary VDD Decoupling Capacitor;
0.1 mF, MLCC, ≥ 6.3 V
AVX
Optional VDD Decoupling Capacitor;
Samsung
Murata
CL05B103KB5VPNC
GCM155R71H103KA55J
CC0603KRX7R7BB103
0.01 mF, MLCC, ≥ 6.3 V
Yageo
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP6 1.242x0.842x0.457
CASE 567TS
ISSUE A
DATE 06 JUN 2019
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13367G
WLCSP6 1.242x0.842x0.457
PAGE 1 OF 1
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