FAN48610BUC50X [ONSEMI]
2.5 MHz, Fixed-Output Synchronous TinyBoost Regulator;
| 型号： | FAN48610BUC50X |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 MHz, Fixed-Output Synchronous TinyBoost Regulator 开关 输出元件 |
| 文件： | 总12页 (文件大小：775K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 2015
FAN48610
2.5 MHz, Fixed-Output Synchronous TinyBoost® Regulator
Description
Features
The FAN48610 is a low-power boost regulator designed to
provide a minimum voltage-regulated rail from a standard
single-cell Li-Ion battery and advanced battery chemistries.
Even below the minimum system battery voltage, the device
maintains the output voltage regulation for a minimum output
load current of 1.0 A. The combination of built-in power
transistors, synchronous rectification, and low supply current
suit the FAN48610 for battery-powered applications.
.
.
.
.
.
.
.
.
.
.
Input Voltage Range: 2.5 V to 4.50 V
Output Voltages Range: 3.0 V to 5.0 V
IOUT ≥ 1 A at VOUT = 5.0 V, VIN ≥ 2.5 V
IOUT ≥ 1.5 A at VOUT = 5.0 V, VIN ≥ 3.0 V
Up to 94% Efficient
Internal Synchronous Rectification
Soft-Start with True Load Disconnect
Short-Circuit Protection
The FAN48610 is available in a 9-bump, 0.4 mm pitch,
Wafer-Level Chip-Scale Package (WLCSP).
9-Bump, 1.215 mm x 1.215 mm, 0.4 mm Pitch WLCSP
Three External Components: 2016 0.47 H Inductor,
0603 Case Size Input / Output Capacitors
Total Application Board Solution Size: < 11 mm2
VIN
VOUT
+
CIN
10F
Battery
.
COUT
22F
SYSTEM
LOAD
FAN48610
SW
EN
PGND
AGND
0.47H
Applications
.
.
.
Class-D Audio Amplifier and USB OTG Supply
Boost for Low-Voltage Li-Ion Batteries
Smart Phones, Tablets, Portable Devices, Wearables
Figure 1. Typical Application
Ordering Information
Device
Operating
Temperature
Part Number
VOUT
Package
Packing(1)
Marking
FAN48610UC50X
FAN48610BUC50X(2)
FAN48610BUC45X(2) 4.5 V
FAN48610BUC33X(2) 3.3 V
Notes:
5.0 V
KF
-40°C to 85°C
WLCSP, 0.4 mm Pitch
Tape and Reel
KA
KN
1. Tape and reel specifications are available on www.fairchildsemi.com.
2. Includes backside lamination.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN48610 • Rev. 1.5
Block Diagrams
SW
VIN
Q2B Q2A
VOUT
COUT
Q2
Q1
CIN
Synchronous
Rectifier
Control
PGND
EN
Modulator
Logic & Control
AGND
Figure 2. IC Block Diagram
Vendor
Table 1. Recommended Components
Component
Description
Parameter
Typ.
Unit
Toko: DFE201612C
DFR201612C
Cyntec: PIFE20161B
L
0.47
µH
L1
0.47 µH, 30%, 2016
DCR (Series R)
40
m
Murata: GRM188R60J106K
TDK: C1608X5R0J106K
CIN
10 µF, 10%, 6.3 V, X5R, 0603
22 µF, 20%, 6.3 V, X5R, 0603
C
C
10
22
µF
µF
COUT
TDK: C1608X5R0J226M
Pin Configuration
VOUT
VIN
A3
A3
B3
C3
A2
B2
C2
A1
B1
C1
A1
A2
SW
EN
B3
B1
B2
PGND
C1 C2
AGND
C3
Figure 3. Top View
Figure 4. Bottom View
Pin Definitions
Pin # Name
Description
Output Voltage. This pin is the output voltage terminal; connect directly to COUT
.
A1, A2
A3
VOUT
VIN
Input Voltage. Connect to Li-Ion battery input power source and the bias supply for the gate drivers.
Switching Node. Connect to inductor.
B1, B2
B3
SW
Enable. When this pin is HIGH, the circuit is enabled.
EN
Power Ground. This is the power return for the IC. COUT capacitor should be returned with the shortest
path possible to these pins.
C1, C2 PGND
C3 AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with
respect to this pin – connect to PGND at a single point.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN48610 • Rev. 1.5
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
VIN
Parameter
Min. Max. Unit
Voltage on VIN Pin
-0.3
6.0
6.0
V
V
VOUT
Voltage on VOUT Pin
DC
-0.3
-1.0
-0.3
6.0
SW
VCC
SW Node
V
V
Transient: 10 ns, 3 MHz
8.0
6.0(3)
Voltage on Other Pins
Electrostatic Discharge Protection Level
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
2
1
ESD
kV
TJ
TSTG
TL
Junction Temperature
-40
-65
+150
+150
+260
°C
°C
°C
Storage Temperature
Lead Soldering Temperature, 10 Seconds
Note:
3. Lesser of 6.0 V or VIN + 0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max. Unit
VIN
IOUT
TA
Supply Voltage
2.5
1000
-40
4.5
V
Maximum Output Current
Ambient Temperature
Junction Temperature
mA
°C
°C
+85
TJ
-40
+125
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer
2s2p boards with vias in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction
temperature, TJ(max), at a given ambient temperature, TA.
Symbol
Parameter
Junction-to-Ambient Thermal Resistance
Typical
Unit
ϴJA
50
°C/W
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN48610 • Rev. 1.5
3
Electrical Characteristics
Recommended operating conditions, unless otherwise noted, circuit per Figure 1, VOUT= 3.0 V to 5.0 V, VIN = 2.5 V to 4.5 V,
TA = -40˚C to 85˚C. Typical values are given VIN = 3.6 V and TA = 25˚C.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Power Supply
VIN=3.6 V, IOUT=0, EN= VIN
Shutdown: EN=0, VIN=3.6 V
VIN Rising
85
3
125
10
IQ
VIN Quiescent Current
A
VUVLO
Under-Voltage Lockout
2.2
150
2.3
V
VUVLO_HYS Under-Voltage Lockout Hysteresis
mV
Inputs
VIH
VIL
Enable HIGH Voltage
Enable LOW Voltage
1.05
V
V
0.4
IPD
Current Sink Pull-Down
Low-State Active Pull-Down
EN Pin, Logic HIGH
EN Pin, Logic LOW
100
300
nA
kΩ
RLOW
Outputs
200
-2
400
Referred to VOUT
,
VREG
ILK_OUT
ILK
Output Voltage Accuracy DC(4)
VIN -to-VOUT Leakage Current
4
1
%
2.5 V ≤ VIN ≤ VOUT -150 mV
VOUT=0, EN=0, VIN=4.2 V
A
A
%
VOUT-to-VIN Reverse Leakage
Current
Output Voltage Accuracy Transient(5)
VOUT=5.0 V, EN=0, VIN=2.5 V
3.5
5
VTRSP
Timing
fSW
Referred to VOUT, 50-500 mA Load Step
-5
Switching Frequency
VIN=3.6 V, VOUT=5.0 V, Load=1000 mA
2.0
2.5
600
20
3.0
MHz
s
tSS
Soft-Start EN HIGH to Regulation(5)
FAULT Restart Timer(5)
50 Load, VOUT = 5.0 V
tRST
ms
Power Stage
RDS(ON)N
RDS(ON)P
IV_LIM
N-Channel Boost Switch RDS(ON)
P-Channel Sync. Rectifier RDS(ON)
Boost Valley Current Limit
VIN=3.6 V, VOUT=5.0 V
VIN=3.6 V, VOUT=5.0 V
VOUT=5.0 V
80
65
130
115
mΩ
mΩ
A
3.0
1.7
2.5
3.0
150
20
IV_LIM_SS Boost Soft-Start Valley Current Limit
VMIN_1.0A Minimum VIN for 1000 mA Load(5)
VMIN_1.5A Minimum VIN for 1500 mA Load(5)
VIN<VOUT < VOUT
VOUT=5.0 V
_
TARGET, SS Mode
A
V
VOUT=5.0 V
V
T150T
T150H
Over-Temperature Protection (OTP)
OTP Hysteresis
˚C
˚C
Notes:
4. DC ILOAD from 0 to 1 A. VOUT measured from mid-point of output voltage ripple. Effective capacitance of COUT > 3 F.
5. Guaranteed by design and characterization; not tested in production.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN48610 • Rev. 1.5
4
Typical Characteristics
Unless otherwise specified; VIN = 3.6 V, VOUT = 5.0 V, TA = 25°C, and circuit and components according to Figure 1.
96%
92%
88%
84%
80%
76%
96%
92%
88%
84%
80%
76%
2.6 VIN
3.0 VIN
3.6 VIN
4.2 VIN
- 40C
+25C
+85C
1
10
100
1000
1
10
100
1000
Load Current (mA)
Load Current (mA)
Figure 5. Efficiency vs. Load Current and Input Voltage
Figure 6. Efficiency vs. Load Current and Temperature
98%
94%
90%
86%
96%
92%
88%
84%
82%
78%
-40C
+25C
+85C
2.5 VIN
2.7 VIN
3.0 VIN
80%
10
100
1000
10
100
1000
Load Current (mA)
Load Current (mA)
Figure 7. Efficiency vs. Load Current and Input Voltage, Figure 8. Efficiency vs. Load Current and Temperature,
VOUT=3.3V
VIN=3.0V, VOUT=3.3V
2
1
3
2
1
0
0
2.6 VIN
3.0 VIN
3.6 VIN
4.2 VIN
-1
-2
- 40C
+25C
+85C
-1
-2
0
250
500
750
1000
0
250
500
750
1000
Load Current (mA)
Load Current (mA)
Figure 10. Output Regulation vs. Load Current and
Temperature (Normalized to 3.6 VIN, 500 mA Load,
TA=25°C)
Figure 9. Output Regulation vs. Load Current and Input
Voltage (Normalized to 3.6 VIN, 500 mA Load)
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN48610 • Rev. 1.5
5
Typical Characteristics
Unless otherwise specified; VIN = 3.6 V, VOUT = 5.0 V, TA = 25°C, and circuit and components according to Figure 1.
120
100
80
60
40
20
0
60
50
40
30
20
10
0
2.6 VIN
3.0 VIN
3.6 VIN
4.2 VIN
- 40C Auto
+25C Auto
+85C Auto
0
250
500
750
1000
2.0
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
Load Current (mA)
Figure 11. Quiescent Current vs. Input Voltage,
Temperature
Figure 12. Output Ripple vs. Load Current and
Input Voltage
3,000
2,500
2,000
1,500
1,000
2.6 VIN
3.0 VIN
500
3.6 VIN
4.2 VIN
1000
0
0
250
500
750
Load Current (mA)
Figure 13. Frequency vs. Load Current and Input Voltage
Figure 14. Startup, 50
Figure 15. Overload Protection
Figure 16. Load Transient, 100-500 mA, 100 ns Edge
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN48610 • Rev. 1.5
6
Typical Characteristics
Unless otherwise specified; VIN = 3.6 V, VOUT = 5.0 V, TA = 25°C, and circuit and components according to Figure 1.
Figure 18. Simultaneous Line / Load Transient, 3.3-3.9 VIN,
Figure 17. Load Transient, 500-1000 mA, 100 ns Edge
10 µs Edge, 500-1000 mA Load, 100 ns Edge
2.60
2.20
1.80
1.40
1.00
+25C
+85C
4.5
0.60
2.5
3.0
3.5
4.0
Input Voltage (V)
Figure 20. Typical Maximum Output Current vs.
Input Voltage
Figure 19. Line Transient, 3.3-3.9 VIN, 10 s Edge,
500 mA Load
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN48610 • Rev. 1.5
7
Circuit Description
FAN48610 is a synchronous boost regulator, typically
operating at 2.5 MHz in Continuous Conduction Mode
(CCM), which occurs at moderate to heavy load current and
low VIN voltages. The regulator’s Pass-Through Mode
automatically activates when VIN is above the boost
regulator’s set point.
If VOUT reaches VIN-300 mV during LIN1 Mode, the SS Mode
is initiated. Otherwise, LIN1 times out after 512 s and LIN2
Mode is entered.
In LIN2 Mode, the current source is incremented to 1.6 A. If
VOUT fails to reach VIN-300 mV after 1024 s, a fault
condition is declared and the device waits 20 ms to attempt
an automatic restart.
Table 2. Operating Modes
Mode
LIN
Description
Linear Startup
Invoked When:
VIN > VOUT
Soft-Start (SS) Mode
Upon the successful completion of LIN Mode (VOUT>VIN-
300 mV), the regulator begins switching with boost pulses
current limited to 50% of nominal level.
SS
Boost Soft-Start
VIN < VOUT < VOUT(TARGET)
VOUT= VOUT(TARGET)
VIN > VOUT(TARGET)
BST
PT
Boost Operating Mode
Pass-Through Mode
During SS Mode, if VOUT fails to reach regulation during the
SS ramp sequence for more than 64 s, a fault is declared. If
large COUT is used, the reference is automatically stepped
slower to avoid excessive input current draw.
Boost Mode Regulation
Boost (BST) Mode
This is a normal operating mode of the regulator.
The FAN48610 uses a current-mode modulator to achieve
excellent transient response and smooth transitions between
CCM and DCM operation. During CCM operation, the device
maintains a switching frequency of about 2.5 MHz. In light-
load operation (DCM), frequency is naturally reduced to
maintain high efficiency.
Pass-Through (PT) Mode
In normal operation, the device automatically transitions from
Boost Mode to Pass-Through Mode if VIN goes above the
target VOUT
. In Pass-Through Mode, the device fully
Shutdown and Startup
enhances Q2 to provide a very low impedance path from
VIN to VOUT. Entry to the Pass-Through Mode is triggered
by condition where VIN > VOUT and no switching has occurred
during the past 5 µs. To soften the entry into Pass-Through
Mode, Q2 is driven as a linear current source for the first
5 µs. Pass-Through Mode exit is triggered when VOUT
reaches the target VOUT voltage. During Automatic Pass-
Through Mode, the device is short-circuit protected by a
voltage comparator tracking the voltage drop from VIN to
VOUT; if the drop exceeds 300 mV, a fault is declared.
When EN is LOW, all bias circuits are off and the regulator is
in Shutdown Mode. During shutdown, current flow is
prevented from VIN to VOUT, as well as reverse flow from
VOUT to VIN. It is recommended to keep load current draw
below 500 mA until the devices successfully executes
startup. The following table describes the startup sequence.
Table 3. Boost Startup Sequence
Start
Mode
End Timeout
Entry
Exit
Mode
(µs)
Fault State
The regulator enters Fault State under any of the following
conditions:
VOUT > VIN-
300 mV
VIN >
VUVLO,
EN=1
SS
LIN2
SS
LIN1
LIN2
SS
.
VOUT fails to achieve the voltage required to advance
from LIN Mode to SS Mode.
TIMEOUT
512
VOUT > VIN-
300 mV
.
VOUT fails to achieve the voltage required to advance
from SS Mode to BST Mode.
LIN1 Exit
TIMEOUT
FAULT
1024
64
.
.
Boost current limit triggers for 2 ms during BST Mode.
VOUT=VOUT(TARGET) BST
LIN1 or
LIN2 Exit
VIN – VOUT > 300 mV; this fault can occur only after
successful completion of the soft-start sequence.
OVERLOAD
FAULT
TIMEOUT
.
VIN < VUVLO.
Once a fault is triggered, the regulator stops switching and
presents a high-impedance path between VIN and VOUT.
After waiting 20 ms, an automatic restart is attempted.
LIN Mode
When EN is HIGH and VIN > VUVLO, the regulator first
attempts to bring VOUT within 300 mV of VIN by using the
internal fixed-current source from VIN (Q2). The current is
limited to the LIN1 set point.
Over-Temperature
The regulator shuts down if the die temperature exceeds
150°C. Restart occurs when the IC has cooled by
approximately 20°C.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN48610 • Rev. 1.5
8
Application Information
Output Capacitance (COUT
)
Output Voltage Ripple
The effective capacitance (CEFF(6)) of small, high-value
ceramic capacitors decreases as their bias voltage
increases, as illustrated in the graph below:
25
Output voltage ripple is inversely proportional to COUT
.
During tON, when the boost switch is on, all load current is
supplied by COUT
.
ILOAD
VRIPPLE (PP) tON
EQ. 1
COUT
20
15
10
5
and
V
IN
tON tSW D tSW 1
EQ. 2
VOUT
therefore:
V
ILOAD
IN
VRIPPLE (PP) tSW 1
EQ. 3
EQ. 4
VOUT
C
OUT
0
0
1
2
3
4
5
6
1
DC Bias Voltage (V)
tSW
fSW
Figure 21. CEFF for 22 F, 0603, X5R, 6.3 V-Rated
Capacitor (TDK C1608X5R0J226M)
The maximum VRIPPLE occurs when VIN is minimum and ILOAD
is maximum. For better ripple performance, more output
capacitance can be added.
FAN48610 is guaranteed for stable operation with the
minimum value of CEFF (CEFF(MIN)) outlined in Table 4.
Table 4. Minimum CEFF Required for Stability
Layout Recommendations
The layout recommendations below highlight various top-
copper pours by using different colors.
Operating Conditions
CEFF(MIN) (F)
VOUT (V)
VIN (V)
ILOAD (mA)
To minimize spikes at VOUT, COUT must be placed as close
as possible to PGND and VOUT, as shown below.
5.0
2.5 to 4.5
0 to 1000
3.0
Note:
For thermal reasons, it is suggested to maximize the pour
area for all planes other than SW. Especially the ground
pour should be set to fill all available PCB surface area and
tied to internal layers with a cluster of thermal vias.
6. CEFF varies by manufacturer, capacitor material, and
case size.
Inductor Selection
Recommended nominal inductance value is 0.47 H.
The FAN48610 employs valley-current limiting, so peak
inductor current can reach 3.8 A for a short duration during
overload conditions. Saturation effects cause the inductor
current ripple to become higher under high loading, as only
the valley of the inductor current ripple is controlled.
Startup
Input current limiting is in effect during soft-start, which limits
the current available to charge COUT and any additional
capacitance on the VOUT line. If the output fails to achieve
regulation within the limits described in the Soft-Start section
above, a fault occurs, causing the circuit to shut down. It
waits about 20 ms before attempting a restart. If the total
combined output capacitance is very high, the circuit may
not start on the first attempt, but eventually achieves
regulation if no load is present. If a high current load and
high capacitance are both present during soft-start, the
circuit may fail to achieve regulation and continually attempt
soft-start, only to have the output capacitance discharged by
the load when in Fault State.
Figure 22. Layout Recommendation
Product-Specific Dimensions (This table pertains to the package information on the following page.)
D
E
X
Y
1.215 ±0.030 mm
1.215 ±0.030 mm
0.2075 mm
0.2075 mm
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN48610 • Rev. 1.5
9
0.03 C
E
E
A
2X
B
D
0.40
A1
ꢄꢀꢁꢂꢇꢋꢅ
Cu Pad (Bottom)
BALL A1
INDEX AREA
0.40
ꢄꢀꢁꢉꢇꢋꢅ
Solder Mask
0.03 C
2X
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
TOP VIEW
0.06 C
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ꢀꢁꢋꢈꢇꢀꢁꢀꢉꢈ
0.05 C
C
SEATING
PLANE
D
SIDE VIEWS
NOTES
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCE PER
ASME Y14.5M, 2009.
D. DATUM C IS DEFINED BY THE
SPHERICAL CROWNS OF THE BALLS.
E. FOR DIMENSIONS D,E,X, AND Y SEE
PRODUCT DATASHEET.
0.005
C A B
ꢀꢁꢂꢃꢀꢀꢁꢀꢂ
9X
0.40
C
B
A
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0.40
F. DRAWING FILNAME: MKT-UC009Ak rev3
2 3
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