FAN48630BUC31JX [ONSEMI]
带旁路模式的 2.5MHz，1500mA，同步 TinyBoost™ 稳压器;
| 型号： | FAN48630BUC31JX |
| 厂家： | 
ONSEMI |
| 描述： | 带旁路模式的 2.5MHz，1500mA，同步 TinyBoost™ 稳压器 稳压器 |
| 文件： | 总15页 (文件大小：2784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Synchronous Regulator
with Bypass Mode,
TINYBOOST®,
2.5 MHz, 1500 mA
FAN48630J
Description
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The FAN48630J allows systems to take advantage of new battery
chemistries that can supply significant energy when the battery
voltage is lower than the required voltage for system power ICs. By
combining built−in power transistors, synchronous rectification, and
low supply current; this IC provides a compact solution for systems
using advanced Li−Ion battery chemistries.
WLCSP16 1.78x1.78x0.586
CASE 567SY
The FAN48630J is a boost regulator designed to provide a minimum
output voltage (V
) from a single−cell Li−Ion battery, even
OUT(MIN)
when the battery voltage is below system minimum. Output voltage
regulation is guaranteed to a maximum load current of 1500 mA.
Quiescent current in Shutdown Mode is less than 3 mA, which
maximizes battery life. The regulator transitions smoothly between
Bypass and normal Boost Mode. The device can be forced into Bypass
Mode to reduce quiescent current.
MARKING DIAGRAM
1
2
K
Y
K
Z
Pin−1
Mark
X
The FAN48630J is available in a 16−bump, 0.4 mm pitch,
Wafer−Level Chip−Scale Package (WLCSP).
12
KK
X
Y
Z
= Alphanumeric Device Marking
= Lot Rune Code
= Alphabetical Year Code
= 2−weeks Date Code
= Assembly Plant Code
Features
• 3 External Components: 0.47 mH Inductor and 0603 Case Size Input
and Output Capacitors
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
• Input Voltage Range: 2.35 V to 5.5 V
• Fixed Output Voltage Option: 3.15 V/3.6 V
• Up to 96% Efficient
• True Bypass Operation when V > Target V
IN
OUT
• Internal Synchronous Rectifier
VIN
VOUT
• Soft−Start with True Load Disconnect
• Forced Bypass Mode
+
CIN
Battery
COUT
47 mF
PGND
SYSTEM
LO AD
0.47mF
0.47 mH
SW
• V
Control to Optimize Target V
OUT
• Short−Circuit Protection
SEL
FAN48630
VSEL
EN
AGND
PG
• Low Operating Quiescent Current
• 16−Bump, 0.4 mm Pitch WLCSP
BYP
Applications
Figure 1. Typical Application
• Boost for Low−Voltage Li−ion Batteries, Brownout Prevention,
Boosted Audio, USB OTG, and LTE / 3G RF Power
• Cell Phones, Smart Phones, Portable Instruments
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
October, 2019 − Rev. 2
FAN48630J/D
FAN48630J
Table 1. ORDERING INFORMATION
Output Voltage
Operating
Temperature
Device
Marking
†
V /V
SELO SEL1
Part Number
Package
Shipping
Tape & Reel
FAN48630BUC31JX
3.15 V/3.60 V
−40 to 85°C
WLCSP
JH
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
TYPICAL APPLICATION
Q3B Q3A
VIN
CIN
Q3
Bypass
Control
Q1B Q1A
SW
VOUT
Q1
COUT
Q2
Synchronous
Rectifier Control
GND
VSEL
EN
Modulator Logic
and Control
BYP
PG
Figure 2. Typical Application Block Diagram
Table 2. RECOMMENDED COMPONENTS
Component
Description
Vendor
Parameter
Typ.
Unit
L1
0.47 mH, 30%
Toko: DFE201612C
DFR201612C
Cyntec: PIFE20161B
L
0.47
mH
mF
C
4.7 mF, 10%, 6.3 V, X5R, 0603 (1608)
47 mF, 20%, 6.3 V, X5R, 0603 (1608)
Murata: GRM188R60J475K
TDK: C1608X5R0J475K
C
C
4.7
47
IN
C
Samsung: CL10A476MQ8CZNE
OUT
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2
FAN48630J
PIN CONFIGURATION
EN
A1
PG
A2
VIN
A4
B4
C4
D4
A3
B3
C3
D3
A2
B2
C2
D2
A1
B1
C1
D1
A4
A3
VSEL AGND
VOUT
B4
B3
B1
B2
C2
D2
BYP
C1
SW
C4
D4
C3
AGND
D1
PGND
D3
Figure 3. Top Through View (Bumps Down)
Figure 4. Bottom View
Table 3. PIN DEFINITIONS
Pin #
A1
Name
EN
Description
Enable. When this pin is HIGH, the circuit is enabled (Note 1).
A2
PG
Power Good. This is an open−drain output. PG is actively pulled LOW if output falls out of
regulation due to overload or if thermal protection threshold is exceeded.
A3–A4
B1
VIN
Input Voltage. Connect to Li−Ion battery input power source.
VSEL
AGND
Output Voltage Select. When boost is running, this pin can be used to select output voltage.
B2, C2, D1
Analog Ground. This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
B3–B4
C1
VOUT
BYP
Output Voltage. Place C
as close as possible to the device.
OUT
Bypass. This pin can be used to activate Forced Bypass Mode. When this pin is LOW,
the bypass switches (Q3 and Q1) are turned on and the IC is otherwise inactive.
C3–C4
D2–D4
SW
Switching Node. Connect to inductor.
PGND
Power Ground. This is the power return for the IC. The C
returned with the shortest path possible to these pins.
bypass capacitor should be
OUT
1. Do not connect the EN pin to VIN. A logic voltage of 1.8 V should control the EN pin and enable/disable the device.
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3
FAN48630J
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
Max.
Unit
V
V
V
Input Voltage
−0.3
6.5
6.0
8.0
8.0
V
V
V
V
V
IN
IN
V
OUT
Output Voltage
OUT
SW Node
DC
−0.3
−1.0
−0.3
Transient: 10 ns, 3 MHz
Other Pins
6.5
(Note 2)
ESD
Electrostatic Discharge Protection Level
Human Body Model per JESD22−A114
Charged Device Model per JESD22−C101
2.0
1.5
kV
kV
°C
°C
°C
T
J
Junction Temperature
−40
−65
+150
+150
+260
T
STG
Storage Temperature
T
L
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Lesser of 6.5 V or V + 0.3 V.
IN
Table 5. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
2.35
0
Max.
5.5
Unit
V
V
IN
Supply Voltage
Output Current
I
1500
+85
mA
°C
OUT
T
A
Ambient Temperature
Junction Temperature
−40
−40
T
J
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 6. THERMAL PROPERTIES
Symbol
Parameter
Typ.
Unit
θ
Junction−to−Ambient Thermal Resistance
Junction−to−Board Thermal Resistance
80
42
JA
°C/W
θ
JB
Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer Fairchild evaluation
boards (1 oz copper on all layers). Special attention must be paid not to exceed junction temperature T
at a given ambient temperate T .
J(max)
A
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4
FAN48630J
Table 7. ELECTRICAL CHARACTERISTICS Recommended operating conditions, unless otherwise noted, circuit
per Figure 1, V = 2.35 V to 5.5 V, T = −40°C to 85°C. Typical values are given at V = 3.0 V and T = 25°C.
IN
A
IN
A
Symbol
Parameter
Condition
Bypass Mode V = 3.15 V,
Min.
Typ.
Max.
Unit
I
Q
V
IN
Quiescent Current
140
190
mA
OUT
V
= 4.2 V
IN
Boost Mode V
IN
= 3.15 V,
150
250
mA
OUT
V
= 2.5 V
Shutdown: EN = 0, V = 3.0 V
1.5
4
5.0
10
mA
mA
mA
mA
IN
Forced Bypass Mode, V = 3.5 V
IN
I
VOUT to VIN Reverse Leakage
Leakage Current
V
= 3.6 V, EN = 0
0.2
0.1
1.0
1.0
LK
OUT
OUT
I
V
V
= 0, EN = 0, V = 4.2 V
IN
LK_OUT
OUT
V
Under−Voltage Lockout
V
IN
Rising
2.20
200
2.35
V
UVLO
V
Under−Voltage Lockout Hystere-
sis
mV
UVLO_HYS
V
PG Low
I
= 5 mA
0.4
1
V
mA
V
PG(OL)
PG
I
PG Leakage Current
PG_LK
V
IH
Logic Level High EN, VSEL, BYP
Logic Level Low EN, VSEL, BYP
1.2
V
IL
0.4
V
R
Logic Control Pin Pull Downs
(LOW Active)
300
100
kΩ
LOW
BYP, VSEL, EN
BYP, VSEL, EN
I
Weak Current Source Pull−Down
nA
%
PD
V
Output Voltage Accuracy
2.35 V ≤ V ≤ V −100 mV,
OUT_TARGET
–2
2.0
2.6
4
REG
IN
DC, 0 to 1500 mA
f
Switching Frequency
V
= 2.7 V, V
= 3.15 V,
OUT
2.5
3.0
MHz
SW
IN
Load = 1000 mA
I
Boost Valley Current Limit
V
IN
= 2.6 V
2.9
6.0
3.1
6.3
A
V
V_LIM
V
Output Over−Voltage Protection
Threshold
OVP
mV
V
Output Over−Voltage Protection
Hysteresis
300
OVP_HYS
120
85
mW
mW
R
R
N−Channel Boost Switch R
P−Channel Sync Rectifier
V
V
= 3.5 V, V
= 3.5 V, V
= 3.5 V
= 3.5 V
85
65
DS(ON)N
DS(ON)
IN
OUT
DS(ON)P
IN
OUT
R
DS(ON)
85
mW
R
P−Channel Bypass Switch
DS(ON)
V
IN
= 3.5 V, V
= 3.5 V
65
DS(ON)P_BYP
OUT
R
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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FAN48630J
Table 8. SYSTEM CHARACTERISTICS
The following table is verified by design and verified while using the following external components: L = 0.47 mH, DFE201612C−R47M
(Toko), C = 4.7 mF, 0603 (1608 metric), C1608X5R0J475K (TDK), C = 47 mF, 0603 (1608 metric), CL10A476MQ8CZNE
IN
OUT
(Samsung). These parameters are not verified in production. Minimum and maximum values are at V = 2.5 V to 5.5 V, T = −40°C
IN
A
to +85°C; circuit per Figure 1, unless otherwise noted. Typical values are at T = 25°C, V = 3.0 V, V
= 3.6 V, V = 1.8 V.
EN
A
IN
OUT
Symbol
ΔV
Parameter
Load Regulation
Line Regulation
Ripple Voltage
Condition
= 0 A to 1 A, V = 3.0 V
Min.
Typ.
80
Max.
Unit
mV/A
mV/V
mV
I
OUT_LOAD
OUT
IN
ΔV
2.7 V ≤ V ≤ 3.0 V, I = 1 A
OUT
7
OUT_LINE
IN
V
V
= 3.0 V, V
= 3.6 V,
10
OUT_RIPPLE
IN
OUT
I
= 800 mA, PWM Mode
OUT
V
OUT
= 3.0 V, V
= 3.6 V,
11
90
IN
OUT
I
= 50 mA, PFM Mode
η
Efficiency
%
V
OUT
= 2.5 V, V
= 3.15 V,
IN
OUT
I
= 20 mA, PFM
V
OUT
= 3.0 V, V
= 3.15 V,
96
IN
OUT
I
= 500 mA, PWM
V
OUT
= 3.0 V, V
= 3.6 V,
93
IN
OUT
I
= 600 mA, PWM
T
Soft−Start
EN High to 95% of Target_ V
L
550
"95
"15
ms
SS
OUT.
R = 50 W
ΔV
Load Transient
Line Transient
V
= 3.0 V, I = 0.5 A ⇔1 A,
OUT
= T = 1 ms
F
mV
mV
OUT_LOAD_TRX
IN
R
T
ΔV
V
= 2.5 V ⇔ 3.0 V,
OUT_LINE_TRX
IN
R
T
= T = 10 ms, I
= 300 mA
F
OUT
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FAN48630J
TYPICAL CHARACTERISTICS
Unless otherwise specified; V = 3.0 V, V
= 3.6 V, and T = 25°C; circuit and components according to Figure 1.
IN
OUT
A
100%
96%
92%
88%
84%
100%
96%
92%
88%
84%
80%
−40C
+25C
+85C
2.5 VIN
80%
3.0 VIN
3.3 VIN
750
Load Current (mA)
76%
0
250
500
750
1000
1250
1500
0
250
500
1000
1250
1500
Load Current (mA)
Figure 5. Efficiency vs. Load Current and Input
Voltage
Figure 6. Efficiency vs. Load Current and
Temperature
100%
100%
96%
92%
88%
84%
80%
76%
96%
92%
88%
84%
80%
76%
72%
2.5 VIN
3.0 VIN
3.3 VIN
−40C
+25C
+85C
0
250
500
750
1000
1250
1500
0
250
500
750
1000
1250
1500
Load Current (mA)
Load Current (mA)
Figure 8. Efficiency vs. Load Current and
Temperature, VOUT = 3.15 V
Figure 7. Efficiency vs. Load Current and Input Voltage,
V
OUT = 3.15 V
3
2
3
2
1
1
0
0
−1
−2
2.5 VIN
3.0 VIN
3.3 VIN
−40C
+25C
+85C
−1
−2
0
250
500
750
1000
1250
1500
0
250
500
750
1000
1250
1500
Load Current (mA)
Load Current (mA)
Figure 9. Output Regulation vs. Load Current and Input
Voltage
Figure 10. Output Regulation vs. Load Current
and Temperature
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FAN48630J
TYPICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified; V = 3.0 V, V
= 3.6 V, and T = 25°C; circuit and components according to Figure 1.
IN
OUT
A
250
200
150
20
16
12
8
−40C Bypass
+25C Bypass
+85C Bypass
100
−40C Auto
50
4
+25C Auto
+85C Auto
0
0
2.0
2.5
3.0
3.5
4.0
4.5
2.0
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
Input Voltage (V)
Figure 11. Quiescent Current vs. Input Voltage and
Temperature, VOUT = 3.15 V, Auto Mode
Figure 12. Quiescent Current vs. Input Voltage and
Temperature, VOUT = 3.15 V, Forced Bypass Mode
30
20
10
3,000
2,500
2,000
1,500
1,000
2.5 VIN
3.0 VIN
500
0
2.5 VIN
3.0 VIN
3.3 VIN
3.3 VIN
0
0
250
500
750
1000
1250 1500
0
250
500
750
1000
1250
1500
Load Current (mA)
Load Current (mA)
Figure 14. Frequency vs. Load Current and Input
Voltage
Figure 13. Output Ripple vs. Load Current and Input
Voltage
VOUT (2V/div)
VOUT (1V/div)
IL (500mA/div)
IL (500mA/div)
EN (2V/div)
EN (2V/div)
PG (5V/div)
PG (5V/div)
Figure 15. Startup, 50 ꢀ Load
Figure 16. Startup, 50 ꢀ Load, VIN = 2.5 V, VOUT = 3.15 V
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FAN48630J
TYPICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, V = 3.0 V; V
= 3.6 V, and T = 25°C; circuit and components according to Figure 1.
IN
OUT
A
VOUT (100mV/div)
VOUT (100mV/div)
IOUT (500mA/div)
IOUT (500mA/div)
Figure 17. Load Transient, IOUT = 500 ꢀ 1000 mA,
1 ꢁs Edge
Figure 18. Load Transient, IOUT = 100 ꢀ 500 mA,
1 ꢁs Edge, VOUT = 3.15 V
VOUT (200mV/div)
VOUT (50mV/div)
VIN(200mV/div)
VIN(200mV/div)
Figure 20. Line Transient, VIN = 2.5 V ꢀ 3.0 V,
10 ꢁs Edge, IOUT = 300 mA
Figure 19. Line Transient, VIN = 3.0 V ꢀ 3.6 V,
10 ꢁs Edge, IOUT = 500 mA, VOUT = 3.15 V
VOUT (200mV/div)
VSEL (2V/div)
Figure 21. VSEL Step, VIN = 3 V, VOUT = 3.15 ꢀ V3.6 V,
IOUT = 500 mA
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FAN48630J
CIRCUIT DESCRIPTION
FAN48630J is a synchronous boost regulator, typically
operating at 2.5 MHz in Continuous Conduction Mode
(CCM), which occurs at moderate to heavy load current and
internal fixed current source from V (Q3). The current is
IN
limited to LIN1 set point.
If V reaches V −300 mV during LIN1 Mode, the SS
OUT
IN
low V voltages. The regulator includes a Bypass Mode
state is initiated. Otherwise, LIN1 times out after 512 ms and
LIN2 Mode is entered.
IN
that activates when V is above the boost regulator’s
IN
setpoint.
In LIN2 Mode, the current source is incremented to 2 A.
In anticipation of a heavy load transition, the setpoint can
be adjusted upward by fixed amounts with the VSEL pin to
reduce the required system headroom during lighter−load
operation to save power.
If V
fails to reach V −300 mV after 1024 ms, a fault
OUT
IN
condition is declared.
SS State
Upon the successful completion of the LIN state
(V
≥V −300 mV), the regulator begins switching with
OUT
IN
Table 9. Operating States
boost pulses current limited to 50% of nominal level.
During SS state, V
internal reference. If V
the SS ramp sequence for more than 64 ms, a fault condition
is declared. If large C is used, the reference
is automatically stepped slower to avoid excessive input
current draw.
is ramped up by stepping the
fails to reach regulation during
Mode
LIN
Description
Linear Startup
Invoked When
> V
OUT
OUT
V
IN
OUT
SS
Boost Soft−Start
Boost Operating Mode
True Bypass Mode
V
< V
OUT
OUT
OUT(MIN)
OUT(MIN)
OUT
BST
BPS
V
= V
V
IN
> V
OUT(MIN)
BST State
Boost Mode
This is a normal operating state of the regulator.
The FAN48630J uses a current−mode modulator to
achieve excellent transient response and smooth transitions
between CCM and Discontinuous Conduction Mode
(DCM) operation. During CCM operation, the device
maintains a switching frequency of about 2.5 MHz.
In light−load operation (DCM), frequency is reduced to
maintain high efficiency.
BPS State
If V is above V
when the SS Mode successfully
IN
REG
completes, the device transitions directly to BPS Mode.
FAULT State
The regulator enters the FAULT state under any of
the following conditions:
• V
fails to achieve the voltage required to advance
from LIN state to SS state.
OUT
Table 10. Boost Startup Sequence
Start
State
Timeout
(ꢁ s)
• V
fails to achieve the voltage required to advance
from SS state to BST state.
OUT
Entry
Exit
End State
LIN1
V
>
V
IN
>
SS
• Boost current limit triggers for 2 ms during the BST
IN
OUT
UVLO,
EN = 1
V
−300 mV
state.
• V protection threshold is exceeded during BPS state.
DS
LIN2
SS
512
1024
64
• V drops below UVLO threshold.
IN
LIN2
SS
LIN1 Exit
V
IN
>
OUT
Once a FAULT is triggered, the regulator stops switching
and presents a high−impedance path between VIN to VOUT.
After waiting 20 ms, a restart is attempted.
V
−300 mV
TIMEOUT
FAULT
BST
LIN1 or
LIN2 Exit
V
OUT
=
Power Good
V
OUT(MIN)
Power good is 0 FAULT, 1 POWER GOOD, open−drain
output.
OVERLOAD
TIMEOUT
FAULT
The Power good pin is provided for signaling the system
when the regulator has successfully completed soft−start
and no faults have occurred. Power good also functions as
an early warning flag for high die temperature and overload
conditions.
Shutdown and Startup
If EN is LOW, all bias circuits are off and the regulator is
in Shutdown Mode. During shutdown, current flow is
prevented from V to V
, as well as reverse flow from
IN
OUT
• PG is released HIGH when the soft−start sequence is
successfully completed.
V
to V . During startup, it is recommended to keep DC
OUT
IN
current draw below 500 mA.
• PG is pulled LOW when PMOS current limit has
triggered for 64 ms OR the die the temperature exceeds
LIN State
When EN is HIGH and V > UVLO, the regulator
IN
attempts to bring V
within 300 mV of V using the
OUT
IN
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FAN48630J
120CC. PG is re−asserted when the device cools below
to 100CC.
• Any FAULT condition causes PG to be de−asserted.
transition from Boost Mode to Bypass Mode occurs at the
target V +25 mV. The corresponding input voltage is:
OUT
VIN w VOUT ) 25mV ) ILOAD * (DCRL ) RDS(ON)P
)
(eq. 2)
Over−Temperature
Forced Bypass
The regulator shuts down when the die temperature
exceeds 150°C. Restart occurs when the IC has cooled by
approximately 20°C.
Bypass Operation
In normal operation, the device automatically transitions
Entry to Forced Bypass Mode initiates with a current limit
on Q3 and then proceeds to a true bypass state. To prevent
reverse current to the battery, the device waits until output
discharges below V before entering Forced Bypass Mode.
IN
After the transition is complete, most of the internal
circuitry is disabled to minimize quiescent current draw.
Short−circuit, UVLO, output OVP and over−temperature
protections are inactive in Forced Bypass Mode.
from Boost Mode to Bypass Mode, if V goes above target
IN
V . In Bypass Mode, the device fully enhances both Q1
OUT
and Q3 to provide a very low impedance path from VIN to
VOUT. Entry to the Bypass Mode is triggered by condition
In Forced Bypass Mode, V
can follow V below
OUT
IN
V
.
OUT(MIN)
where V > V
and no switching has occurred during
IN
OUT
past 5 ms. To soften the entry to Bypass Mode, Q3 is driven
as a linear current source for the first 5 ms. Bypass Mode exit
VSEL
V
SEL
can be asserted in anticipation of a positive load
is triggered when V
reaches the target V
voltage.
OUT
OUT
transient. Raising V
amount and V
output voltage in 20 ms. The functionality can also be utilized
to mitigate undershoot during severe line transients, while
minimizing V
to save power.
increases V
by a fixed
SEL
OUT(MIN)
During Automatic Bypass Mode, the device is short−circuit
protected by voltage comparator tracking the voltage drop
is stepped to the corresponding target
OUT
from V to V
; if the drop exceeds 200 mV, FAULT is
OUT
IN
declared.
during more benign operating conditions
OUT
With sufficient load to enforce CCM operation, the
Bypass Mode to Boost Mode transition occurs at the target
V . The corresponding input voltage at the transition
OUT
EN
Setting the EN pin voltage below 0.4 V disables the part.
Placing the voltage above 1.2 V enables the part. Do not
connect the EN pin to VIN. A logic voltage of 1.8 V should
control the EN pin and enable / disable the device. The EN
point is:
Ŧ
(eq. 1)
VIN v VOUT ) ILOAD * (DCRL ) RDS(ON)P) RDS(ON)BYP
The Bypass Mode entry threshold has 25 mV hysteresis
imposed at VOUT to prevent cycling between modes. The
pin should be pulled HIGH after the V voltage has reached
IN
a minimum voltage of 2.3 V.
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11
FAN48630J
APPLICATION INFORMATION
Output Capacitance (COUT
)
present. If a high−current load and high capacitance are both
present during soft−start, the circuit may fail to achieve
regulation and continually attempts soft−start, only to have
the output capacitance discharged by the load when in
a FAULT state.
Stability
The effective capacitance (C ) of small, high−value,
ceramic capacitors decreases as bias voltage increases.
FAN48630J is guaranteed for stable operation with the
EFF
minimum value of C
(C ) outlined in Table 11.
EFF(MIN)
Output Voltage Ripple
EFF
Output voltage ripple is inversely proportional to C
.
OUT
During t , when the boost switch is on, all load current is
ON
Table 11. Minimum CEFF Required for Stability
Operating Conditions
supplied by C . Output ripple is calculated as:
OUT
ILOAD
COUT
V
(V)
I
(mA)
C
(ꢁ Fꢃ
VRIPPLE(P*P) + tON
*
(eq. 3)
(eq. 4)
OUT
LOAD
EFF(MIN)
3.15
0 to 1500
15
and
VIN
VOUT
C
varies with manufacturer, material, and case size.
EFF
* ǒ1 * Ǔ
tON + tSW * D + tSW
therefore:
Inductor Selection
Recommended nominal inductance value is 0.47 mH.
FAN48630J employs valley−current limiting; peak
inductor current can reach 3.8 A for a short duration during
overload conditions. Saturation effects cause the inductor
current ripple to become higher under high loading as only
valley of the inductor current ripple is controlled.
A 0.33 mH inductor can be used for improved transient
performance.
ILOAD
COUT
VIN
* ǒ1 * Ǔ*
VOUT
(eq. 5)
(eq. 6)
VRIPPLE(P*P) + tSW
and
1
fSW
tSW
+
Layout Recommendations
Startup
The layout recommendations below highlight various
top−copper pours using different colors.
Input current limiting is in effect during soft−start, which
limits the current available to charge C
additional capacitance on the V
to achieve regulation within the limits described in the
Startup section, a FAULT occurs, causing the circuit to shut
down then restart after 20 ms. If the total combined output
capacitance is very high, the circuit may not start on the first
attempt, but eventually achieves regulation if no load is
and any
line. If the output fails
To minimize spikes at V
, C
must be placed as
OUT
OUT
OUT
close as possible to PGND and VOUT, as shown in
Figure 22.
For thermal reasons, it is suggested to maximize the pour
area for all planes other than SW. Especially the ground pour
should be set to fill all available PCB surface area and tied
to internal layers with a cluster of thermal vias.
OUT
Figure 22. Top Layer
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12
FAN48630J
Figure 23. Layer 2
Figure 24. Layer 3
Table 12. PRODUCT−SPECIFIC DIMENSIONS
Product
D
E
X
Y
FAN48630BUC31JX
1.780 0.030
1.780 0.030
0.290
0.290
TINYBOOST is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
FAIRCHILD is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP16 1.78x1.78x0.586
CASE 567SY
ISSUE O
DATE 30 NOV 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
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DOCUMENT NUMBER:
DESCRIPTION:
98AON16621G
WLCSP16 1.78x1.78x0.586
PAGE 1 OF 1
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