FAN501AMPX [ONSEMI]
离线 DCM / CCM 反激 PWM 控制器，适用于充电器应用;
| 型号： | FAN501AMPX |
| 厂家： | 
ONSEMI |
| 描述： | 离线 DCM / CCM 反激 PWM 控制器，适用于充电器应用 控制器 |
| 文件： | 总18页 (文件大小：1413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 2014
FAN501A
Offline DCM / CCM Flyback PWM Controller for
Charger Applications
Description
Features
The advanced PWM controller, FAN501A, simplifies
isolated power supply design that requires CC
regulation of the output. The output current is
precisely estimated with only the information in the
primary side of the transformer and controlled with an
internal compensation circuit, removing the output
current-sensing loss and eliminating external CC
control circuitry. With an extremely low operating
current (250 µA), Burst Mode maximizes light-load
efficiency, allowing conformance to worldwide
Standby Mode efficiency guidelines.
.
WSaver® Technology Provides Ultra-Low
Standby Power Consumption for Energy Star’s
5-Star Level (<30 mW)
.
Constant-Current (CC) Control without
Secondary-Side Feedback Circuitry for
Discontinuous Conduction Mode (DCM) and
Continuous Conduction Mode (CCM)
.
.
Dual-Frequency Function Changes Switching
Frequency (140 kHz / 85 kHz) According to Input
Voltage to Maximize Transformer Utilization and
Improve Efficiency
Compared with
a conventional approach using
external control circuit in the secondary side for CC
regulation, the FAN501A can reduce total cost,
component count, size, and weight; while increasing
efficiency, productivity, and system reliability.
High Power Density and High Conversion
Efficiency in CCM Compact Charger Applications
.
.
.
Frequency Hopping to Reduce EMI Noise
High-Voltage Startup
Vo
Precise Maximum Output Power Limit by CC
Regulation through External Resistor Adjustment
.
.
.
Peak-Current-Mode Control with Slope
Compensation to Avoid Sub-Harmonic Oscillation
Maximum
Typical
Minimum
Programmable Over-Temperature Protection with
Latch Mode through External NTC Resistor
Two-Level UVLO Reduces Input Power in Output
Short Situation
Io
Figure 1.
Typical Output V-I Characteristic
.
.
.
VS Over-Voltage Protection with Latch Mode
VDD Over-Voltage Protection with Auto Restart
Available in MLP 4 X 3 Package
Applications
.
.
Battery Chargers for Smart Phones, Feature
Phones, and Tablet PCs
AC-DC Adapters for Portable Devices or Battery
Chargers that Require CV / CC Control
Ordering Information
Operating
Temperature Range
Packing
Method
Part Number
Package
10-Lead, MLP, QUAD, JEDEC MO-220 4 mm x 3 mm,
0.8 mm Pitch, Single DAP
FAN501AMPX
Tape & Reel
-40C to +125C
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
Application Diagram
RSNS
CSNS
LF
TX
+
DR
RSNP
CSNP
Bridge
NP
NS
CO
Vo
CBLK1
CBLK2
-
AC IN
DSNP
RHV
Choke
Fuse
DG
RBias1
RBias2
RF1
Photo
coupler
CComp2
FAN501A
FB
RG2
RG1
HV
RComp1
CComp1
GATE
CS
RCSF
RCS
Shunt
regulator
COMP
SD
DVDD
VDD
VS
RF2
Photo
CFB
SGND
RVS1
RCOMP
RSD
NTC
coupler
NA
PGND
CVDD
CVS
RVS2
Figure 2.
Typical Application
Internal Block Diagram
VDD
SD Fault
OTP Fault
VSOVP Fault
HV
8
Latch
Protection
1
PWM Control Block
GATE
VDD OVP Fault
7.5V
Latch released
10 PGND
VDD UVLO
17.5V / 6V
VDD
2
Internal bias 5V
VDD OVP Fault
OCP Fault
Slope
VCS-LIM
Burst / Green
Mode
5V
Compensation
COMV
ZFB
VSAW
COMI
9
4
CS
LEB
Σ
FB
6
AV
IO Estimator
5V
Frequency
Hopping
CC Control
Correction
COMP
ISD
SD
7
SD Fault
VSH
Zero Current
Detector
Line Voltage
Detector
VSD-TH
S/H
VSOVP Fault
VVS-OVP
S/H = Sample and Hold
5
3
SGND
VS
Figure 3.
Function Block Diagram
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
2
Marking Information
F- Fairchild Logo
Z: Assembly Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: Package Type (MP=MLP)
M: Manufacture Flow Code
ZXYTT
FAN501A
TM
Figure 4.
Top Mark
Pin Configuration
HV
8
SD
7
6
5
FB
CS
9
SGND
COMP
FAN501A
PGND 10
4
1
2
3
GATE VDD
Figure 5.
VS
Pin Assignments
Pin Definitions
Pin #
Name
Description
PWM Signal Output. This pin has an internal totem-pole output driver to drive the power
MOSFET. The gate driving voltage is internally clamped at 7.5 V.
1
GATE
Power Supply. IC operating current and MOSFET driving current are supplied through this pin.
This pin is typically connected to an external capacitor.
2
3
VDD
VS
Voltage Sense. This pin detects the output voltage information and diode current discharge time
based on the voltage of the auxiliary winding. It also senses sink current through the auxiliary
winding to detect input voltage information.
CC Control Correction. This pin connects to external resistor to program the CC control
correction weighting.
4
5
COMP
SGND
Signal Ground
Feedback. An opto-coupler is typically connected to this pin to provide feedback information to
the internal PWM comparator. This feedback is used to control the duty cycle in Constant-
Voltage (CV) regulation.
6
FB
Shut Down. This pin is implemented for external over-temperature protection by connecting to
an NTC thermistor.
7
8
SD
HV
High Voltage. This pin connects to a DC bus for high-voltage startup.
Current Sense. This pin connects to a current-sense resistor to detect the MOSFET current for
Peak-Current-Mode control for output regulation. The current-sense information is also used to
estimate the output current for CC regulation.
9
CS
10
PGND
Power Ground
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VHV
Parameter
Min.
Max.
500
30
Unit
V
HV Pin Input Voltage
DC Supply Voltage
VVDD
VVS
V
VS Pin Input Voltage
CS Pin Input Voltage
FB Pin Input Voltage
COMP Pin Input Voltage
SD Pin Input Voltage
Power Dissipation (TA=25C)
-0.3
-0.3
-0.3
-0.3
-0.3
6.0
V
VCS
6.0
V
VFB
6.0
V
VCOMP
VSD
6.0
V
6.0
V
PD
850
150
mW
θJA
Thermal Resistance (Junction-to-Air)
Thermal Resistance (Junction-to-Case)
Operating Junction Temperature
C/W
C/W
C
θJC
TJ
10
-40
-40
+150
+150
+260
TSTG
TL
Storage Temperature Range
C
Lead Temperature (Wave soldering or IR, 10 Seconds)
C
Human Body Model, ANSI/ESDA/JEDEC JS-001-2012
(Except HV Pin)
5.0
2.0
Electrostatic
Discharge
ESD
kV
Capability(3)
Charged Device Model, JEDEC:JESD22_C101
(Except HV Pin)
Notes:
1. All voltage values, except differential voltages, are given with respect to the GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD ratings including HV pin: HBM=3.5 kV, CDM=1.25 kV.
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
4
Electrical Characteristics
VDD=15 V and TJ=-40~125C unless noted.
Symbol
HV Section
VHV-MIN
Parameter
Conditions
Min. Typ. Max. Unit
Minimum Startup Voltage on HV Pin
Supply Current Drawn from HV Pin
Leakage Current Drawn from HV Pin
30
5.0
V
IHV
VHV=120 V, VDD=0 V
1.2
2.0
0.8
mA
μA
IHV-LC
VHV=500 V, VDD=VDD-OFF+1 V
10.0
VDD Section
VDD-ON
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Threshold Voltage for HV Startup
Threshold Voltage for Latch Release
Startup Current
VDD Rising
VDD Falling
16.0
5.5
17.5
6.0
18.5
6.5
V
V
VDD-OFF
VDD-HVON
VDD-DLH
IDD-ST
3.4
4.4
5.1
V
2.50
150
V
VDD=VDD-ON-0.16 V
250
4.0
μA
VCS=5.0 V, VS=3 V, VFB=3 V,
VDD=15 V, CGATE=1 nF
IDD-OP
Operating Supply Current
3.5
mA
VCS=0.3 V, VS=0 V, VFB=0 V
VDD=VDD-ONVDD-OVP10 V,
CGATE=1 nF
IDD-Burst
Burst Mode Operating Supply Current
VDD Over-Voltage Protection Level
250
300
μA
VDD-OVP
Oscillator Section
26.5
28.0
29.5
V
Operating Frequency, IVS Below
fOSC--H
fOSC--L
VCS=5 V, VS=2.5 V, VFB=6 V
VCS=5 V, VS=2.5 V, VFB=4 V
133
79
140
85
147
91
kHz
kHz
Threshold IVS-L(Low Line)(4)
Operating Frequency, IVS Over
Threshold IVS-H(High Line)(4)
ΔfHopping-H Frequency Hopping Range, High Line
ΔfHopping-L Frequency Hopping Range, Low Line
VCS=0.5 V, VS=0.7 V, VFB=3 V ±5.5 ±7.0 ±8.5
VCS=0.5 V, VS=0.0 V, VFB=3 V ±2.5 ±4.0 ±5.5
2.54
kHz
kHz
ms
ΔtHopping
Frequency Hopping Period
Feedback Input Section
ZFB
AV
FB Pin Input Impedance
36
41
48
kΩ
V/V
V
Internal Voltage Attenuator of FB Pin
FB Pin Pull-Up Voltage
1/2.5
5.50
VFB-Open
FB Pin Open
5.00
1.60
5.90
1.80
FB Threshold to Enable Gate Drive in
Burst Mode(4)
VFB Rising with VCS=0.3 V,
VS=0 V
VFB-Burst-H
VFB-Burst-L
1.70
1.65
V
V
FB Threshold to Disable Gate Drive in
Burst Mode(4)
VFB Falling with VCS=0.3 V,
VS=0 V
1.55
1.75
Over-Temperature Protection Section
TOTP
Threshold Temperature for Over-Temperature Protection
140
C
Shutdown Function Section
ISD
SD Pin Source Current
VCS=0.3 V
VCS=0.3 V
85
100
115
μA
Threshold Voltage for Shutdown
Function Enable
VSD-TH
0.85
1.00
1.15
V
Continued on the following page…
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
5
Electrical Characteristics
VDD=15 V and TJ=-40~125C unless noted.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Voltage-Sense Section
ITC
Temperature-Independent Bias Current VCS=5 V, VFB=3 V
VS Source Current Threshold to fOSC-L Operation
VS Source Current Threshold to fOSC-H Operation
8.75 10.00 11.25
μA
μA
IVS-H
IVS-L
750
680
160
μA
IVS-Brownout VS Source Current Threshold to Enable Brownout
μA
VVS-OVP
NVS-OVP
Output Over-Voltage Protection with VS Sampling Voltage(4)
Output Over-Voltage Protection Debounce Cycle Counts(4)
3.10 3.20
8
3.30
V
Cycle
Current-Sense Section
VVR
Internal Reference Voltage for CC Regulation
2.460 2.500 2.540
2.405 2.430 2.455
12.0
V
V
Variation Test Voltage on CS Pin for
CC Regulation(4)
VCS=0.375 V, VCOMP= 1.59 V,
VS= 6 V
VCCR
KCCM
VCS-LIM
tPD
Design Parameter in CC Regulation
Current Limit Threshold Voltage
GATE Output Turn-Off Delay
Leading-Edge Blanking Time
Slope Compensation
V/V
V
0.80 0.85
100
0.90
200
200
ns
tLEB
150
ns
VSlope
Maximum Duty Cycle
66.6
mV/μs
Constant Current Correction
VCS=0.3 V, VFB=2.5 V,
VS=0.3 V
ICOMP-H
COMP Pin Source Current as VS=0.3 V
25
35
45
μA
GATE Section
VCS=0.6 V, VS=0.3 V,
VFB=1.7 V
tON-MIN
Minimum On Time
450
550
650
ns
VCS=0.6 V, VS=0.5 V,
VFB=1.7 V
tON-MIN-Limit Limited Minimum On Time
0.95 1.20 1.45
μs
DCYMAX
VGATE-L
Maximum Duty Cycle
VCS=0.6 V, VS=0 V, VFB=4 V
60.0 68.5
0
77.0
1.5
%
V
Gate Output Voltage Low
VDD-PMOS-ON Internal Gate PMOS Driver ON
VDD-PMOS-OFF Internal Gate PMOS Driver OFF
7.0
9.0
100
30
7.5
9.5
140
50
8.0
V
10.0
180
70
V
tr
tf
Rising Time
Falling Time
VCS=0 V, VS=0 V, CGATE=1 nF
VCS=0 V, VS=0 V, CGATE=1 nF
VDD=25 V
ns
ns
V
VGATE-CLAMP Gate Output Clamping Voltage
7.0
7.5
8.0
Notes:
4. TJ guaranteed range at 25C.
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
6
Typical Performance Characteristics
18.1
17.8
17.5
17.2
16.9
16.6
16.3
6.05
6.00
5.95
5.90
5.85
5.80
5.75
-40
-30
-15
0
25
50
75
85
100 125
-40
-30
-15
0
25
50
75
85
100 125
Temperature ( C)
Temperature ( C)
Figure 6.
VDD Turn-On Threshold Voltage (VDD-ON
)
Figure 7.
VDD Turn-Off Threshold Voltage (VDD-OFF
vs. Temperature
)
vs. Temperature
3.9
3.7
3.5
3.3
3.1
2.9
280
270
260
250
240
230
2.7
-40
220
-40
-30
-15
0
25
50
75
85
100 125
-30
-15
0
25
50
75
85
100 125
Temperature ( C)
Temperature ( C)
Figure 8.
Operating Supply Current (IDD-OP
)
Figure 9.
Burst Mode Operating Supply Current
(IDD-Burst) vs. Temperature
vs. Temperature
149
146
143
140
137
134
131
94
91
88
85
82
79
76
-40
-30
-15
0
25
50
75
85
100 125
-40
-30
-15
0
25
50
75
85
100 125
Temperature ( C)
Temperature ( C)
Figure 10. Operating Frequency, IVS < IVS-L Threshold Figure 11. Operating Frequency while IVS < IVS-H
(fOSC-H) vs. Temperature Threshold (fOSC-L) vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FAN501A • Rev. 1.0.0
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
2.56
2.54
2.52
2.50
2.48
2.46
2.44
3.35
3.30
3.25
3.20
3.15
3.10
3.05
-40
-30
-15
0
25
50
75
85
100 125
-40
-30
-15
0
25
50
75
85
100 125
Temperature ( C)
Temperature ( C)
Figure 12. Output OVP with VS Sampling Voltage
Figure 13. Internal Reference Voltage for CC
(VVS-OVP) vs. Temperature
Regulation (VVR) vs. Temperature
2.49
2.47
2.45
2.43
2.41
2.39
2.37
10.9
10.6
10.3
10.0
9.7
9.4
9.1
-40
-30
-15
0
25
50
75
85
100 125
-40
-30
-15
0
25
50
75
85
100 125
Temperature ( C)
Temperature ( C)
Figure 14. Variation Test Voltage on CS Pin for CC Figure 15. Temperature-Independent Bias Current
Regulation (VCCR) vs. Temperature (ITC) vs. Temperature
0.88
0.87
0.86
0.85
0.84
0.83
0.82
79
76
73
70
67
64
61
-40
-30
-15
0
25
50
75
85
100 125
-40
-30
-15
0
25
50
75
85
100 125
Temperature ( C)
Temperature ( C)
Figure 16. Current Limit Threshold Voltage (VCS-LIM
)
Figure 17. Maximum Duty Cycle (DCYMAX)
vs. Temperature
vs. Temperature
8.1
7.9
7.7
7.5
7.3
7.1
6.9
-40
-30
-15
0
25
50
75
85
100 125
Temperature ( C)
Figure 18. Gate Output Clamping Voltage
(VGATE-Clamp) vs. Temperature
© 2014 Fairchild Semiconductor Corporation
FAN501A • Rev. 1.0.0
www.fairchildsemi.com
8
Functional Description
FAN501A is an offline flyback converter controller that
offers constant output voltage (CV) regulation through
opto-coupler feedback circuitry and constant output
current (CC) regulation with primary-side control.
Advanced output current estimation technology allows
stable CC regulation regardless of the power stage
operation mode: Continuous Conduction Mode (CCM)
or Discontinuous Conduction Mode (DCM).
while COMI is saturated to HIGH level. During CC
regulation, COMI determines the duty cycle while
COMV is saturated to HIGH level.
VBLK
Vo
GATE
PWM Control
Block
ZCOMP
Dual-switching-frequency operation adaptively selects
the operational frequency between 85 kHz and 140 kHz
Slope
Compenastion
according to the line voltage. As
a result, the
COMV
CS
transformer can be fully utilized and high efficiency is
maintained over entire line range. A frequency-hopping
function is incorporated to reduce EMI noise.
VSAW
AV
Σ
COMI
FB
IO Estimator
Line voltage information through transformer auxiliary
winding is used for dual-switching frequency selection
and line voltage CC correction.
VS
Zero Current
Detector
Figure 19. Simplified CV / CC PWM Control Circuit
mWSaver® technology, including high-voltage startup
and ultra-low operating current in Burst Mode, enables
system compliance with Energy Star’s 5-star
requirement of <30 mW standby power consumption.
CV
CC
COMI
COMV
VSAW
Protections such as VDD Over-Voltage Protection (VDD
OVP), VS Over-Voltage Protection (VS OVP), internal
Over-Temperature Protection (OTP), and brownout
protection improve reliability.
All these innovative technologies allow the FAN501A to
offer low total cost, reduced component counts, small
size / weight, high conversion efficiency, and high power
density for compact charger / adapter applications
requiring CV / CC control.
GATE
Figure 20. PWM Operation for CV / CC Regulation
CV / CC PWM Operation Principle
Primary-Side Constant Current Operation
Figure 19 shows a simplified CV / CC PWM control
circuit of the FAN501A. The Constant Voltage (CV)
regulation is implemented in the same manner as the
conventional isolated power supply, where the output
voltage is sensed using a voltage divider and compared
with the internal reference of the shunt regulator to
generate a compensation signal. The compensation
signal is transferred to the primary side through an opto-
coupler and scaled down by attenuator AV to generate a
COMV signal. This COMV signal is applied to the PWM
comparator to determine the duty cycle.
Figure 21 and Figure 22 show the key waveforms of a
flyback converter operating in DCM and CCM,
respectively. The output current of each mode is
estimated by calculating the average of output diode
current over one switching cycle:
푡푆
0
ꢀ ꢁ
퐼퐷 푡 푑푡
[퐼퐷]퐴푅퐸퐴
(1)
퐼푂 =< 퐼퐷 >푡 =
=
푆
푡푆
푡푆
The area of output diode current in both DCM and CCM
operation can be expressed in a same form, as a
product of diode current discharge time (tDIS) and diode
current at the middle of diode discharge (ID-Mid), such as:
The Constant Current (CC) regulation is implemented
internally with primary-side control. The output current
estimator calculates the output current using the
transformer primary-side current and diode current
discharge time. By comparing the estimated output
current with internal reference signal, a COMI signal is
generated to determine the duty cycle.
[퐼퐷]퐴푅퐸퐴 = 퐼퐷−푀푖푑 ∙ 푡퐷퐼푆
(2)
In steady state, ID_Mid can be expressed as:
푁푃
These two control signals, COMV and COMI, are
compared with an internal sawtooth waveform (VSAW) by
two PWM comparators to determine the duty cycle.
Figure 20 illustrates the outputs of two comparators
,combined with an OR gate, to determine the MOSFET
turn-off instant. Of COMV and COMI, the lower signal
determines the duty cycle. As shown in Figure 20,
during CV regulation, COMV determines the duty cycle
퐼퐷−푀푖푑 = 퐼퐷푆_푀푖푑
∙
(3)
푁푆
where IDS_Mid is primary-side current at the middle of
MOSFET conduction time and NP/NS is primary-to-
secondary turn ratio.
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
9
The unified output current equation both for DCM and
CCM operation is obtained as:
tDIS(n)
0.85∙tDIS(n-1)
푁푃
푡퐷퐼푆 푁푃 푉퐶푆_푀푖푑 푡퐷퐼푆
200mV
(4)
퐼푂 =
∙ 퐼퐷푆_푀푖푑
∙
=
∙
∙
푁
푆
푡푆
푁
푆
푅퐶푆
푡푆
VS
VCS_Mid is obtained by sampling the current-sense
voltage at the middle of the MOSFET conduction time.
The diode current discharge time is obtained by
detecting the diode current zero-crossing instant. Since
the diode current cannot be sensed directly in the
primary side, Zero-Crossing Detection (ZCD) is
accomplished indirectly by monitoring the auxiliary
winding voltage in the primary side. When the diode
current reaches zero, the transformer winding voltage
begins to drop sharply. To detect the corner voltage, the
VS is sampled, called VSH, at 85% of diode current
discharge time (tDIS) of the previous switching cycle and
compared with the instantaneous VS voltage. When
instantaneous voltage of the VS pin drops below VSH by
more than 200 mV, the ZCD of diode current is
obtained, as shown in Figure 23.
VSH
ZCD
Figure 23. Operation Waveform for ZCD Function
Line Voltage Detection and its Utilization
The FAN501A indirectly senses line voltage using the
current flowing out of the VS pin while the MOSFET is
turned on, as illustrated in Figure 25 and Figure 26.
During the MOSFET turn-on period, auxiliary winding
The output current can be programmable by setting
current sensing resistor as:
voltage, VAux, reflects input bulk capacitor voltage, VBLK
,
by the transformer coupling between primary and
auxiliary. During MOSFET conduction time, the line
voltage detector clamps the VS pin voltage ~0.5 V and
the current, IVS, flowing from the VS pin is expressed as:
NP VCCR
1
RCS
(5)
IO NS KCC
where VCCR is the internal voltage for CC control and
KCC is the IC design parameter, 12 for the FAN501A.
NA / NP VBLK
0.5
IVS
+
(6)
RVS1
RVS1 / /RVS 2
IDS-Mid
IDS
Typically, the second term in Equation (6) can be
ignored because it is much smaller than the first term.
The current, IVS, is approximately proportional to the line
voltage, calculated as:
½ tON
ID-Mid = NPS∙IDS-Mid
IO = <ID>Ts
ID
NA / NP
IVS
VBLK
(7)
½ tDIS
RVS1
The IVS current, reflecting the line voltage information, is
used for dual switching frequency operation, CC control
correction weighting, and brownout protection; as
illustrated in Figure 25.
VS
tON
tDIS
tS
Dual Switching Frequency
The FAN501A changes the switching frequency
between 85 kHz and 140 kHz according to the line
voltage. It is typical to design the flyback converter to
operate in CCM for low line and DCM in high line.
Therefore, the peak transformer current decreases as
the operation mode changes from CCM to DCM, as
shown in Figure 24(a), for single-frequency operation.
The transformer is not fully utilized at high line when a
single switching frequency is used. The peak
transformer current can be maintained almost constant
when the flyback converter operates at lower frequency
at high line, as illustrated in Figure 24(b). This allows full
transformer utilization and improves the efficiency by
decreasing the switching losses at high line.
Figure 21. Waveforms of DCM Flyback Converter
IDS-Mid
IDS
½ tON
ID-Mid = NPS∙IDS-Mid
IO = <ID>Ts
ID
½ tDIS
VS
When IVS is larger than IVS-H (750 µA), the switching
frequency is set at fOSC-L (85 kHz) in CV Mode. When IVS
is less than IVS-L (680 µA), the switching frequency is set
at fOSC-H (140 kHz) in CV Mode. For the universal line
range, the frequency change should occur between 132
~ 180 VAC to avoid the transition within the actual
tON
tDIS
tS
Figure 22. Waveforms of CCM Flyback Converter
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
10
operation range. It is typical to design the voltage divider
for the VS pin such that frequency change occurs at
170 VAC (VDC-170 VAC = 240 V); calculated as:
NA / NP
RVS1
240
(8)
GATE
IVS -H
With the value of RVS1 determined from Equation (8), the
switching frequency drops to 85 kHz as line voltage
increases above 170 VAC, while switching frequency
increases to 140 kHz, as line voltage drops <155 VAC
.
VAux
IDS
IDS
NA
NS
-
VBLK
VDS
VDS
1/140kHz
1/140kHz
High line
(a) Single frequency operation
Low line
0.5V
VS
IDS
IDS
tON
tS
VDS
VDS
Figure 26. Waveforms for Line Voltage Detection
1/140kHz
1/85kHz
High line
Low line
Maximum Power Limit by Precision CC Control
(b) Dual frequency operation
Primary-side current-sensing voltage is used to estimate
the output current for CC regulation. However, the
actual output current regulation is also affected by the
turn-off delay of the MOSFET, as illustrated in Figure
27. While FAN501A samples the CS pin voltage at the
half on-time of gate drive signal, the actual turn-off is
delayed by the MOSFET gate charge and driving
current resulting in peak current detection error as:
Figure 24. Peak Switch Current, Single- and
Dual-Frequency Operation
Brownout Protection
Line voltage information is also used for brownout
protection. When the IVS current out of the VS pin during
the MOSFET conduction time is less than 160 μA for
longer than 30 ms, the brownout protection is triggered.
When setting RVS1 as calculated in Equation (8), the
VDL
PK
brownout level is set at 30 VAC
.
IDS
tOFF.DLY
(9)
Lm
Pri.
NP
VBLK
where Lm is the primary side magnetic inductance.
As can be seen, the error is proportional to the line
voltage. FAN501A has an internal correction function to
improve CC regulation, as shown in Figure 28. Line
information is obtained through the line voltage detector
as shown in Figure 25 and Figure 26 and this
information is used for the CC regulation correction. The
correction gain can be programmed using external
resistor RCOMP on the COMP pin. This correction
current, ILVF, flows through internal resistor, RLVF, and
external resistor, RCSF, to introduce offset voltage on
current sensing voltage. Thus, the primary current
detection error affected by line voltage and turn-off
delay is corrected for better CC regulation. The RCOMP
resistor can be calculated as:
5V
IVS
GATE
VAux
Aux.
Line signal
Line Voltage
Detector
RVS1
NA
IVS
VS
VS_Offset
RVS2
NP
RCS
tOFF.DLY
RCOMP
RVS1
KCOMP
(10)
NA RLVF + RCSF
Lm
Figure 25. Line Voltage Detection Circuit
where RLVF is the internal resistor on the IC, which is
2.0 kΩ, and KCOMP is the design factor of the IC, which
is 3.745 MΩ.
© 2014 Fairchild Semiconductor Corporation
FAN501A • Rev. 1.0.0
www.fairchildsemi.com
11
The turn-off delay should be obtained by measuring the
time between the falling edge and actual turn-off instant
of MOSFET, as illustrated in Figure 27.
tOFF.DLY
VO
IDS RCS
VFB-Burst-H
VFB-Burst-L
RCS IDS
PK
IDS
R
CS
IDS.SH RCS
VFB
Actual diode current
NP
NS
PK
ID
Estimated diode current
GATE
NP
NS
IDS.SH
Figure 29. Burst-Mode Operation
tDIS
Frequency Hopping
GATE (#2)
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth of the EMI test equipment, allowing
compliance with EMI limitations.
VGS
Figure 27. CC Control Correction Concept
Pri.
Slope Compensation
VBLK
5V
The sensed voltage across the current-sense resistor is
used for current-mode control and pulse-by-pulse
current limiting. A synchronized ramp signal with a
positive slope is added to the current-sense information
at each switching cycle, improving noise immunity
during current mode control and avoiding sub-harmonic
oscillation during CCM operation.
NP
CC Control
ILVF
Correction
COMP
Line Signal
RCOMP
GATE
RLVF
Line Voltage
RCSF
Detector
Aux.
CS
RVS1
RCS
NA
Zero Current
Detector
IO Estimator
RVS2 VS
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse by the spike, a 150 ns
Figure 28. CC Correction Circuit
leading-edge
blanking
time
is
incorporated.
Pulse-by-Pulse Current Limit
Conventional RC filtering can therefore be omitted.
During this blanking period, the current-limit comparator
is disabled and it cannot switch off the gate driver.
Since the peak transformer current is controlled by a
feedback loop, the peak transformer current is not
properly controlled when the feedback loop is saturated
to HIGH, which typically occurs under startup or
overload conditions. To limit the current, a pulse-by-
pulse current limit forces the gate drive signal to turn off
when the CS pin voltage reaches the current-limit
threshold (VCS-LIM) in normal operation.
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter. Though slope
compensation helps alleviate this problem, precautions
should be taken to improve the noise immunity. Good
placement and layout practices are important. Avoid
long PCB traces and component leads and locate
bypass capacitor as close to the PWM IC as possible.
Burst Mode Operation
The power supply enters Burst Mode at no-load or
extremely light-load condition. As shown in Figure 29,
when VFB drops below VFB-Burst-L, the PWM output shuts
off and the output voltage drops at a rate dependent on
load current. This causes the feedback voltage to rise.
Once VFB exceeds VFB-Burst-H, the internal circuit starts to
provide a switching pulse. The feedback voltage then
falls and the process repeats. In this manner, Burst
Mode alternately enables and disables switching of the
MOSFET to reduce the switching losses in Standby
Mode. In Burst Mode, the operating current is reduced
from 3.5 mA to 250 μA to minimize power consumption.
High Voltage (HV) Startup
Figure 30 shows the high-voltage (HV) startup circuit for
FAN501A applications. The JFET is used to internally
implement the high-voltage current source (see Figure
31 for characteristics). Technically, the HV pin can be
directly connected to voltage (VBLK) on an input bulk
capacitor. To improve reliability and surge immunity,
however, it is typical to use a ~100 kΩ resistor between
the HV pin and bulk capacitor voltage. The actual HV
current with a given bulk capacitor voltage and startup
resistor is determined by the intersection of V-I
characteristics line and load line, as shown in Figure 31.
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
12
During startup, the internal startup circuit is enabled and
the bulk capacitor voltage supplies the current, IHV, to
charge the hold-up capacitor, CVDD, through RHV. When
VDD reaches VDD-ON, the internal HV startup circuit is
disabled and the IC starts PWM switching. Once the HV
startup circuit is disabled, the energy stored in CVDD
should supply the IC operating current until the
transformer auxiliary winding voltage reaches the
nominal value. Therefore, CVDD should be designed to
prevent VDD from dropping to VDD-OFF before the auxiliary
The supply current drawn from the HV pin charges the
hold-up capacitor. When VDD reaches the turn-on
voltage of 17.5 V, normal operation resumes. In this
manner, Auto-Restart Mode alternately enables and
disables MOSFET switching until the abnormal
condition is eliminated, as shown in Figure 32.
Power On
VDS
winding builds up enough voltage to supply VDD
.
VBLK
Primary-Side
Fault
Occurs
VDD
VDD-OVP
NP
Fault
Removed
RHV
CBLK
VDD-ON
VDD-OFF
VDD-HV-ON
IHV
HV
Operating Current
IDD-OP
DVDD
VDD
Aux.
NA
IDD-Brust
IDD-ST
CVDD
6V/17V
Figure 32. Auto-Restart Mode Operation
When a Latch Mode protection is triggered, PWM
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD turn-off
voltage of 5.8 V, the internal startup circuit is enabled
without resetting the protection and the supply current
drawn from HV pin charges the hold-up capacitor. Since
the protection is not reset, the IC does not resume PWM
switching even when VDD reaches the turn-on voltage of
17.5 V, disabling HV startup circuit. Then VDD drops
again down to 5.8 V. In this manner, Latch Mode
protection alternately charges and discharges VDD until
there is no more energy in DC link capacitor. The
protection is reset when VDD drops to 2.5 V, which is
allowed only after power supply is unplugged from the
AC line, as shown in Figure 33.
Figure 30. HV Startup Circuit
IHV
5.0mA
VBLK
RHV
2.0mA
1.2mA
AC Disconnected
Power On
VDS
100V
200V
300V
400V
500V
VHV
Power
On Again
VBLK
Figure 31. V-I Characteristic of HV Pin
VDD
Protection
Triggered
Protections
The protection functions include VDD over-voltage
protection (VDD OVP), brownout protection, VS over-
voltage protection (VS OVP), internal over-temperature
protection (OTP), and externally triggered shutdown
(SD) protection. The VDD OVP and brownout protection
are implemented as Auto-Restart Mode. VS OVP, OTP,
and SD protections are implemented as Latch Mode.
VDD-ON
Protection
Reset
VDD-OFF
VDD-Burst
VDD-LH
Operating Current
IDD-OP
When an Auto-Restart Mode protection is triggered,
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD turn-off
voltage of 5.8 V; the protection is reset, and next step to
reduced operation current until startup circuit is enabled.
IDD-Burst
IDD-ST
Figure 33. Latch Mode Operation
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
13
Aux.
NA
VDD Over-Voltage-Protection
3.20V
VDD over-voltage protection prevents damage from over-
voltage exceeding the IC voltage rating. When VDD
exceeds 28 V due to an abnormal condition, protection
is triggered. This protection is typically caused by an
open circuit in the secondary-side feedback network.
RVS1
D
Q
S/H
RVS2
PWM
VSOVP Dedounce
time
Latch
Protection
Brownout Protection
Brownout protection is implemented through line voltage
detection circuit using the auxiliary winding, as shown in
Figure 25 and Figure 26. When the current flowing out
of the VS pin during the MOSFET conduction time is
smaller than 160 μA for longer than 30 ms, the brownout
protection is triggered.
Counter
Figure 34. VS OVP Protection Circuit
Externally Triggered Shutdown
By pulling the SD pin voltage below threshold voltage,
VSD-TH (1.0 V); shutdown can be externally triggered and
the FAN501A enters Latch Mode protection. It can be
also used for external OTP protection by connecting an
NTC thermistor between the shutdown (SD)
programming pin and ground. An internal constant
current source, ISD (100 µA), introduces voltage drop
across the thermistor. Resistance of the NTC thermistor
becomes smaller as the ambient temperature increases,
which reduces the voltage drops across the thermistor.
When the voltage of the SD pin is less than threshold
voltage VSD-TH (1.0 V), OTP protection is triggered.
Over-Temperature Protection (OTP)
If the junction temperature exceeds 140°C (TOTP), the
internal temperature-sensing circuit shuts down PWM
output and enters Latch Mode protection.
Fold-Back Point and Over-Voltage Protection (VS
OVP)
Generally, the fold-back point in CC regulation as output
drops is determined by the VDD-OFF level. Thus, the fold-
back level mainly depends on the characteristics of the
VDD diode and transformer. For VS pin voltage divider
design, RVS1 is obtained from Equation (8), and RVS2 is
determined by the VSOVP function as:
5V
−1
푉푂−푂푉푃 푁퐴
100μA
(11)
푅푉푆2 = 푅푉푆1 ∙ ꢂ
∙
− 1ꢃ
푉푉푆−푂푉푃 푁푆
Latch
Protection
where VO-OVP is the output over-voltage protection
threshold level.
1.0V
NTC
Thermistor
VS over-voltage protection prevents damage caused by
output over-voltage condition. Figure 34 shows the
internal circuit of VS OVP. When abnormal system
conditions occur that cause VS sampling voltage to
exceed VVS-OVP (3.2 V) for more than debounce
switching cycles (NVS-OVP), PWM pulses are disabled
and the FAN501A enters Latch Mode protection. VS
over-voltage conditions are usually caused by an open
circuit in the secondary-side feedback network or a fault
condition in the VS pin voltage divider resistors.
Figure 35. Thermal Shutdown Using SD Pin
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
14
Physical Dimensions
4.60
1.80
0.80
4.0
A
B
0.10
C
10
9
PIN#1 QUADRANT
0.40 (10X)
1.60
0.30
0.80
8
7
1
2
1.58
3.60
3.0
3
0.36
0.65 (10X)
0.10
C
6
4
5
0.80
TOP VIEW
0.45
RECOMMENDED LAND PATTERN
0.80 MAX
0.10
0.08
C
C
(0.20)
0.05
0.00
C
SEATING
PLANE
FRONT VIEW
1.85
1.75
0.45
0.30
3
0.80
4
5
6
7
A. DOES NOT FULLY CONFORM TO
JEDEC REGISTRATION, MO-220.
0.80
2
1.63
1.53
B. DIMENSIONS ARE IN MILLIMETERS.
8
1
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
0.36
10
9
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY
0.35(10X)
PIN #1 IDENT
CHAMFER 0.25 mm
SIDE VIEW
SIDE VIEW
0.30(10X)
E. DRAWING FILE NAME : MKT-MLP10Hrev1
0.10
0.05
C
C
A B
BOTTOM VIEW
Figure 36. 10-Lead, MLP, QUAD, JEDEC MO-220 4 mm X 3 mm, 0.8 mm Pitch, Single DAP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/ML/MLP10H.pdf.
For current packing container specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/packing_dwg/PKG-MLP10H.pdf.
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
15
© 2014 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN501A • Rev. 1.0.0
16
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相关型号：
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