FAN5069EMTCX [ONSEMI]
PWM 和 ULDO 控制器组合;
| 型号： | FAN5069EMTCX |
| 厂家： | 
ONSEMI |
| 描述： | PWM 和 ULDO 控制器组合 控制器 开关 光电二极管 |
| 文件： | 总23页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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September 2006
FAN5069
PWM and LDO Controller Combo
Features
Description
■ General Purpose PWM Regulator and LDO Controller
■ Input Voltage Range: 3V to 24V
■ Output Voltage Range: 0.8V to 15V
– VCC
The FAN5069 combines a high-efficiency Pulse-Width-
Modulated (PWM) controller and an LDO (Low DropOut)
linear regulator controller. Synchronous rectification pro-
vides high efficiency over a wide range of load currents.
Efficiency is further enhanced by using the low-side
MOSFET’s RDS(ON) to sense current.
– 5V
■ Shunt Regulator for 12V Operation
■ Support for Ceramic Cap on PWM Output
■ Programmable Current Limit for PWM Output
Both the linear and PWM regulator soft-start are con-
trolled by a single external capacitor, to limit in-rush cur-
rent from the supply when the regulators are first
enabled. Current limit for PWM is also programmable.
■ Programmable Switching Frequency (200KHz to
600KHz)
The PWM regulator employs a summing-current-mode
control with external compensation to achieve fast load
transient response and provide design optimization.
■ RDS(ON) Current Sensing
■ Internal Synchronous Boot Diode
■ Soft-Start for both PWM and LDO
■ Multi-Fault Protection with Optional Auto-restart
■ 16-pin TSSOP Package
FAN5069 is offered in both industrial temperature grade
(-40°C to +85°C) as well as commercial temperature
grade (-10°C to +85°C).
Applications
■ PC/Server Motherboard Peripherals
– VCC_MCH (1.5V), VDDQ (1.5V) and
VTT_GTL (1.25V)
■ Power Supply for
– FPGA, DSP, Embedded Controllers, Graphic Card
Processor, and Communication Processors
■ Industrial Power Supplies
■ High-Power DC-to-DC Converters
Ordering Information
Part Number Operating Temp. Range Pb-Free
Package
Packing Method Qty./Reel
FAN5069MTCX
FAN5069EMTCX
-10°C to +85°C
-40°C to +85°C
Yes
Yes
16-Lead TSSOP
16-Lead TSSOP
Tape and Reel
Tape and Reel
2500
2500
Note: Contact Fairchild sales for availability of other package options.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
Typical Application
RVCC
+12V
3 TO 24V
R8
VCC
C9
15
FAN5069
R(RAMP)
14
11
+5V
BOOT
C5
EN
SS
7
4
Q1
C3
C4
C7
R4
R5
ILIM
HDRV
SW
3
10
9
PWM
PWM OUT
L1
R(T)
2
8
AGND
Q2
C6
LDRV
PWM OUT
R1
13
12
6
PGND
FB
Q3
GLDO
16
1
ULDO
CONTROL
C2
C1
R2
R7
R6
R3
LDO OUT
C8
FBLDO
COMP
5
Figure 1. Typical Application Diagram
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
2
Pin Assignment
1
2
3
4
5
6
7
8
FBLDO
R(T )
ILIM
16
15
14
13
12
11
10
GLDO
VCC
R(RAMP)
LDRV
PGND
BOOT
HDRV
SW
SS
FAN5069
COMP
FB
EN
AGND
9
Figure 2. Pin Assignment
Pin Description
Pin #
Name
FBLDO
R(T)
Description
LDO Feedback. This node is regulated to VREF
1
2
.
Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By plac-
ing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased.
3
4
ILIM
SS
Current Limit. A resistor from this pin to GND sets the current limit.
Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the
LDO during initialization. It also sets the time by which the converter delays when restarting
after a fault occurs. SS has to reach 1.2V before fault shutdown feature is enabled. The LDO
is enabled when SS reaches 2.2V.
5
6
COMP
FB
COMP. The output of the error amplifier drives this pin.
Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combi-
nation with the COMP pin, to compensate the feedback loop of the converter.
7
EN
Enable. Enables operation when pulled to logic high. Toggling EN resets the regulator after a
latched fault condition. This is a CMOS input whose state is indeterminate if left open and
needs to be properly biased at all times.
8
9
AGND
SW
Analog Ground. The signal ground for IC. All internal control voltages are referred to this pin.
Tie this pin to the ground island/plane through the lowest impedance connection available.
Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect
to source of high-side MOSFET and drain of low-side MOSFET.
10
HDRV
High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This
pin is also monitored by the adaptive shoot-through protection circuitry to determine when the
high-side MOSFET is turned off.
11
12
13
BOOT
PGND
LDRV
Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver.
Connect to bootstrap capacitor as shown in Figure 1.
Power Ground. The return for the low-side MOSFET driver. Connect to the source of the low-
side MOSFET.
Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin
is also monitored by the adaptive shoot-through protection circuitry to determine when the
lower MOSFET is turned off.
14
15
R(RAMP) Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage
feed-forward.
VCC
VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic
capacitor as close to this pin as possible. This pin has a shunt regulator which draws current
when the input voltage is above 5.6V.
16
GLDO
Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
3
Absolute Maximum Ratings
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are
not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the condi-
tions for actual device operation. (1)
Parameter
Min.
Max.
6.0
Unit
V
VCC to PGND
BOOT to PGND
SW to PGND
33.0
V
Continuous
-0.5
-3.0
33.0
V
Transient (t < 50nS, F < 500kHz)
33.0
V
HDRV (VBOOT- – VSW
LDRV
)
6.0
V
-0.5
-0.3
6.0
V
All Other Pins
VCC + 0.3
150
V
Maximum Shunt Current for VCC
mA
kV
Electrostatic Discharge Protection (ESD)
Level(2)
HBM
CDM
3.5
1.8
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are referenced to AGND.
2. Using Mil Std. 883E, method 3015.7(Human Body Model) and EIA/JESD22C101-A (Charge Device Model).
Thermal Information
Symbol
TSTG
TL
Parameter
Storage Temperature
Min.
Typ.
Max.
150
300
215
220
715
Unit
°C
-65
Lead Soldering Temperature, 10 Seconds
Vapor Phase, 60 Seconds
°C
°C
Infrared, 15 Seconds
°C
PD
θJC
θJA
Power Dissipation, TA = 25°C
mW
°C/W
°C/W
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient(3)
37
100
Notes:
3. Junction-to-ambient thermal resistance, θJA, is a strong function of PCB material, board thickness, thickness and
number of copper planes, number of vias used, diameter of vias used, available copper surface, and attached heat
sink characteristics.
Recommended Operating Conditions
Symbol
Parameter
Supply Voltage
Conditions
VCC to GND
Commercial
Industrial
Min.
4.5
Typ.
Max.
5.5
Unit
V
VCC
5.0
-10
85
°C
TA
TJ
Ambient Temperature
Junction Temperature
-40
85
°C
125
°C
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
4
Electrical Characteristics
Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
Supply Current
IVCC
VCC Current (Quiescent)
HDRV, LDRV Open
EN = 0V, VCC = 5.5V
•
•
2.6
3.2
200
10
3.8
400
15
mA
μA
IVCC(SD) VCC Current (Shutdown)
IVCC(OP) VCC Current (Operating)
EN = 5V, VCC = 5.0V,
mA
QFET = 20nC, FSW = 200kHz
VSHUNT VCC Voltage(6)
Sinking 1mA to 100mA at VCC
Pin
5.5
5.9
V
Under-Voltage Lockout (UVLO)
UVLO(H) Rising VCC UVLO Threshold
UVLO(L) Falling VCC UVLO Threshold
•
•
4.00
3.60
4.25
3.75
0.50
4.50
4.00
V
V
V
VCC UVLO Threshold
Hysteresis
Soft-Start
ISS
Current
10
2.2
1.2
μA
V
VLDOSTART LDO Start Threshold
VSSOK PWM Protection Enable
Threshold
V
Oscillator
FOSC
Frequency
R(T) = 56KΩ ± 1%
240
160
160
300
200
360
240
600
KHz
KHz
KHz
V
R(T) = Open
Frequency Range
ΔVRAMP Ramp Amplitude
R(RAMP) = 330KΩ
0.4
(Peak-to-Peak)
Minimum ON Time
Reference
F = 200kHz
200
nS.
VREF
Reference Voltage
(Measured at FB Pin)
TA = 0°C to 70°C
•
•
790
788
800
800
160
810
812
mV
mV
mV
TA = -40°C to 85°C
Current Amplifier Reference
(at SW node)
Error Amplifier
DC Gain
GBWP Gain-BW Product
80
25
8
dB
MHz
V/μS.
V
S/R
Slew Rate
10pF across COMP to GND
No Load
Output Voltage Swing
FB Pin Source Current
•
0.5
4.0
IFB
Gate Drive
RHUP
1
μA
HDRV Pull-up Resistor
HDRV Pull-down Resistor
LDRV Pull-up Resistor
LDRV Pull-down Resistor
Sourcing
Sinking
•
•
•
•
1.8
1.8
1.8
1.2
3.0
3.0
3.0
2.0
Ω
Ω
Ω
Ω
RHDN
RLUP
Sourcing
Sinking
RLDN
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Protection/Disable
ILIM
ILIMIT Source Current
9
10
2
11
μA
mA
%
ISWPD SW Pull-down Current
SW = 1V, EN = 0V
VUV
VOV
TSD
Under-Voltage Threshold As % of set point; 2μS noise fil-
•
•
65
75
80
ter
Over-Voltage Threshold
As % of set point; 2μS noise fil-
ter
110
115
160
120
%
Thermal Shutdown
°C
V
Enable Threshold Voltage Enable Condition
Enable Threshold Voltage Disable Condition
•
•
2.0
0.8
V
Enable Source Current
V
CC = 5V
50
μA
LDO(7)
VLDOREF Reference Voltage (mea- TA = 0°C to 70°C
•
•
•
775
770
1.17
800
800
1.2
825
830
1.23
0.3
mV
mV
V
sured at FBLDO pin)
TA = -40°C to 85°C
Regulation
VLDO_DO Drop out Voltage
External Gate Drive
0A ≤ ILOAD ≤ 5A
ILOAD ≤ 5A and RDS-ON < 50mΩ
V
V
CC = 4.75V
CC = 5.6V
•
•
4.5
V
V
5.3
V
Gate Drive Source Current
Gate Drive Sink Current
1.2
mA
μA
400
Notes:
4. All limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality
control.
5. AC specifications guaranteed by design/characterization (not production tested).
6. For a case when VCC is higher than the typical 5V VCC; voltage observed at VCC pin when the internal shunt
regulator is sinking current to keep voltage on VCC pin constant.
7. Test Conditions: VLDO_IN = 1.5V and VLDO_OUT = 1.2V
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
6
Typical Performance Characteristics
Figure 3. Dead Time Waveform
Figure 6. PWM Load Transient (0 to 15A)
Figure 7. LDO Load Transient (0 to 2A)
Figure 8. LDO Load Transient (0 to 5A)
Figure 4. PWM Load Transient (0 to 5A)
Figure 5. PWM Load Transient (0 to 10A)
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
Figure 9. PWM/LDO Power Up
Figure 12. Enable ON (IPWM = 5A)
Figure 10. PWM/LDO Power Down
Figure 13. Enable OFF (IPWM = 5A)
Figure 11. Auto Restart
© 2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5069 Rev. 1.1.5
8
Typical Performance Characteristics (Continued)
PWM Line Regulation (V
OUT
= 1.5V)
LDO Load Regulation (V
= 1.203V)
OUT
1.210
1.205
1.200
1.195
1.190
1.54
1.52
1.50
1.48
1.46
I
I
I
= 0A
= 5A
= 10A
L
L
L
V
V
V
V
= 8V
IN
IN
IN
IN
= 12V
= 15V
= 20V
0
1
2
3
5
4
6
8
10
12
14
16
18
20
LOAD CURRENT (A)
INPUT VOLTAGE (V)
Figure 14. PWM Line Regulation
Figure 17. LDO Load Regulation
Load Line Regulation (V
= 1.203V)
Master Clock Frequency
OUT
700
600
500
400
300
200
100
1.210
1.205
1.200
1.195
1.190
I
I
I
= 0A
= 2A
= 5A
L
L
L
8
10
12
14
16
18
20
0
100
200
(kΩ)
300
400
R
T
INPUT VOLTAGE (V)
Figure 15. LDO Line Regulation
Figure 18. R vs. Frequency
T
PWM Load Regulation (V
OUT
= 1.50V)
Efficiency vs. Input Voltage
1.510
1.505
1.500
1.495
1.490
100
80
60
40
20
0
V
V
V
V
= 8V
IN
IN
IN
IN
= 12V
= 15V
= 20V
V
V
V
V
= 8V
IN
IN
IN
IN
= 12V
= 15V
= 20V
0
2
4
6
8
10
0
2
4
6
8
10
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 16. PWM Load Regulation
Figure 19. 1.5V PWM Efficiency
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
9
Block Diagram
CBOOT
Internal Vcc 5.6V Max.
BOOT
Vcc
Internal
Boot Diode
Shunt Reg
10μA
RILIM
ILIM
Current Limit
Comparator
VIN
PWM
COMP
FB
Error
Amplifier
PWM
Comparator
R Q
HDRV
S
Adaptive
Gate Drive
Circuit
Vref
Vcc
LO
Vout
CO
10μA
OSC
SW
SS
Current
Sense
Amplifier
LDRV
VIN
Summing
Σ
RRAMP
Ramp
Generator
R(RAMP)
EN
PGND
Amplifier
Enable
Figure 20. Block Diagram
Choose a resistor such that:
■ It is rated to handle the power dissipation.
Detailed Operation Description
FAN5069 combines a high-efficiency, fixed-frequency
PWM controller designed for single-phase synchronous
buck Point-Of-Load converters with an integrated LDO
controller to support GTL-type loads. This controller is
ideally suited to deliver low-voltage, high-current power
supplies needed in desktop computers, notebooks,
workstations, and servers. The controller comes with an
integrated boot diode which helps reduce component
cost and increase space savings. With this controller, the
input to the power supply can be varied from 3V to 24V
and the output voltage can be set to regulate at 0.8V to
15V on the switcher output. The LDO output can be con-
figured to regulate between 0.8V to 3V and the input to
the LDO can be from 1.5V to 5V, respectively. An internal
shunt regulator at the VCC pin facilitates the controller
operation from either a 5V or 12V power source.
■ Current sunk within the controller is minimized to
prevent IC temperature rise.
R
Selection (IC)
VCC
The selection of RVCC is dependent on:
■ Variation of the 12V supply
■ Gate charge of the top and bottom FETs (QFET
)
■ Switching frequency (FSW
)
■ Shunt regulator minimum current (1mA)
■ Quiescent current of the IC (IQ)
Calculate RVCC based on the minimum input voltage for
the VCC
:
VinMIN – 5.6
(EQ. 1)
RVCC = -----------------------------------------------------------------------------------------
(IQ + 1 • 10–3 + QFET • FSW • 1.2)
V
Bias Supply
CC
FAN5069 can be configured to operate from 5V or 12V
for VCC. When 5V supply is used for VCC, no resistor is
required to be connected between the supply and the
VCC. When the 12V supply is used, a resistor RVCC is
connected between the 12V supply and the VCC, as
shown in Figure 1. The internal shunt regulator at the
VCC pin is capable of sinking 150mA of current to
ensure that the controller’s internal VCC is maintained at
5.6V maximum.
For a typical example, where: VinMIN = 11.5V, IQ = 3mA,
QFET = 30nC, FSW = 300KHz, RVCC is calculated to be
398.65Ω.
PWM Section
The FAN5069’s PWM controller combines the conven-
tional voltage mode control and current sensing through
lower MOSFET RDS_ON to generate the PWM signals.
This method of current sensing is loss-less and cost
effective. For more accurate current sense requirements,
an optional external resistor can be connected with the
bottom MOSFET in series.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
10
age varies. The RRAMP also has an effect on the current
limit, as can be seen in the RLIM equation (EQ. 5). The
RRAMP value can be approximated using the following
equation:
PWM Operation
Refer to Figure 20 for the PWM control mechanism. The
FAN5069 uses the summing mode method of control to
generate the PWM pulses. The amplified output of the
current-sense amplifier is summed with an internally
generated ramp and the combined signal is amplified
and compared with the output of the error amplifier to get
the pulse width to drive the high-side MOSFET. The
sensed current from the previous cycle is used to modu-
late the output of the summing block. The output of the
summing block is also compared against the voltage
threshold set by the RLIM resistor to limit the inductor cur-
rent on a cycle-by-cycle basis. The controller facilitates
external compensation for enhanced flexibility.
V
IN – 1.8
RRAMP = --------------------------------------------- KΩ
6.3 • 10–8 • Fosc
(EQ. 4)
where FOSC is in Hz. For example, for FOSC = 300kHz
and VIN = 12V, RRAMP
540KΩ.
≈
Gate Drive Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals
and provides necessary amplification, level shifting, and
shoot-through protection. It also has functions that help
optimize the IC performance over a wide range of oper-
ating conditions. Since the MOSFET switching time can
vary dramatically from device to device and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than approxi-
mately 1V. Similarly, the upper MOSFET is not turned on
until the gate-to-source voltage of the lower MOSFET
has decreased to less than approximately 1V. This
allows a wide variety of upper and lower MOSFETs to be
used without a concern for simultaneous conduction, or
shoot-through.
Initialization
When the PWM is disabled, the SW node is connected
to GND through an internal 500Ω MOSFET to slowly dis-
charge the output. As long as the PWM controller is
enabled, this internal MOSFET remains OFF.
Soft-Start (PWM and LDO)
When VCC exceeds the UVLO threshold and EN is high,
the circuit releases SS and enables the PWM regulator.
The capacitor connected to the SS pin and GND is
charged by a 10µA internal current source, causing the
voltage on the capacitor to rise. When this voltage
exceeds 1.2V, all protection circuits are enabled. When
this voltage exceeds 2.2V, the LDO output is enabled.
The input to the error amplifier at the non-inverting pin is
clamped by the voltage on the SS pin until it crosses the
reference voltage.
A low impedance path between the driver pin and the
MOSFET gate is recommended for the adaptive dead-
time circuit to work properly. Any delay along this path
reduces the delay generated by the adaptive dead-time
circuit, thereby increasing the chances for shoot-through.
The time it takes the PWM output to reach regulation
(TRise) is calculated using the following equation:
TRISE = 8 × 10–2 × CSS (CSS is in μf)
(EQ. 2)
Oscillator Clock Frequency (PWM)
Protection
The clock frequency on the oscillator is set using an
external resistor, connected between R(T) pin and
ground. The frequency follows the graph, as shown in
Figure 18. The minimum clock frequency is 200KHz,
which is when R(T) pin is left open. Select the value of
R(T) as shown in the equation below. This equation is
valid for all FOSC > 200kHz.
In the FAN5069, the converter is protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions. All of these conditions generate an
internal “fault latch” which shuts down the converter. For
all fault conditions both the high-side and the low-side
drives are off except in the case of OVP where the low-
side MOSFET is turned on until the voltage on the FB pin
goes below 0.4V. The fault latch can be reset either by
toggling the EN pin or recycling VCC to the chip.
5 × 109
R(T) = --------------------------------------------------Ω
(FOSC – 200 × 103)
(EQ. 3)
Over Current Limit (PWM)
where FOSC is in Hz.
The PWM converter is protected against overloading
through a cycle-by-cycle current limit set by selecting
RILIM resistor. An internal 10µA current source sets the
threshold voltage for the output of the summing amplifier.
When the summing amplifier output exceeds this thresh-
old level, the current limit comparator trips and the PWM
starts skipping pulses. If the current limit tripping occurs
for 16 continuous clock cycles, a fault latch is set and the
controller shuts down the converter. This shutdown fea-
For example, for FOSC = 300kHz, R(T) = 50KΩ.
R
Selection and Feed-Forward Operation
RAMP
The FAN5069 provides for input voltage feed-forward
compensation through RRAMP. The value of RRAMP effec-
tively changes the slope of the internal ramp, minimizing
the variation of the PWM modulator gain when input volt-
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
11
ture is disabled during the start-up until the voltage on
the SS capacitor crosses 1.2V.
EN Pin
Pull to GND
VCC
PWM/Restart
OFF
To achieve current limit, the FAN5069 monitors the
inductor current during the OFF time by monitoring and
holding the voltage across the lower MOSFET. The volt-
age across the lower MOSFET is sensed between the
PGND and the SW pins.
No restart after fault
Cap to GND
Restart after TDELAY (Sec.) =
0.85 x C where C is in μF
The fault latch can also be reset by recycling the VCC to
the controller.
The output of the summing amplifier is a function of the
inductor current, RDS_ON of the bottom FET and the gain
of the current sense amplifier. With the RDS_ON method
of current sensing, the current limit can vary widely from
unit to unit. RDS_ON not only varies from unit to unit, but
also has a typical junction temperature coefficient of
about 0.4%/°C (consult the MOSFET datasheet for
actual values). The set point of the actual current limit
decreases in proportion to increase in MOSFET die tem-
perature. A factor of 1.6 in the current limit set point typi-
cally compensates for all MOSFET RDS_ON variations,
assuming the MOSFET's heat sinking keeps its operat-
ing die temperature below 125°C.
Under Voltage Protection (PWM)
The PWM converter output is monitored constantly for
under voltage at the FB pin. If the voltage on the FB pin
stays lower than 75% of internal Vref for 16 clock cycles,
the fault latch is set and the converter shuts down. This
shutdown feature is disabled during startup until the volt-
age on the SS capacitor reaches 1.2V.
Over Voltage Protection (PWM)
The PWM converter output voltage is monitored con-
stantly at the FB pin for over voltage. If the voltage on the
FB pin stays higher than 115% of internal VREF for two
clock cycles, the controller turns OFF the upper MOS-
FET and turns ON the lower MOSFET. This crowbar
action stops when the voltage on the FB pin reaches
0.4V to prevent the output voltage from becoming nega-
tive. This over-voltage protection (OVP) feature is active
as soon as the voltage on the EN pin becomes high.
For more accurate current limit setting, use resistor
sensing. In a resistor sensing scheme, an appropriate
current sense resistor is connected between the source
terminal of the bottom MOSFET and PGND.
Set the current limit by choosing RILIM as follows:
K1 • IMAX • RDSON • 103
Vout • 33.32 • 1011
---------------------------------------------------
FSW • RRAMP
⎛
⎜
⎝
⎛
⎜
⎝
1.8
1 – --------
Vin
⎛
⎝
⎞
RILIM
=
128 + -----------------------------------------------------------------
•
+
⎠
Turning ON the low-side MOSFETs on an OVP condition
pulls down the output, resulting in a reverse current,
which starts to build up in the inductor. If the output over-
voltage is due to failure of the high-side MOSFET, this
crowbar action pulls down the input supply or blows its
fuse, protecting the system, which is very critical.
1.43
(EQ. 5)
where RILIM is in KΩ.
IMAX is the maximum load current.
K1 is a constant to accommodate for the variation of
MOSFET RDS(ON) (typically 1.6).
During soft-start, if the output overshoots beyond 115%
of VREF, the output voltage is brought down by the low-
side MOSFET until the voltage on the FB pin goes below
0.4V. The fault latch is NOT set until the voltage on the
SS pin reaches 1.2V. Once the fault latch is set, the con-
verter shuts down.
With K1 = 1.6, IMAX = 20A, RDS(ON) = 7mΩ, VIN = 24V,
VOUT = 1.5V, FSW = 300 KHz, RRAMP = 400 KΩ, RILIM
calculates to be 323.17KΩ.
ILIM
Auto Restart (PWM)
115% Vref
UV
Fault
Latch
S
R
OV
The FAN5069 supports two modes of response when the
internal fault latch is set. The user can configure it to
keep the power supply latched in the OFF state OR in
Q
VSS>1.2V
Delay
2 Clks
EN
FB
S
Q
the Auto Restart mode. When the EN pin is tied to VCC
,
LS Drive
R
0.4V
the power supply is latched OFF. When the EN pin is ter-
minated with a 100nF to GND, the power supply is in
Auto Restart mode. The table below describes the rela-
tionship between PWM restart and setting on EN pin. Do
not leave the EN pin open without any capacitor.
Figure 21. Over-Voltage Protection
Thermal Fault Protection
The FAN5069 features thermal protection where the IC
temperature is monitored. When the IC junction temper-
ature exceeds +160°C, the controller shuts down and
when the junction temperature gets down to +125°C, the
converter restarts.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
12
operate at the boundary of continuous and discontinuous
conduction modes.
LDO Section
The LDO controller is designed to provide ultra low volt-
ages, as low as 0.8V for GTL-type loads. The regulating
loop employs a very fast response feedback loop and
small capacitors can be used to keep track of the chang-
ing output voltage during transients. For stable opera-
tion, the minimum capacitance on the output needs to be
100µF and the typical ESR needs to be around 100mΩ.
Setting the Output Voltage (PWM)
The internal reference for the PWM controller is at 0.8V.
The output voltage of the PWM regulator can be set in
the range of 0.8V to 90% of its power input by an exter-
nal resistor divider. The output is divided down by an
external voltage divider to the FB pin (for example, R1
and RBIAS as in Figure 24). The output voltage is given
by the following equation:
The maximum voltage at the gate drive for the MOSFET
can reach close to 0.5V below the VCC of the controller.
For example, for a 1.2V output, the minimum enhance-
ment voltage required with 4.75V on VCC is 3.05V
(4.75V-0.5V-1.2V = 3.05V). The drop-out voltage for the
LDO is dependent on the load current and the MOSFET
chosen. It is recommended to use low enhancement
voltage MOSFETs for the LDO. In applications where
LDO is not needed, pull up the FBLDO pin (Pin #1)
higher than 1V to disable the LDO.
(EQ. 6)
R1
RBIAS
⎛
⎞
⎠
VOUT = 0.8V × 1 + ---------------
⎝
To minimize noise pickup on this node, keep the resistor
to GND (RBIAS) below 10KΩ.
Inductor Selection (PWM)
When the ripple current, switching frequency of the con-
verter, and the input-output voltages are established,
select the inductor using the following equation:
The soft-start on the LDO output (ramp) is controlled by
the capacitor on the SS pin to GND. The LDO output is
enabled only when the voltage on the SS pin reaches
2.2V. Refer to Figure 9 for start-up waveform.
2
VOUT
⎛
⎝
⎞
⎠
V
OUT – --------------
VIN
LMIN = -------------------------------------------
IRipple × FSW
Design Section
(EQ. 7)
General Design Guidelines
where IRipple is the ripple current.
Establishing the input voltage range and maximum cur-
rent loading on the converter before choosing the switch-
ing frequency and the inductor ripple current is highly
recommended. There are design trade-offs in choosing
an optimum switching frequency and the ripple current.
This number typically varies between 20% to 50% of the
maximum steady-state load on the converter.
When selecting an inductor from the vendors, select the
inductance value which is close to the value calculated at
the rated current (including half the ripple current).
The input voltage range should accommodate the worst-
case input voltage with which the converter may ever
operate. This voltage needs to account for the cable drop
encountered from the source to the converter. Typically,
the converter efficiency tends to be higher at lower input
voltage conditions.
Input Capacitor Selection (PWM)
The input capacitors must have an adequate RMS cur-
rent rating to withstand the temperature rise caused by
the internal power dissipation. The combined RMS cur-
rent rating for the input capacitor should be greater than
the value calculated using the following equation:
When selecting maximum loading conditions, consider
the transient and steady-state (continuous) loading sep-
arately. The transient loading affects the selection of the
inductor and the output capacitors. Steady state loading
affects the selection of MOSFETs, input capacitors, and
other critical heat-generating components.
2
VOUT VOUT
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎞
⎠
IINPUT(RMS) = ILOAD(MAX)
×
-------------- – --------------
(EQ. 8)
⎝
VIN
VIN
Common capacitor types used for such application
include aluminum, ceramic, POS CAP, and OSCON.
The selection of switching frequency is challenging.
While higher switching frequency results in smaller com-
ponents, it also results in lower efficiency. Ideal selection
of switching frequency takes into account the maximum
operating voltage. The MOSFET switching losses are
directly proportional to FSW and the square function of
the input voltage.
Output Capacitor Selection (PWM)
The output capacitors chosen must have low enough
ESR to meet the output ripple and load transient require-
ments. The ESR of the output capacitor should be lower
than both of the values calculated below to satisfy both
the transient loading and steady-state ripple conditions
as given by the following equation:
When selecting the inductor, consider the minimum and
maximum load conditions. Lower inductor values pro-
duce better transient response, but result in higher ripple
and lower efficiency due to high RMS currents. Optimum
minimum inductance value enables the converter to
VSTEP
ESR ≤ ---------------------------------- and ESR ≤ ------------------
ΔILOAD(MAX) IRipple
VRipple
(EQ. 9)
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
13
In the case of aluminum and polymer based capacitors,
the output capacitance is typically higher than normally
required to meet these requirements. While selecting the
ceramic capacitors for the output; although lower ESR
can be achieved easily, higher capacitance values are
required to meet the VOUT(MIN) restrictions during a load
transient. From the stability point of view, the zero
caused by the ESR of the output capacitor plays an
important role in the stability of the converter.
VIN
5V
CGD
RGATE
RD
HDRV
SW
G
CGS
Output Capacitor Selection (LDO)
Figure 23. Drive Equivalent Circuit
For stable operation, the minimum capacitance of 100µF
with ESR around 100mΩ is recommended. For other val-
ues, contact the factory.
The upper graph in Figure 22 represents Drain-to-
Source Voltage (VDS) and Drain Current (ID) waveforms.
The lower graph details Gate-to-Source Voltage (VGS
)
Power MOSFET Selection (PWM)
vs. time with a constant current charging the gate. The x-
axis is representative of Gate Charge (QG). CISS = CGD
+ CGS and it controls t1, t2, and t4 timing. CGD receives
the current from the gate driver during t3 (as VDS is fall-
ing). Obtain the gate charge (QG) parameters shown on
the lower graph from the MOSFET datasheets.
The FAN5069 is capable of driving N-Channel MOSFETs
as circuit switch elements. For better performance,
MOSFET selection must address these key parameters:
■ The maximum Drain-to-Source Voltage (VDS) should
be at least 25% higher than worst-case input voltage.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1's switching losses
occur during the shaded time when the MOSFET has
voltage across it and current through it.
■ The MOSFETs should have low QG, QGD, and QGS.
■
The R
of the MOSFETs should be as low as possible.
DS_ON
In typical applications for a buck converter, the duty
cycles are lower than 20%. To optimize the selection of
MOSFETs for both the high-side and low-side, follow dif-
ferent selection criteria. Select the high-side MOSFET to
minimize the switching losses and the low-side MOSFET
to minimize the conduction losses due to the channel
and the body diode losses. Note that the gate drive
losses also affect the temperature rise on the controller.
Losses are given by (EQ. 10), (EQ. 11), and (EQ. 12):
PUPPER = PSW + PCOND
(EQ. 10)
(EQ. 11)
VDS × IL
⎛
⎞
PSW
=
--------------------- × 2 × ts FSW
⎝
⎠
2
VOUT
(EQ. 12)
⎛
⎝
⎞
PCOND
=
-------------- × IO2 UT × RDS(ON)
⎠
For loss calculation, refer to Fairchild's Application Note
AN-6005 and the associated spreadsheet.
VIN
where PUPPER is the upper MOSFET's total losses and
PSW and PCOND are the switching and conduction losses
for a given MOSFET. RDS(ON) is at the maximum junction
temperature (TJ) and tS is the switching period (rise or
fall time) and equals t2+t3 (Figure 22.).
High-Side Losses
Losses in the MOSFET can be understood by following
the switching interval of the MOSFET in Figure 22. MOS-
FET gate drive equivalent circuit is shown in Figure 23.
The driver's impedance and CISS determine t2 while t3's
CISS
CGD
CISS
period is controlled by the driver's impedance and QGD
.
VDS
Since most of tS occurs when VGS = VSP, assume a con-
stant current for the driver to simplify the calculation of tS
using the following equation:
QG(SW)
IDriver
Q
ts = ------------------- ≈ ------------------G----(--S----W-----)-------------
(EQ. 13)
VCC – VSP
----------------------------------------
Driver + RGate
⎛
⎝
⎞
⎠
ID
R
Most MOSFET vendors specify QGD and QGS. QG(SW)
can be determined as:
QGS
QGD
QG(SW) = QGD + QGS – QTH where QTH is the gate
charge required to reach the MOSFET threshold (VTH).
4.5V
VSP
VTH
Note that for the high-side MOSFET, VDS equals VIN,
which can be as high as 20V in a typical portable appli-
cation. Include the power delivered to the MOSFET's
(PGATE) in calculating the power dissipation required for
the FAN5069.
QG(SW)
VGS
t1
t2
t3
t4
t5
Figure 22. Switching Losses and QG
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
14
PGATE is determined by the following equation:
R-C components for the snubber are selected as follows:
(EQ. 14)
PGate = QG × VCC × FSW
a) Measure the SW node ringing frequency (Fring) with a
low capacitance scope probe.
where QG is the total gate charge to reach VCC
.
b) Connect a capacitor (CSNUB) from SW node to GND
so that it reduces this ringing by half.
Low-Side Losses
Q2 switches on or off with its parallel schottky diode
simultaneously conducting, so the VDS ≈ 0.5V. Since
PSW is proportional to VDS, Q2's switching losses are
negligible and Q2 is selected based on RDS(ON) alone.
c) Place a resistor (RSNUB) in series with this capacitor.
RSNUB is calculated using the following equation:
2
RSNUB = ----------------------------------------------
(EQ. 17)
π × Fring × CSNUB
Conduction losses for Q2 are given by the equation:
PCOND = (1 – D) × IO2 UT × RDS(ON)
(EQ. 15)
d) Calculate the power dissipated in the snubber resistor
as shown in the following equation:
where RDS(ON) is the RDS(ON) of the MOSFET at the
highest operating junction temperature and D=VOUT/VIN
is the minimum duty cycle for the converter.
PR(SNUB) = CSNUB × V2IN(MAX) × FSW
(EQ. 18)
where, VIN(MAX) is the maximum input voltage and FSW
is the converter switching frequency.
Since DMIN < 20% for portable computers, (1-D) ≈ 1 pro-
duces a conservative result, simplifying the calculation.
The snubber resistor chosen should be de-rated to han-
The maximum power dissipation (PD(MAX)) is a function
of the maximum allowable die temperature of the low-
side MOSFET, the θJA, and the maximum allowable
ambient temperature rise. PD(MAX) is calculated using
the following equation:
dle the worst-case power dissipation. Do not use wire-
wound resistors for RSNUB
.
Loop Compensation
Typically, the closed loop crossover frequency (Fcross),
where the overall gain is unity, should be selected to
achieve optimal transient and steady-state response to
disturbances in line and load conditions. It is recom-
mended to keep Fcross below fifth of the switching fre-
quency of the converter. Higher phase margin tends to
have a more stable system with more sluggish response
to load transients. Optimum phase margin is about 60°, a
good compromise between steady state and transient
responses. A typical design should address variations
over a wide range of load conditions and over a large
sample of devices.
T
J(MAX) – TA(MAX)
PD(MAX) = ------------------------------------------------
θJA
(EQ. 16)
θJA depends primarily on the amount of PCB area
devoted to heat sinking.
Selection of MOSFET Snubber Circuit
The Switch node (SW) ringing is caused by fast switch-
ing transitions due to the energy stored in the parasitic
elements. This ringing on the SW node couples to other
circuits around the converter if they are not handled
properly. To dampen this ringing, an R-C snubber is con-
nected across the SW node and the source of the low-
side MOSFET.
VIN
Current
Sense
Amplifier
Q1
VIN
RRAMP
Ramp
Generator
L
RDC
VOUT
PWM
Summing
&
C
Σ
DRIVER
RL
Q2
Amplifier
RES
C2
C1
R2
C3
R3
RBIAS
R1
Reference
Figure 24. Closed-Loop System with Type-3 Network
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
15
FAN5069 has a high gain error amplifier around which
the loop is closed. Figure 24 shows a Type-3 compensa-
tion network. For Type-2 compensation, R3 and C3 are
not used. Since the FAN5069 architecture employs sum-
ming current mode, Type-2 compensation can be used
for most applications.
For further information about Type-2 compensation
networks, refer to:
■ Venable, H. Dean, "The K factor: A new mathematical
tool for stability analysis and synthesis,” Proceedings
of Powercon, March 1983.
Note: For critical applications requiring wide loop
bandwidth using very low ESR output capacitors,
use Type-3 compensation.
Type 3 Feedback Component Calculations
Use the following steps to calculate feedback components:
Notation:
C0 = Net Output Filter capacitance
Gp(s) = Net Gain of Plant = control-to-output transfer function
L = Inductor Value
RDSON = ON-state Drain-to Source Resistance of Low-side MOSFET
Res = Net ESR of the Output Filter Capacitors
RL = Load Resistance
Ts = Switching Period
VIN = Input Voltage
FSW = Switching Frequency
Equations:
Effective current sense resistance = Ri = 7 × RDSON
(EQ. 19)
(EQ. 20)
RL
Current modulator DC gain = Mi = ------
Ri
(VIN – 1.8) × Ts
Vm = 3.33 × 1010 × ----------------------------------------
Effective ramp amplitude =
Rramp
(EQ. 21)
(EQ. 22)
VIN
Voltage modulator DC gain = Mv = --------
Vm
Mv × Mi
||
Plant DC gain = Mo = Mv Mi = -------------------
(EQ. 23)
(EQ. 24)
(EQ. 25)
(EQ. 26)
(EQ. 27)
Mv + Mi
π
Sampling gain natural frequency = ωn = -----
Ts
–2
Qz = -----
π
Sampling gain quality factor (damping) =
MO
Mv × Ri
⎛
⎞
⎠
Effective inductance = Le = -------- × L + -------------------
⎝
Mv
ωn × Qz
Mv × Ri × RL
||
Rp = -------------------------------- = (Mv × Ri) RL
Mv × Ri + RL
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
16
Poles and Zeros of Plant Transfer Function:
1
Plant zero frequency = fz = -----------------------------------------
2 × π × Co × Res
(EQ. 28)
(EQ. 29)
1
Plant 1st pole frequency = fp1 = ----------------------------------------------------------
Le
⎛
⎞
2 × π × Co × Rp + ------
⎝
⎠
RL
Rp
1
2 × π
1
Plant 2nd pole frequency = fp2 = ------------ × -------------------- + ------
(EQ. 30)
(EQ. 31)
⎛
⎞
⎠
⎝
Co × RL Le
ω2n × Le
Plant 3rd pole frequency = fp3 = -------------------------
2 × π × Rp
Plant gain (magnitude) response:
2
f
⎛ ⎞
1 + ---
⎝ ⎠
fz
Gp (f) = 20 × logM0 + 10 × log ---------------------------------------------------------------------------------------------------------
(EQ. 32)
(EQ. 33)
2
2
2
f
f
f
⎛
⎛
⎞
⎠
⎛
⎞
⎠
⎞
⎠
1 + ------
× 1 + ------
× 1 + ------
⎝
⎝
⎝
fp3
fp1
fp2
Plant phase response:
–1
f
–1
f
–1
f
⎛
–1⎛ f ⎞
⎛
⎞
⎛
⎞
⎞
⎠
∠GP(f) = tan --- – tan ------ – tan ------ – –tan ------
⎝ ⎠
fz
⎝
⎠
⎝
⎠
⎝
fp3
fp1
fp2
Choose R1, RBIAS to set the output voltage using EQ.6. Choose the zero crossover frequency Fcross of the overall
loop. Typically Fcross should be less than fifth of Fsw. Choose the desired phase margin; typically between 60° to 90°.
Calculate plant gain at Fcross using EQ.34 by substituting Fcross in place of f. The gain that the amplifier needs to pro-
vide to get the required crossover is given by:
1
GAMP = -------------------------------
(EQ. 34)
(EQ. 35)
Gp (Fcross
)
The phase boost required is calculated as given in (EQ. 35)
Phase Boost = M – ∠GP(Fcross ) – 90°
where M is the desired phase margin in degrees.
The feedback component values are calculated as given in equations below:
2
⎧
⎫
⎬
⎭
Boost
⎛
⎞
K = Tan ---------------- + 45
⎨
⎝
⎠
4
⎩
(EQ. 36)
1
C2 = -----------------------------------------------------------------------
2 × π × Fcross × GAMP × R1
(EQ. 37)
(EQ. 38)
(EQ. 39)
C1 = C2 × (K – 1)
1
C3 = ---------------------------------------------------------------
2 × π × Fcross
× K × R3
K
R2 = -------------------------------------------------
2 × π × Fcross × C1
(EQ. 40)
(EQ. 41)
R1
R3 = -----------------
(K – 1)
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
17
Design Tools
Layout Considerations
Fairchild application note AN-6010 provides a PSPICE
model and spreadsheet calculator for the PWM regula-
tor, simplifying external component selections and verify-
ing loop stability. The topics covered provide an
understanding of the calculations in the spreadsheet.
The switching power converter layout needs careful
attention and is critical to achieving low losses and clean
and stable operation. Below are specific recommenda-
tions for good board layout:
■ Keep the high-current traces and load connections as
The spreadsheet calculator, which is part of AN-6010,
can be used to calculate all external component values
for designing around FAN5069. The spreadsheet pro-
vides optimized compensation components and gener-
ates a Bode Plot to ensure loop stability.
short as possible.
■ Use thick copper boards whenever possible to
achieve higher efficiency.
■ Keep the loop area between the SW node, low-side
MOSFET, inductor, and the output capacitor as small
as possible.
Based on the input values entered, AN-6010’s PSPICE
model can be used to simulate Bode Plots (for loop sta-
bility) as well as transient analysis to help customize the
design for a wide range of applications.
■ Route high dV/dt signals, such as SW node, away
from the error amplifier input/output pins. Keep com-
ponents connected to these pins close to the pins.
■ Place ceramic de-coupling capacitors very close to the
Use Fairchild Application Note AN-6005 for prediction of
the losses and die temperatures for the power semicon-
ductors used in the circuit.
VCC pin.
■ All input signals are referenced with respect to AGND
pin. Dedicate one layer of the PCB for a GND plane.
Use at least four layers for the PCB.
AN-6010 and AN-6005 can be downloaded from
www.fairchildsemi.com/apnotes/.
■ Minimize GND loops in the layout to avoid EMI-related
issues.
■ Use wide traces for the lower gate drive to keep the
drive impedances low.
■ Connect PGND directly to the lower MOSFET source
pin.
■ Use wide land areas with appropriate thermal vias to
effectively remove heat from the MOSFETs.
■ Use snubber circuits to minimize high-frequency ring-
ing at the SW nodes.
■ Place the output capacitor for the LDO close to the
source of the LDO MOSFET.
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
18
Application Board Schematic
VIN = 3 to 24V; VOUT =1.5V at 20A.
+5V or +12V
Vcc
J1
R9
220
U1
PWM OUT
C7
3-24V
0.22µF
J2
VIN
R6 453K
15
16
1
14
10
11
9
VCC
GLDO
FBLDO
R(T)
R(RAMP)
HDRV
BOOT
SW
C10
+
C11
+
C6
FDD6296
Q1
FDD6530A
Q2
820µF
820µF
0.1µF
J3
GND
LDO
J7
LDO_Out
R8
5K
PWM OUT
C17
C8
0.22µF
+
C4
R7 10K
0.1µF
L1
1.8µH
J4
R4
2
560µF
J6
GND
SW_Out
50K
FDD6606 FDD6606
Q3
R11
2.2
C12
C13
C14
+ +
C15
+
Q4
R5
243K
C5
3
13
12
5
IL IM
SS
LDRV
PGND
COMP
FB
560µF 560µF 560µF
0.1µF
TP1
C16
3.3nF
J5
GND
4
0.1µF
C1
1500pF
C3
R2
R3
825
R1
5.11K
TP2
7
EN
12.7k
3300pF
C9
0.01µF
C2
220pF
8
6
AGND
R10
FAN5069
5.83K
Figure 25. Application Board Schematic
Bill of Materials
Part Description
Capacitor, 1500pF, 20%, 25V, 0603,X7R
Capacitor, 220pF, 5%, 50V, 0603,NPO
Capacitor, 3300pF, 10%, 50V, 0603,X7R
Capacitor, 0.1µF, 10%, 25V, 0603,X7R
Capacitor, 0.22µF, 20%, 25V, 0603,X7R
Capacitor, 0.01µF, 10%, 50V, 0603,X7R
Quantity
Designator
Vendor
Vendor Part #
1
C1
Panasonic
PCC1774CT-ND
PCC221ACVCT-ND
PCC1778CT-ND
PCC2277CT-ND
PCC1767CT-ND
PCC1784CT-ND
KZH25VB820MHJ20
PSC2.5VB820MH08
PSA4VB560MH11
PCC332BNCT-ND
WM6436-ND
1
1
4
2
1
2
1
3
1
1
6
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
3
1
C2
Panasonic
C3
Panasonic
C4, C5, C6, C15
Panasonic
C7, C8
Panasonic
C9
Panasonic
Capacitor, 820µF, 20%, 10X20, 25V,20mOhm,1.96A
Capacitor, 820µF, 20%, 8X8, 2.5V,7mOhm,6.1A
Capacitor, 560µF, 20%, 8X11.5, 4V,7mOhm,5.58A
Capacitor, 3300pF, 10%, 50V, 0603,X7R
Connector Header 0.100 Vertical, Tin - 2 Pin
Terminal Quickfit Male .052"Dia.187" Tab
Inductor, 1.8µH, 20%, 26Amps Max, 3.24mOhm
MOSFET N-CH, 32 mΩ, 20V, 21A, D-PAK, FSID: FDD6530A
MOSFET N-CH, 8.8 mΩ, 30V, 50A, D-PAK, FSID: FDD6296
MOSFET N-CH, 6 mΩ, 30V, 75A, D-PAK, FSID: FDD6606
Resistor, 5.11K, 1%, 1/16W
C10, C11
Nippon-Chemicon
Nippon-Chemicon
Nippon-Chemicon
Panasonic
C17
C12, C13, C14
C16
J1
Molex
J2 - J7
Keystone
1212K-ND
L1
Inter-Technical
Fairchild Semiconductor
Fairchild Semiconductor
Fairchild Semiconductor
Panasonic
SC5018-1R8M
FDD6530A
Q1
Q2
FDD6296
Q3, Q4
FDD6606
R1
P5.11KHCT-ND
P12.7KHCT-ND
P825HCT-ND
Resistor, 12.7K, 1%, 1/16W
R2
Panasonic
Resistor, 825Ω, 1%, 1/16W
R3
Panasonic
Resistor, 49.9K, 1%, 1/16W
R4
Panasonic
P49.9KHCT-ND
P243KHCT-ND
P453KHCT-ND
P10.0KHCT-ND
P4.99KHCT-ND
P200FCT-ND
Resistor, 243K, 1%, 1/16W
R5
Panasonic
Resistor,453K, 1%, 1/16W
R6
Panasonic
Resistor,10K, 1%, 1/16W
R7
Panasonic
Resistor, 4.99K, 1%, 1/16W
R8
Panasonic
Resistor, 220Ω, 1%, 1/4W
R9
Panasonic
Resistor, 5.90K, 1%, 1/16W
R10
Panasonic
P5.90KHCT-ND
P2.2ECT-ND
Resistor, 2.2Ω, 1%, 1/4W
R11
Panasonic
Connector Header 0.100 Vertical, Tin - 1 Pin
IC, System Regulator, TSSOP16, FSID: FAN5069
TP1,TP2, Vcc
U1
Molex
WM6436-ND
Fairchild Semiconductor
FAIRCHILD
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
19
Typical Application Board Layout
Figure 26. Assembly Diagram
Figure 29. Mid Layer 2
Figure 27. Top Layer
Figure 30. Bottom Layer
Figure 28. Mid Layer 1
© 2005 Fairchild Semiconductor Corporation
FAN5069 Rev. 1.1.5
www.fairchildsemi.com
20
5.10
4.90
A
4.55
16
9
B
4.50
4.30
6.4
5.90
4.45 7.35
1.45
0.65
3.2
1
8
0.2 C B A
PIN #1
IDENT
0.11
5.00
ALL LEAD TIPS
TOP VIEW
LAND PATTERN RECOMMENDATION
1.10 MAX
0.15
0.05
A
0.20
0.09
0.90
ALL LEAD TIPS
0.1 C
0.30
0.19
SIDE VIEW
C
M
S
S
C
0.13
A B
0.65
NOTES:
FRONT VIEW
12°
A. CONFORMS TO JEDEC REGISTRATION
MO-153, VARIATION AB
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF
BURRS, MOLD FLASH, AND TIE BAR
EXTRUSIONS
D. DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 2009
E. LAND PATTERN RECOMMENDATION
PER IPC7351 - ID# TSOP65P640X110-16N
F. DRAWING FILENAME: MKT-MTC16rev5
TOP & BOTTOM
GAGE
PLANE
0.25
8°
0°
0.70
0.50
SEATING PLANE
DETAIL A
SCALE 3:1
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