FAN5234MTCX [ONSEMI]
PWM/PFM 控制器，宽输入电压范围;
| 型号： | FAN5234MTCX |
| 厂家： | 
ONSEMI |
| 描述： | PWM/PFM 控制器，宽输入电压范围 控制器 开关 光电二极管 |
| 文件： | 总14页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PWM/PFM Controller
FAN5234
Description
The FAN5234 PWM controller provides high efficiency and
regulation with an adjustable output from 0.9 V to 5.5 V required to
power I/O, chip−sets, memory banks, or peripherals in
high−performance notebook computers, PDAs, and Internet
appliances. Synchronous rectification and hysteretic operation at light
loads contribute to a high efficiency over a wide range of loads. The
Hysteretic Mode of operation can be disabled if PWM Mode is desired
for all load levels. Efficiency is further enhanced by using the
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TSSOP16
CASE 948AH
MOSFET’s R
as a current−sense component.
DS(ON)
Feed−forward ramp modulation, average current mode control, and
internal feedback compensation provide fast response to load
transients. The FAN5234 monitors these outputs and generates
a PGOOD (power−good) signal when the soft−start is completed and
the output is within 10% of its set point. A built−in over−voltage
protection prevents the output voltage from going above 120% of the
set point. Normal operation is automatically restored when the
over−voltage conditions cease. Under−voltage protection latches the
chip off when the output drops below 75% of its set value after the
soft− start sequence is completed. An adjustable over−current function
monitors the output current by sensing the voltage drop across the
lower MOSFET.
MARKING DIAGRAM
$Y&Z&2&K
5234MTCX
$Y
&Z
&2
&K
= ON Semiconductor Logo
Features
= Assembly Plant Code
= Numeric Date Code
= Lot Code
• Wide Input Voltage Range for Mobile Systems: 2 V to 24 V
• Excellent Dynamic Response with Voltage Feed−Forward and
Average−Current−Mode Control
5234MTCX
= Specific Device Code
• Lossless Current Sensing on Low−Side MOSFET or Precision
Over−Current via Sense Resistor
ORDERING INFORMATION
• V Under−Voltage Lockout
CC
†
Device
FAN5234MTCX
Package
Shipping
2500 /
Tape & Reel
• Power−Good Signal
TSSOP 16
(Pb−Free)
• Light−Load Hysteretic Mode Maximizes Efficiency
• 300 kHz or 600 kHz Operation
• Operating Temperature Range: −10°C to +85°C
• TSSOP16 Package
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• This is a Pb−Free Device
Applications
• Mobile PC Regulator
• Handheld PC Power
Related Resources
• Application Note − AN−6002 Component Calculations and
Simulation Tools for FAN5234 or FAN5236
• Application Note − AN−1029 Maximum Power Enhancement
Techniques for SO−8 Power MOSFET
© Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
June, 2021 − Rev. 3
FAN5234/D
FAN5234
TYPICAL APPLICATION
VIN(BATTERY)
= 2 to 24 V
VIN
C1
C5
C2
1
D1
VCC
ILIM
BOOT
+5
11
4
15
+5
C4
Q1A
HDRV
SW
14
13
R5
C3
L1
1.8 V at 3.5 A
C6
R1
EN
Q1B
3
7
FAN5234
R3
LDRV
SS1
10
PGND
ISNS
+5
9
FPWM
AGND
16
8
R2
12
R4
VSEN
VOUT
6
5
PGOOD
2
Figure 1. 1.18 V Output Regulator
BLOCK DIAGRAM
5 V
C
BOOT
BOOT
V
DD
EN
V
IN
POR/UVLO
Q1
FPWM
FPWM
HYST
HDRV
SW
HYST
SS
+
V
OUT
C
OVP
−
+
ADAPTIVE
L
OUT
Q2
−
GATE
CONTROL
LOGIC
V
DD
OUT
LDRV
PGND
RAMP
OSC
VIN
CLK
Q
R
PWM
S/H
PWM/HYST
S
PWM
RAMP
S
+
R
SENSE
I
I
det.
MODE
ISNS
LIM
−
CURRENT
PROCESSING
VSEN
SS
EA
DUTY
CYCLE
CLAMP
−
OUT
+
I
LIM
V
REF
R
ILIM
Reference and
PGOOD
REF2
PWM/HYST
Soft−Start
Figure 2. Block Diagram
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2
FAN5234
PIN CONFIGURATION
VIN
PGOOD
EN
FPWM
BOOT
HDRV
SW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ILIM
FAN5234
ISNS
VCC
VOUT
VSEN
SS
LDRV
PGND
AGND
Figure 3. Pin Configuration
PIN DEFINITIONS
Pin #
Name
Description
1
VIN
Input Voltage. Connect to main input power source (battery), also used to program operating frequency for
low input voltage operation (see Table 1)
2
3
PGOOD
EN
Power−Good Flag. An open−drain output that pulls LOW when V
is outside of a 10% range of the 0.9 V
SEN
reference
Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator after a latched fault
condition. This is a CMOS input whose state is indeterminate if left open
4
5
ILIM
Current Limit. A resistor from this pin to GND sets the current limit
VOUT
Output Voltage. Connect to output voltage. Used for regulation to ensure a smooth transition during mode
changes. When VOUT is expected to exceed VCC, tie this pin to VCC
6
7
8
9
VSEN
SS
Output Voltage Sense. The feedback from the output. Used for regulation as well as power−good,
under−voltage, and over−voltage protection monitoring
Soft−Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization,
when this pin is charged with a 5 mA current source
AGND
PGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect
to this pin
Power Ground. The return for the low−side MOSFET driver output. Connect to the gate of the low−side
MOSFET
10
11
LDRV
VCC
Low−Side Drive. The low−side (lower) MOSFET driver output. Connect to the gate of the low−side MOSFET
Supply Voltage. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage
on this pin exceeds 4.6 V (UVLO rising) and shuts down when it drops below 4.3 V (UVLO falling)
12
13
ISNS
SW
Current−Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor for
current feedback
Switching Node. Return for the high−side MOSFET driver and a current−sense input. Connect to source of
high−side MOSFET and low−side MOSFET drain
14
15
16
HDRV
BOOT
FPWM
High−Side Drive. High−side (upper) MOSFET driver output. Connect to the gate of the high−side MOSFET
BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 2
Forced PWM Mode. When logic HIGH, inhibits the regulation from entering Hysteretic Mode
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3
FAN5234
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
−
Max.
6.5
27
Unit
V
V
CC
V Supply Voltage
CC
V
IN
V Supply Voltage
IN
−
V
BOOT, SW, ISNS, HDRV Pins
BOOT to SW Pins
−
33
V
−
6.5
V
All Other Pins
−0.3
−10
−65
−
V
CC
+ 0.3
V
T
J
Junction Temperature
+150
+150
+300
°C
°C
°C
T
STG
Storage Temperature
T
L
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
4.75
−
Typ.
5.00
−
Max.
5.25
24
Unit
V
V
CC
V
Supply Voltage
CC
V
IN
V Supply Voltage
IN
V
T
Ambient Temperature
Thermal Resistance, Junction to Ambient
−10
−
−
+85
112
°C
A
qJA
−
°C/W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL SPECIFICATIONS Recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES
I
V
CC
Current
LDRV, HDRV Open;
Forced Above Regulation Point
−
850
1300
mA
VCC
V
SEN
Shutdown (EN−0)
−
10
5
20
15
−
15
30
mA
mA
mA
mA
V
I
V
IN
V
IN
V
IN
Current, Sinking
Current, Sourcing
Current, Shutdown
VIN Pin = Input Voltage Source
VIN Pin = GND
SINK
I
7
20
SOURCE
I
−
1
SD
V
UVLO Threshold
UVLO Hysteresis
Frequency
Rising V
Falling
4.30
4.10
0.1
4.55
4.27
−
4.75
4.50
0.5
UVLO
CC
V
V
kHz
V
UVLOH
OSCILLATOR
f
V
IN
V
IN
V
IN
V
IN
> 5 V
255
510
−
300
600
2
345
690
−
osc
= 0 V
= 16 V
> 5 V
V
PP
Ramp Amplitude
−
1.25
0.5
125
250
−
V
RAMP
Ramp Offset
−
−
V
G
Ramp / V Gain
−
−
mV/V
V
IN
≥ 3 V
IN
1 V < V < 3 V
−
−
IN
REFERENCE AND SOFT−START
V
Internal Reference Voltage
Soft−Start Current
0.891
0.900
5
0.909
V
mA
V
REF
I
At Startup
−
−
−
−
SS
V
Soft−Start Complete Threshold
1.5
SS
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4
FAN5234
ELECTRICAL SPECIFICATIONS Recommended operating conditions, unless otherwise noted. (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PWM CONVERTER
Load Regulation
V Bias Current
SEN
I
from 0 to 3 A, V from 2 to 24 V
−1
50
−
80
55
75
144
−
+1
150
65
%
nA
kW
%
OUT
IN
I
SEN
VOUT Pin Input Impedance
Under−Voltage Shutdown
Over−Current Threshold
Over−Voltage Threshold
40
UVLO
% of Set Point, 2 ms Noise Filter
= 68.5 kW, Figure 6
70
80
TSD
I
R
115
113
172
120
%
SNS
ILIM
UVLO
OUTPUT DRIVERS
HDRV Output Resistance
% of Set Point, 2 ms Noise Filter
mA
Sourcing
Sinking
−
−
−
−
8.0
3.2
8.0
1.5
15.0
4.0
W
W
LDRV Output Resistance
Sourcing
Sinking
15.0
2.4
POWER−GOOD OUTPUT AND CONTROL PINS
Lower Threshold
% of Set Point, 2 ms Noise Filter
% of Set Point, 2 ms Noise Filter
IPGOOD = 4 mA
86
110
−
−
−
92
115
0.5
1
%
%
V
Upper Threshold
PGOOD Output Low
−
Leakage Current
VPULLUP = 5 V
−
−
mA
%
Soft−Start Voltage,
PGOOD Enabled
−
1.5
−
V
REF2
EN, FPWM INPUTS
V
Input High
Input Low
2
−
−
−
V
V
INH
V
−
0.8
INL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
FUNCTIONAL DESCRIPTION
Overview
time. In Hysteretic Mode, a comparator is synchronized to
the main clock to allow seamless transition between the
operational modes and reduced channel−to−channel
interaction.
The Hysteretic Mode of operation can be inhibited
independently using the FPWM pin if variable frequency
operation is not desired.
The FAN5234 is a PWM controller intended for
low−voltage power applications in notebook, desktop, and
sub−notebook PCs. The output voltage of the controller can
be set in the range of 0.9 V to 5.5 V by an external resistor
divider.
The synchronous buck converter can operate from an
unregulated DC source (such as a notebook battery), with
voltage ranging from 2 V to 24 V, or from a regulated system
rail. In either case, the IC is biased from a +5 V source. The
PWM modulator uses an average−current−mode control
with input voltage feed−forward for simplified feedback
loop compensation and improved line regulation. The
controller includes integrated feedback loop compensation
that dramatically reduces the number of external
components.
Oscillator
Table 1. CONVERTER OPERATING MODES
Mode
f
Converter Power
2 to 24 V
VIN Pin
Battery (> 5 V)
100 kW to GND
GND
SW
Battery
300
300
600
Fixed 300
Fixed 600
< 5.5 V Fixed
< 5.5 V Fixed
Depending on the load level, the converter can operate in
fixed−frequency PWM Mode or in Hysteretic Mode.
Switch−over from PWM to Hysteretic Mode improves the
converters’ efficiency at light loads and prolongs battery run
When V is from the battery, the oscillator ramp
IN
amplitude is proportional to V , providing voltage
IN
feed−forward control for improved loop response. When in
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5
FAN5234
either of the fixed modes, oscillator ramp amplitude is fixed.
The operation frequency is determined according to the
connection on the VIN pin (see Table 1)
The boundary value of inductor current, where current
becomes discontinuous, is estimated by the following:
(VIN * VOUT)VOUT
2fSWLOUTVIN
+ ǒ
Ǔ
ILOAD(DIS)
(eq. 2)
Initialization and Soft Start
Assuming EN is HIGH, FAN5234 is initialized when V
CC
Hysteretic Mode
exceeds the rising UVLO threshold. Should V drop below
CC
Conversely, the transition from Hysteretic Mode to PWM
Mode occurs when the SW node is negative for eight
consecutive cycles.
A sudden increase in the output current causes a change
from Hysteretic to PWM Mode. This load increase causes an
instantaneous decrease in the output voltage due to the
voltage drop on the output capacitor ESR. If the load causes
the UVLO threshold, an internal power−on reset function
disables the chip.
The voltage at the positive input of the error amplifier is
limited by the voltage at the SS pin, which is charged with
5 mA current source. Once CSS has charged to V
REF
(0.9 V), the output voltage is in regulation. The time it takes
SS to reach 0.9 V is:
the output voltage (as presented at V ) to drop below the
SEN
0.9 CSS
(eq. 1)
t0.9
+
hysteretic regulation level (20 mV below V ), the mode
REF
5
is changed to PWM on the next clock cycle.
where t is in seconds if C is in mF.
0.9
SS
In Hysteretic Mode, the PWM comparator and the error
amplifier that provide control in PWM Mode are inhibited
and the hysteretic comparator is activated. In Hysteretic
Mode the low−side MOSFET is operated as a synchronous
When SS reaches 1.5 V, the power−good outputs are
enabled and Hysteretic Mode is allowed. The converter is
forced into PWM Mode during soft−start.
rectifier, where the voltage across (V
) is monitored
DS(ON)
Operation Mode Control
and it is switched off when V
goes positive (current
DS(ON)
The mode−control circuit changes the converter’s mode
from PWM to Hysteretic and vice versa based on the voltage
polarity of the SW node when the lower MOSFET is
conducting and just before the upper MOSFET turns on. For
continuous inductor current, the SW node is negative when
the lower MOSFET is conducting and the converters operate
in fixed−frequency PWM Mode, as shown in Figure 4. This
mode achieves high efficiency at nominal load. When the
load current decreases to the point where the inductor
current flows through the lower MOSFET in the “reverse”
direction, the SW node becomes positive and the mode is
changed to Hysteretic, which achieves higher efficiency at
low currents by decreasing the effective switching
frequency.
To prevent accidental mode change or “mode chatter,” the
transition from PWM to Hysteretic Mode occurs when the
SW node is positive for eight consecutive clock cycles (see
Figure 4). The polarity of the SW node is sampled at the end
of the lower MOSFET conduction time. At the transition
between PWM and Hysteretic Mode, both the upper and
lower MOSFETs are turned off. The SW node “rings” based
on the output inductor and the parasitic capacitance on the
SW node and settles out at the value of the output voltage.
flowing back from the load), allowing the diode to block
reverse conduction.
The hysteretic comparator causes HDRV turn−on when
the output voltage (at V ) falls below the lower threshold
SEN
(10 mV below V ) and terminates the PFM signal when
REF
V
SEN
rises over the higher threshold (5 mV above V ).
REF
The switching frequency is primarily a function of:
• Spread between the two hysteretic thresholds
• I
LOAD
• Output inductor and capacitor ESR
A transition back to PWM Continuous Conduction Mode
or (CCM) occurs when the inductor current rises sufficiently
to stay positive for eight consecutive cycles. This occurs
when:
DVHYSTERESIS
+ ǒ
Ǔ
ILOAD(CCM)
(eq. 3)
2 ESR
where DV
= 15 mV and ESR is the equivalent
HYSTERESIS
series resistance of C
.
OUT
VCORE
PWMMode
HystereticMode
I L
0
1
2
3
4
5
6
7
8
VCORE
HystereticMode
PWMMode
I L
0
1
2
3
4
5
6
7
8
Figure 4. Transitioning between PWM and Hysteretic Mode
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6
FAN5234
Due to different control mechanisms, the value of the load
junction temperature coefficient of about 0.4%/°C (consult
the MOSFET data sheet for actual values), the actual current
limit set point decreases proportional to increasing
MOSFET die temperature. A factor of 1.6 in the current limit
current where transition into PWM operation takes place is
typically higher compared to the load level at which
transition into Hysteretic Mode occurs. Hysteretic Mode can
be disabled by setting the FPWM pin HIGH.
set point should compensate for all MOSFET R
DS(ON)
variations, assuming the MOSFET’s heat sinking keep its
operating die temperature below 125°C.
Current Processing
The following discussion refers to Figure 6.
The current through R
resistor (I ) is sampled
SENSE
SNS
shortly after Q2 is turned on. That current is held and
summed with the output of the error amplifier. This
effectively creates a current−mode control loop. The resistor
Q2
LDRV
connected to the ISNS pin (R
current feedback loop. Equation 4 estimates the
) sets the gain in the
RSENSE
ISNS
SENSE
recommended value of R
as a function of the
) and the value of the
SENSE
R1
maximum load current (I
LOAD(MAX)
PGND
MOSFET R
. R
must be kept higher than 700 W
DS(ON) SENSE
even if the number calculated comes out less than 700 W:
ILOAD(MAX) RDS(ON)
+ ǒ
* 100Ǔ
RSENSE
(eq. 4)
150 mA
Figure 5. Improving Current−Sensing Accuracy
Setting the Current Limit
A ratio of ISNS is also compared to the current established
when a 0.9 V internal reference drives the ILIM pin:
More accurate sensing can be achieved by using a resistor
(R1) instead of the RDS(ON) of the FET, as shown in Figure 5.
This approach causes higher losses, but yields greater
(100 ) RSENSE
)
11
ILOAD
accuracy in both V
and I . R1 is a low value (e.g.
LIMIT
ǒ
Ǔ
RLIM
+
DROOP
RDS(ON)
(eq. 5)
10 mW) resistor.
Since the tolerance on the current limit is largely
dependent on the ratio of the external resistors, it is fairly
accurate if the voltage drop on the switching node side of
Current limit (I ) should be set high enough to allow
LIMIT
inductor current to rise in response to an output load
transient. Typically, a factor of 1.2 is sufficient. Since I
LIMIT
R
SENSE
is an accurate representation of the load current.
is a peak current cut−off value, multiply I
by the
LOAD(MAX)
When using the MOSFET as the sensing element, the
variation of R causes proportional variation in I
inductor ripple current (use 25%). For example, in Figure 1
the target for I would be:
.
DS(ON)
SNS
LIMIT
This value varies from device to device and has a typical
ILIMIT u 1.2 1.25 1.6 3.5 A [ 8.5 A
(eq. 6)
S/H
VtoI
0.17 pF
RSENSE
ISNS
in+
17 pF
1.5 MW
ISNS
ISNS
300 kW
LDRV
PGND
4.14 kW
TO
VSEN
SS
−
+
in−
RILIM
Reference
ILIM
0.9 V
C
SS
+
ILIM* 11
ILIM
−
2.5 V
I2=
ILIMdet.
Figure 6. Current Limit / Summing Circuits
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FAN5234
Duty Cycle Clamp
responses of a current mode modulator and the converter.
The type−2 amplifier, in addition to the pole at the origin, has
a zero−pole pair that causes a flat gain region at frequencies
between the zero and the pole.
During severe load increase, the error amplifier output can
go to its upper limit, pushing a duty cycle to almost 100% for
a significant amount of time. This could cause a large
increase of the inductor current and lead to a long recovery
from a transient over−current condition or even to a failure
at high input voltages. To prevent this, the output of the error
amplifier is clamped to a fixed value after two clock cycles
if severe output voltage excursion is detected, limiting
maximum duty cycle to:
C2
R2
R1
C1
VIN
REF
EA Out
VOUT
VIN
2.4
) ǒ Ǔ
DCMAX
+
(eq. 7)
VIN
This is designed to not interfere with normal PWM
operation. When FPWM is grounded, the duty cycle clamp
is disabled and the maximum duty cycle is 87%.
Modulator
Gate Driver
18
14
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals,
providing necessary amplification, level shifting, and
shoot−through protection. It also has functions that help
optimize the IC performance over a wide range of operating
conditions. Since MOSFET switching time can vary
dramatically from type to type and with the input voltage,
the gate control logic provides adaptive dead time by
monitoring the gate−to−source voltages of both upper and
lower MOSFETs. The lower MOSFET drive is not turned on
until the gate−to−source voltage of the upper MOSFET has
decreased to less than approximately 1 V. Similarly, the
upper MOSFET is not turned on until the gate−to−source
voltage of the lower MOSFET has decreased to less than
approximately 1 V. This allows a wide variety of upper and
lower MOSFETs to be used without concern for
simultaneous conduction or shoot−through.
0
f
f
f
P
P0
Z
Figure 7. Compensation
1
fz
+
+ 6 kHz
(eq. 9)
2pR2C1
1
fP
+
+ 600 kHz
(eq. 10)
2pR2C2
This region is also associated with phase “bump” or
reduced phase shift. The amount of phase shift reduction
depends the width of the region of flat gain and has
a maximum value of 90°. To further simplify the converter
compensation, the modulator gain is kept independent of the
input voltage variation by providing feed−forward of V to
the oscillator ramp.
IN
There must be a low−resistance, low−inductance path
between the driver pin and the MOSFET gate for the
adaptive dead−time circuit to work properly. Any delay
along that path subtracts from the delay generated by the
adaptive dead−time circuit and shoot−through may occur.
The zero frequency, the amplifier high−frequency gain,
and the modulator gain are chosen to satisfy most typical
applications. The crossover frequency appears at the point
where the modulator attenuation equals the amplifier
high−frequency gain. The system designer must specify the
output filter capacitors to position the load main pole
somewhere within one decade lower than the amplifier zero
frequency. With this type of compensation, plenty of phase
margin is achieved due to zero−pole pair phase “boost.”
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the frequency
axis due to excessive output filter capacitance. In this case,
the ESR zero placed within the 10 kHz to 50 kHz range
gives some additional phase boost. There is an opposite
trend in mobile applications to keep the output capacitor as
small as possible.
Frequency Loop Compensation
Due to the implemented current−mode control, the
modulator has a single−pole response with −1 slope at
frequency determined by load. Therefore:
1
fPO
+
(eq. 8)
2pROCO
where R is load resistance and CO is load capacitance.
O
For this type of modulator, type−2 compensation circuit is
usually sufficient. To reduce the number of external
components and simplify the design task, the PWM
controller has an internally compensated error amplifier.
Figure 7 shows a type two amplifier, its response, and the
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8
FAN5234
Protections
circuit is activated and HDRV is inhibited. The circuit
continues to pulse skip in this manner for the next eight clock
cycles. If at any time from the ninth to the sixteenth clock
The converter output is monitored and protected against
extreme overload, short circuit, over−voltage, and
under−voltage conditions.
cycle, the I
det is again reached, the over−current
LIM
A sustained overload on an output sets the PGOOD pin
LOW and latches off the chip. Operation is restored by
protection latch is set, disabling the chip. If I
occur between cycles 9 and 16, normal operation is restored
and the over−current circuit resets itself.
det does not
LIM
cycling the V voltage or by toggling the EN pin.
CC
If VOUT drops below the under−voltage threshold, the chip
shuts down immediately.
Over−Voltage / Under−Voltage Protection
Should the V
voltage exceed 120% of V
(0.9 V)
SEN
REF
due to an upper MOSFET failure or for other reasons, the
over−voltage protection comparator forces LDRV HIGH.
This action actively pulls down the output voltage and, in the
event of the upper MOSFET failure, eventually blows the
battery fuse. As soon as the output voltage drops below the
threshold, the OVP comparator is disengaged.
This OVP scheme provides a ‘soft’ crowbar function to
tackle severe load transients and does not invert the output
voltage when activated − a common problem for latched
OVP schemes.
PGOOD
1
2
8 CLK
I
L
V
OUT
Similarly, if an output short−circuit or severe load
transient causes the output to droop to less than 75% of its
regulation set point, the regulator shuts down.
3
CH1 5.0V
CH2 100mV
M 10.0s
Over−Temperature Protection
CH3 2.0AW
The chip incorporates an over−temperature protection
circuit that shuts the chip down when a die temperature
reaches 150°C. Normal operation is restored at die
temperature below 125°C with internal power on reset
asserted, resulting in a full soft−start cycle.
Figure 8. Over−Current Protection Waveforms
Over−Current Sensing
If the circuit’s current−limit signal (“I
is HIGH at the beginning of a clock cycle, a pulseskipping
det” in Figure 6)
LIM
DESIGN AND COMPONENT SELECTION
Guidelines
Output Inductor Selection
As an initial step, define operating input voltage range,
output voltage, and minimum and maximum load currents
for the controller.
For the examples in the following discussion, select
components for:
The minimum practical output inductor value keeps
inductor current just on the boundary of continuous
conduction at some minimum load. The industry standard
practice is to choose the ripple current to be somewhere from
15% to 35% of the nominal current. At light−load, the ripple
current determines the point where the converter
automatically switches to Hysteretic Mode to sustain high
efficiency. The following equations help to choose the
proper value of the output filter inductor:
V
V
from 5 V to 20 V
IN
= 1.8 V at I
= 3.5 A
OUT
LOAD(MAX)
Setting the Output Voltage
The internal reference is 0.9 V. The output is divided
down by a voltage divider to the VSEN pin (for example, R1
and R2 in Figure 1). The output voltage therefore is:
DVOUT
Dl + 2 * 1MIN
*
(eq. 13)
ESR
where DI is the inductor ripple current, which is chosen for
V
OUT * 0.9 V
0.9 V
R2
+
20% of the full load current and DV
is the maximum
(eq. 11)
OUT
R1
output ripple voltage allowed:
To minimize noise pickup on this node, keep the resistor
to GND (R2) below 2 K; for example R2 at 1.82 K, then
choose R5:
V
IN * VOUT VOUT
L +
(eq. 14)
fSW Dl
VIN
(1.8 kW) (1.8 V * 0.9)
R5 +
+ 1.82 K
(eq. 12)
0.9
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9
FAN5234
For this example, use:
In contrast, the high−side MOSFET (Q1) has a shorter
duty cycle, and its conduction loss has less impact. Q1,
however, sees most of the switching losses, so Q1’s primary
selection criteria should be gate charge.
VIN + 20 V, VOUT + 1.8 V
(eq. 15)
Dl + 20% 3.5 A + 0.7 A
fSW + 300 kHz
High−Side Losses
Therefore:
Figure 9 shows a MOSFET’s switching interval, with the
upper graph being the voltage and current on the drainto
L [ 8 mH
(eq. 16)
source and the lower graph detailing V vs. Time with
a constant current charging the gate. The x−axis therefore is
GS
Output Capacitor Selection
The output capacitor serves two major functions in
a switching power supply. Along with the inductor, it filters
the sequence of pulses produced by the switcher and it
supplies the load transient currents. The output capacitor
requirements are usually dictated by ESR, inductor ripple
current (DI), and the allowable ripple voltage (DV):
also representative of gate charge (Q ). C = C + C ,
G
ISS
GD
GS
and it controls t1, t2, and t4 timing. C receives the current
GD
from the gate driver during t3 (as V is falling). The gate
DS
charge (Q ) parameters on the lower graph are either
G
specified or can be derived from MOSFET datasheets.
Assuming switching losses are about the same for both the
rising edge and falling edge, Q1’s switching losses, occur
during the shaded time when the MOSFET has voltage
across it and current through it.
DV
ESR t
(eq. 17)
Dl
For this example,
0.1 V
0.7 A
DV
Dl
These losses are given by:
ESR(MAX)
+
+
+ 142 mW
PUPPER + PSW ) PCOND
(eq. 20)
In addition, the capacitor’s ESR must be low enough to
allow the converter to stay in regulation during a load step.
The ripple voltage due to ESR for the converter in Figure 1
where:
VDS IL
+ ǒ
Ǔ
PSW
2 ts fSW
(eq. 21)
(eq. 22)
is 100 m V . Some additional ripple will appear due to the
PP
2
capacitance value itself:
VOUT
VIN
Dl
2
+ ǒ Ǔ
PCOND
IOUT RDS(ON)
DV +
(eq. 18)
COUT 8 fSW
which is only about 1.5 mV for the converter in Figure 1 and
can be ignored.
P
P
is the upper MOSFET’s total losses and P
and
UPPER
SW
are the switching and conduction losses for a given
is at the maximum junction temperature
COND
The capacitor must also be rated to withstand the RMS
current, which is approximately 0.3 × (DI) or about 210 mA
for the converter in Figure 1. High−frequency decoupling
capacitors should be placed as close to the loads as
physically possible.
MOSFET. R
DS(ON)
(T ). t is the switching period (rise or fall time) and is t2 + t3
in Figure 9.
J
S
CISS
CGD
CISS
VDS
Input Capacitor Selection
The input capacitor should be selected by its ripple current
rating. The input RMS current at maximum load current (I )
L
is:
Ǹ
IRMS + IL D * D2
(eq. 19)
ID
where the converter duty cycle;
VOUT
VIN
D +
QGS
QGD
4.5 V
the circuit in Figure 1, with V = 6, calculates to
IN
VSP
VTH
I
= 1.6 A.
RMS
QG(SW)
Power MOSFET Selection
VGS
Losses in a MOSFET are the sum of its switching (P
)
SW
t1
t2
t3
t4
t5
and conduction (P
) losses.
COND
In typical applications, the FAN5234 converter’s output
voltage is low with respect to its input voltage. Therefore,
the lower MOSFET (Q2) is conducting the full−load current
for most of the cycle. Q2 should therefore be selected to
minimize conduction losses, thereby selecting a MOSFET
Figure 9. Switching Losses and QG
(CISS = CGS || CGD
)
with low R
.
DS(ON)
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10
FAN5234
VIN
power (P
for the FAN5234:
) in calculating the power dissipation required
GATE
5 V
CGD
RGATE
PGATE + QG VCC fSW
(eq. 25)
RD
HDRV
SW
where Q is the total gate charge to reach V
.
G
CC
G
CGS
Low−Side Losses
Q2 switches on or off with its parallel Schottky diode
conducting; therefore, ≈ 0.5 V. Since is
proportional to V , Q2’s switching losses are negligible
V
DS
P
SW
DS
Figure 10. Drive Equivalent Circuit
and Q2 is selected based on R
only.
DS(ON)
Conduction losses for Q2 are given by:
The driver’s impedance and C determine t2 while t3’s
ISS
2
PCOND + (1 * D) IOUT RDS(ON)
(eq. 26)
period is controlled by the driver’s impedance and Q
.
GD
Since most of tS occurs when V = V , use a constant
current assumption for the driver to simplify the calculation
of tS:
GS
SP
where R
is the R
of the MOSFET at the highest
DS(ON)
DS(ON)
operating junction temperature and D = V
minimum duty cycle for the converter.
Since D
produces a conservative result, simplifying the calculation.
The maximum power dissipation (P ) is a function
of the maximum allowable die temperature of the lowside
/ V is the
IN
OUT
QG(SW)
QS(SW)
< 20% for portable computers, (1−D) ≈ 1
MIN
ts
+
(eq. 23)
+ ǒ
Ǔ
IDRIVER
V
CC*VSP
DRIVER)RGATE
R
D(MAX)
Most MOSFET vendors specify Q and Q . Q
GD
GS
G(SW)
MOSFET, the Q , and the maximum allowable ambient
temperature rise:
JA
can be determined as:
QG(SW) + QGD ) QGS * QTH
(eq. 24)
T
J(MAX) * TA(MAX)
PD(MAX)
+
(eq. 27)
where Q is the gate charge required to get the MOSFET
QJA
TH
to its threshold (V ).
For the high−side MOSFET, V = V , which can be as
high as 20 V in a typical portable application. Care should
be taken to include the delivery of the MOSFET’s gate
TH
q
depends primarily on the amount of PCB area that can
JA
DS
IN
be devoted to heat sinking (see AN−1029 − Maximum
Power Enhancement Techniques for SO−8 Power MOSFET
for MOSFET thermal information).
Table 2. BUILD OF MATERIALS FOR 1.8 V, 3.5 A REGULATOR
Description
Capacitor 68 mF, Tantalum, 25 V, ESR 95 mW
Capacitor 10 nF, Ceramic
Qty.
1
Ref.
C1
Vendor
Part Number
AVX.
TPSV686*025#095
2
C2, C3
C4
Any
Capacitor 68 mF, Tantalum, 6 V, ESR 1.8 W
Capacitor 0.1 mF, Ceramic
Capacitor 330 mF, Tantalum, 6 V, ESR 100 mW
1.82 kW, 1% Resistor
1
AVX.
TAJV686*006
2
C5
Any
2
C6
AVX.
TPSE337*006#0100
2
R1, R2
R3
Any
1.3 kW, 1% Resistor
1
Any
Any
100 kW, 5% Resistor
1
R4
56.2 kW, 1% Resistor
1
R5
Any
Schottky Diode; 0.5 A, 20 V
Inductor 8.4 mH, 6 A
2
D1
ON Semiconductor
Any
MBR05S0L
1
L1
Dual MOSFET with Schottky
PWM Controller
1
Q
ON Semiconductor
ON Semiconductor
FDS6986AS (Note 1)
FAN5234
1
U1
1. If currents above 4 A continuous are required, use single SO−8 packages. For more information, refer to the Power MOSFET Selection
Section and AN−6002 for design calculations.
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11
FAN5234
Layout Considerations
low−current signals only. The use of normal thermal vias is
at the discretion of the designer.
Switching converters, even during normal operation,
produce short pulses of current that could cause substantial
ringing and be a source of EMI if layout constrains are not
observed.
There are two sets of critical components in a dc−dc
converter. The switching power components process large
amounts of energy at high rate and are noise generators. The
low−power components responsible for bias and feedback
functions are sensitive to noise.
Keep the wiring traces from the IC to the MOSFET gate
and source as short as possible and capable of handling peak
currents of 2 A. Minimize the area within the gate−source
path to reduce stray inductance and eliminate parasitic
ringing at the gate.
Locate small critical components, like the soft−start
capacitor and current sense resistors, as close as possible to
the respective pins of the IC.
A multi−layer printed circuit board is recommended.
Dedicate one solid layer for a ground plane. Dedicate
another solid layer as a power plane and break this plane into
smaller islands of common voltage levels.
Notice all the nodes that are subjected to high dV/dt
voltage swing; such as SW, HDRV, and LDRV. All
surrounding circuitry tends to couple the signals from these
nodes through stray capacitance. Do not oversize copper
traces connected to these nodes. Do not place traces
connected to the feedback components adjacent to these
traces. It is not recommended to use high density
interconnect systems, or micro−vias, on these signals. The
use of blind or buried vias should be limited to the
The FAN5234 utilizes advanced packaging technologies
with lead pitches of 0.6 mm. High performance analog
semiconductors utilizing narrow lead spacing may require
special considerations in PWB design and manufacturing. It
is critical to maintain proper cleanliness of the area
surrounding these devices. It is not recommended to use any
type of rosin or acid core solder, or the use of flux, in either
the manufacturing or touch up process as these may
contribute to corrosion or enable electro−migration and / or
eddy currents near the sensitive low−current signals. When
chemicals are used on or near the PWB, it is suggested that
the entire PWB be cleaned and dried completely before
applying power.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP 16
CASE 948AH−01
ISSUE O
DATE 19 SEP 2008
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TSSOP 16
PAGE 1 OF 1
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