FAN5350MPX [ONSEMI]
3MHz 600mA DC/DC 降压转换器，采用 WLCSP 和 MLP 封装;
| 型号： | FAN5350MPX |
| 厂家： | 
ONSEMI |
| 描述： | 3MHz 600mA DC/DC 降压转换器，采用 WLCSP 和 MLP 封装 开关 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：557K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FAN5350
3MHz, 600mA Step-Down DC-DC Converter in
Chip-Scale and MLP Packaging
Features
Description
The FAN5350 is a step-dow n sw itching voltage regulator
that delivers a fixed 1.82V from an input voltage supply of
2.7V to 5.5V. Using a proprietary architecture w ith
synchronous rectification, the FAN5350 is capable of
delivering 600mA at over 90% efficiency, w hile
maintaining a very high efficiency of over 80% at load
currents as low as 1mA. The regulator operates at a
nominal fixed frequency of 3MHz at full load, w hich
reduces the value of the external components to 1µH for
the output inductor and 4.7µF for the output capacitor.
.
.
.
.
.
.
.
.
.
.
.
.
3MHz Fixed-Frequency Operation
16µA Typical Quiescent Current
600mA Output Current Capability
2.7V to 5.5V Input Voltage Range
1.82V Fixed Output Voltage
Synchronous Operation
Pow er-Save Mode
Soft-Start Capability
At moderate and light loads, pulse frequency modulation is
used to operate the device in pow er-save mode w ith a
typical quiescent current of 16µA. Even w ith such a low
quiescent current, the part exhibits excellent transient
response during large load sw ings. At higher loads, the
system automatically sw itches to fixed-frequency control,
operating at 3MHz. In shutdow n mode, the supply current
drops below 1µA, reducing pow er consumption.
Input Under-Voltage Lockout (UVLO)
Thermal Shutdow n and Overload Protection
6-Lead 3 x 3mm MLP
5-Bump 1 x 1.37mm WLCSP
Applications
The FAN5350 is available in a 6-lead Molded Leadless
Package (MLP) and a 5-bump Wafer Level Chip Scale
Package (WLCSP).
.
.
.
.
.
Cell Phones, Smart-Phones
Pocket PCs
WLAN DC-DC Converter Modules
PDA, DSC, PMP, and MP3 Players
Portable Hard Disk Drives
Ordering Information
Operating
Temperature
Range
Eco
Status
Part Number
Package
Packing Method
5-Ball, Type-1 WL-CSP, 1x1.37mm,
.5mm Pitch
FAN5350UCX
FAN5350MPX
-40°C to 85°C
Green
Tape and Reel
Tape and Reel
6-Lead, Molded Leadless Package
(MLP), Dual, JEDEC MO-229, 3mm
Square, Extended DAP
-40°C to 85°C
Green
© 2007 Semiconductor Components Industries, LLC.
October-2017, Rev . 2
Publication Order Number:
FAN5350/D
Typical Applications
4.7µF
VIN
CIN
PGND
VIN
1
2
3
6
5
4
VIN
VIN
4.7µF
CIN
GND
A1 A3
P1
(GND)
AGND
FB
SW
EN
L1
B2
SW
FB
VOUT
1µH
EN
C1
C3
4.7µF
COUT
L1
VOUT
COUT
1µΗ
4.7µF
Figure 1. WLCSP, Bumps Facing Down
Figure 2. MLP, Leads Facing Down
Block Diagram
VIN
Current Limit
Bias
EN
1.8V
Reference
+
-
SW
Modulator
Logic
Driver
FB
3MHz OSC
Zero Crossing
GND
Figure 3. Block Diagram
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2
Pin Configurations
A3 A1
B2
A1 A3
GND
SW
VIN
VIN
GND
SW
B2
FB C3 C1 EN
EN C1 C3 FB
Figure 4. WLCSP - Bumps Facing Down
Figure 5. WLCSP - Bumps Facing Up
PGND
AGND
FB
1
2
3
6
5
4
VIN
SW
EN
P1
(GND)
Figure 6. 3x3mm MLP - Leads Facing Down
Pin Definitions
WLCSP
Pin #
A1
Name Description
VIN
Power Supply Input.
A3
GND
Ground Pin. Signal and pow er ground for the part.
Enable Pin. The device is in shutdow n mode w hen voltage to this pin is <0.4V and enabled w hen
>1.2V. Do not leave this pin floating.
C1
EN
C3
B2
FB
Feedback Analog Input. Connect directly to the output capacitor.
SW
Switching Node. Connection to the internal PFET sw itch and NFET synchronous rectifier.
MLP
Pin #
Name Description
Power Ground Pin. Pow er stage ground. Connect PGND and AGND together via the board
ground plane.
1
PGND
2
3
AGND
FB
Analog Ground Pin. Signal ground for the part.
Feedback Analog Input. Connect directly to the output capacitor.
Enable Pin. The device is in shutdow n mode w hen voltage to this pin is <0.4V and enabled w hen
>1.2V. Do not leave this pin floating.
4
EN
5
6
SW
VIN
Switching Node. Connection to the internal PFET sw itch and NFET synchronous rectifier.
Power Supply Input.
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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
Parameter
Min.
-0.3
-0.3
-40
Max.
6.0
Unit
V
Input Voltage w ith respect to GND
VIN
Voltage on any other pin w ith respect to GND
Junction Temperature
VIN
V
TJ
TSTG
TL
+150
+150
+260
°C
°C
°C
Storage Temperature
-65
Lead Temperature (Soldering 10 Seconds)
Human Body Model
4.5
1.5
2.0
200
MLP
kV
V
Electrostatic Discharge
Protection Level
ESD
Charged Device Model
Machine Model
WLCSP
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
2.7
0
Typ.
Max.
5.5
Unit
V
VCC
IOUT
L
Supply Voltage Range
Output Current
600
mA
µH
µF
µF
°C
Inductor
0.7
3.3
3.3
-40
-40
1.0
4.7
4.7
3.0
C
IN
Input Capacitor
12.0
12.0
+85
COUT
TA
Output Capacitor
Operating Ambient Temperature
Operating Junction Temperature
TJ
+125
°C
Thermal Properties
Symbol
Parameter
Min.
Typ.
Max.
Units
ΘJA_WLCSP
ΘJA_MLP
Note:
Junction-to-Ambient Thermal Resistance(1)
Junction-to-Ambient Thermal Resistance(1)
180
49
°C/W
°C/W
1. Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured w ith four-
layer 1s2p boards in accordance to JESD51- JEDEC standard. Special attention must be paid not to exceed junction
temperature TJ(max) at a given ambient temperate TA.
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Electrical Characteristics
Minimum and maximum values are at VIN = 2.7V to 5.5V, TA = -40°C to +85°C, C = COUT = 4.7µF, L = 1µH, unless
IN
otherw ise noted. Typical values are at TA = 25°C, VIN =3.6V.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
Power Supplies
Device is not sw itching, EN=VIN
Device is sw itching, EN=VIN
VIN = 3.6V, EN = GND
Rising Edge
16
18
µA
µA
µA
IQ
Quiescent Current
25
1.00
2.1
I
Shutdow n Supply Current
0.05
(SD)
1.8
1.75
1.2
VUVLO
Under-Voltage Lockout Threshold
V
Falling Edge
1.95
V(ENH)
V(ENL)
Enable HIGH-Level Input Voltage
Enable LOW-Level Input Voltage
Enable Input Leakage Current
V
V
0.4
I
EN = V IN or GND
0.01
3.0
1.00
µA
(EN)
Oscillator
f0SC
Oscillator Frequency
2.5
3.5
MHz
Regulation
I
LOAD = 0 to 600mA
1.775
1.784
1.820
1.820
1.865
1.856
300
V
V
VO
Output Voltage Accuracy
CCM
tSS
Output Driver
PMOS On Resistance
Soft-Start
EN = 0 -> 1
µs
V
IN = VGS = 3.6V
180
170
800
150
20
mΩ
mΩ
mA
°C
RDS(on)
NMOS On Resistance
VIN = VGS = 3.6V
Open-Loop(2)
CCM Only
ILIM
PMOS Peak Current Limit
Thermal Shutdow n
650
900
TTSD
THYS
Thermal Shutdow n Hysteresis
°C
Note:
2. The Electrical Characteristics table reflects open-loop data. Refer to Operation Description and Typical Characteristic
for closed-loop data.
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Operation Description
The FAN5350 is a step-dow n sw itching voltage regulator
that delivers a fixed 1.82V from an input voltage supply of
2.7V to 5.5V. Using a proprietary architecture w ith
synchronous rectification, the FAN5350 is capable of
delivering 600mA at over 90% efficiency, w hile
maintaining a light load efficiency of over 80% at load
currents as low as 1mA. The regulator operates at a
nominal frequency of 3MHz at full load, w hich reduces the
value of the external components to 1µH for the output
inductor and 4.7µF for the output capacitor.
Enable and Soft Start
Maintaining the EN pin LOW keeps the FAN5350 in non-
sw itching mode in w hich all circuits are off and the part
draw s ~50nA of current. Increasing EN above its
threshold voltage activates the part and starts the soft-
start cycle. During soft start, the current limit is increased
in discrete steps so that the inductor current is increased
in a controlled manner. This minimizes any large surge
currents on the input and prevents any overshoot of the
output voltage.
Control Scheme
The FAN5350 uses a proprietary non-linear, fixed-
frequency PWM modulator to deliver a fast load transient
Under-Voltage Lockout
When EN is high, the under-voltage lock-out keeps the
part from operating until the input supply voltage rises high
enough to properly operate. This ensures no misbehavior
of the regulator during start-up or shutdow n.
response, w hile maintaining
a constant sw itching
frequency over a w ide range of operating conditions. The
regulator performance is independent of the output
capacitor ESR, allow ing for the use of ceramic output
capacitors. Although this type of operation normally
results in a sw itching frequency that varies w ith input
voltage and load current, an internal frequency loop holds
the sw itching frequency constant over a large range of
input voltages and load currents.
Current Limiting
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high-side sw itch. Upon
reaching this point, the high-side sw itch turns off,
preventing high currents from causing damage.
For very light loads, the FAN5350 operates in
discontinuous current (DCM) single-pulse PFM mode,
w hich produces low output ripple compared w ith other
PFM architectures. Transition betw een PWM and PFM is
seamless, w ith a glitch of less than 14mV at VOUT during
the transition betw een DCM and CCM modes.
The peak current limit show n in Figure 16, ILIM(PK) is slightly
higher than the open-loop tested current limit, ILIM(OL), in the
Electrical Characteristics table. This is primarily due to the
effect of propagation delays of the IC current limit
comparator.
Combined
w ith
exceptional
transient
response
characteristics, the very low quiescent current of the
controller (<16µA) maintains high efficiency, even at very
light loads, w hile preserving fast transient response for
applications requiring very tight output regulation.
Thermal Shutdown
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the output
sw itching is disabled until the temperature on the die has
fallen sufficiently. The junction temperature at w hich the
thermal shutdow n activates is nominally 150°C w ith a
20°C hysteresis.
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Applications Information
Selecting the Inductor
The output inductor must meet both the required
inductance and the energy handling capability of the
application.
The increased RMS current produces higher losses
through the RDS(ON) of the IC MOSFETs as w ell as the
inductor ESR.
Increasing the inductor value produces low er RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually
results in an inductor w ith low er saturation current.
The inductor value affects the average current limit, the
PWM-to-PFM transition point, the output voltage ripple, and
the efficiency.
Table 1 show s the effects of inductance higher or low er
The ripple current (∆I) of the regulator is:
than the recommended 1µH on regulator performance.
VOUT
V
− VOUT
L • FSW
IN
Output Capacitor
∆I ≈
•
(1)
V
IN
Table 2 suggests 0603 capacitors. 0805 capacitors may
further improve performance in that the effective
capacitance is higher and ESL is low er than 0603. This
improves the transient response and output ripple.
The maximum average load current, IMAX(LOAD) is related to
the peak current limit, ILIM(PK) (see figure 17) by the ripple
current:
Increasing COUT has no effect on loop stability and can
therefore be increased to reduce output voltage ripple or
to improve transient response. Output voltage ripple,
∆VOUT , is:
∆I
2
(2)
IMAX(LOAD) = ILIM(PK)
−
The transition betw een PFM and PWM operation is
determined by the point at w hich the inductor valley
current crosses zero. The regulator DC current w hen the
inductor current crosses zero, IDCM, is:
1
∆VOUT = ∆I•
+ ESR
(5)
8 • COUT •FSW
∆I
IDCM
=
(3)
Input Capacitor
2
The 4.7µF ceramic input capacitor should be placed as
close as possible betw een the VIN pin and GND to
minimize the parasitic inductance. If a long w ire is used to
bring pow er to the IC, additional “bulk” capacitance
The FAN5350 is optimized for operation w ith L=1µH, but is
stable w ith inductances ranging from 700nH to 3.0µH. The
inductor should be rated to maintain at least 80% of its
value at ILIM(PK)
.
(electrolytic or tantalum) should be placed betw een C
IN
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since ∆I increases,
the RMS current increases, as do the core and skin effect
losses.
and the pow er source lead to reduce ringing that can
occur betw een the inductance of the pow er source leads
and C .
IN
∆I2
12
2
(4)
IRMS
=
IOUT(DC)
+
Table 1. Effects of changes in inductor value (from 1µH recommended value) on regulator performance
Inductor Value
Increase
IMAX(LOAD) EQ. 2
Increase
ILIM(PK)
Decrease
Increase
∆VOUT EQ. 5
Decrease
Transient Response
Degraded
Decrease
Decrease
Increase
Improved
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PCB Layout Guidelines
For the bill of materials of the FAN5350 evaluation board,
see Table 1. There are only three external components:
the inductor and the input and output capacitors. For any
buck sw itcher IC, including the FAN5350, it is alw ays
important to place a low -ESR input capacitor very close to
the IC, as show n in Figure 7. That ensures good input
decoupling, w hich helps reduce the noise appearing at
the output terminals and ensures that the control sections
of the IC do not behave erratically due to excessive noise.
This reduces sw itching cycle jitter and ensures good
overall performance. It is not considered critical to place
either the inductor or the output capacitor very close to
the IC. There is some flexibility in moving these tw o
components further aw ay from the IC.
Table 2. FAN5350 Evaluation Board Bill of Materials (optional parts are installed by request only)
Description
Qty.
Ref.
Vendor
TOKO
Part Number
1117AS-1R2M
1.2µH, 1.8A, 55mΩ
Inductor
1.3µH, 1.2A, 90mΩ
1.5µH, 1.3A
1
L1
FDK
MIPSA2520D1R0
CBC3225T15MR
GRM39 X5R 475K 6.3
Taiyo Yuden
MURATA
Capacitor 4.7µF, ±10%, 6.3V, X5R, 0603
IC DC/DC Regulator in CSP, 5 bumps
Load Resistor (Optional)
2
1
1
C ,COUT
IN
ON
U1
FAN5350UCX
Semiconductor
RLOAD
Any
Feedback Loop
One key advantage of the non-linear architecture is that
there is no traditional feedback loop. The loop response to
changes in VOUT is essentially instantaneous, w hich
explains its extraordinary transient response. The
absence of a traditional, high-gain compensated linear
loop means that the FAN5350 is inherently stable over a
w ide range of LOUT and COUT
.
LOUT can be reduced further for a given application,
provided it is confirmed that the calculated peak current
for the required maximum load current is less than the
minimum of the closed-loop current limit. The advantage is
that this generally leads to improved transient response,
since a small inductance allow s for a much faster
increase in current to cope w ith any sudden load demand.
The inductor can be increased to 2.2µH; but, for the same
reason, the transient response gets slightly degraded. In
that case, increasing the output capacitor to 10µF helps
significantly.
Figure 7. The FAN5350 Evaluation Board PCB (CSP)
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Typical Performance Characteristics
VIN = 3.6V, TA = 25°C, VEN = VIN, according to the circuit in Figure 1 or Figure 2, unless otherw ise specified.
1850
24
22
20
18
1840
DCM spreading
+85°C
1830
1820
1810
CCM
+25°C
16
14
-40°C
1800
1790
12
10
0
100
200
300
400
500
600
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Battery Voltage (V)
Load Current (mA)
Figure 8. Quiescent Current vs. Battery Voltage
Figure 9. Load Regulation, Increasing Load
600
85°C CCM border
-30°C CCM border
500
400
300
200
100
0
85°C DCM border
-30°C DCM border
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Battery Voltage (V)
Figure 10. Switch Mode Operating Areas
Figure 11. Switch Mode Over Temperature
2.00
1.75
1835
1830
VIN=2.7V
VIN=5.5V
1.50
1825
VIN=2.7V
1.25
1.00
1820
VIN=3.6V
1815
0.75
VIN=5.5V
VIN=3.6V
1810
1805
0.50
0.25
0
ILOAD=300mA
1800
-40
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
-20
0
20
40
60
80
Load Current (A)
Ambient Temperature (°C)
Figure 12. DC Current Voltage Output
Characteristics
Figure 13. Output Voltage vs. Temperature
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Typical Performance Characteristics (Continued)
VIN = 3.6V, TA = 25°C, VEN = VIN, according to the circuit in Figure 1 or Figure 2, unless otherw ise specified.
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
VIN=2.5V
VIN=2.7V
VIN=3.3V
VIN=3.6V
VIN=4.2V
VIN=5V
-40°C
+85°C
+25°C
VIN=5.5V
0.001
0.010
0.100
1.000
0.001
0.010
0.100
1.000
Load Current (A)
Load Current (A)
Figure 14. Power Efficiency vs. Load Current
Figure 15. Power Efficiency Over Temperature
Range
1.3
250
200
VIN=5.5V
1.2
1.1
150
+85°C
1.0
VIN=3.6V
100
0.9
+25°C
50
0.8
VIN=2.7V
-40°C
5.5
0
2.5
0.7
3.0
3.5
4.0
4.5
5.0
-40
-20
0
20
40
60
80
Battery Voltage (V)
Ambient Temperature (°C)
Figure 16. PMOS Current Limit in Closed Loop
Figure 17. Shutdown Supply Current vs.
Battery Voltage
85dB
3.3
250mA Load
3.2
3.1
3.0
2.9
2.8
2.7
-40°C
+25°C
5dB
/div
+85°C
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
35dB
1Hz
10Hz
100Hz
1kHz
10kHz
Battery Voltage (V)
Figure 18. Power Supply Rejection Ratio in CCM
Figure 19. Switching Frequency in CCM
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Typical Performance Characteristics (Continued)
VIN = 3.6V, TA = 25°C, VEN = VIN, according to the circuit in Figure 1 or Figure 2, unless otherw ise specified.
IL, 0.5A / div.
IL, 0.5A / div.
VOUT, 0.5V / div.
VOUT, 0.5V / div.
EN, 5.0V / div.
EN, 5.0V / div.
H scale: 20µs / div.
Figure 20. Startup, Full Load
H scale: 10µs / div.
Figure 21. Startup, No Load
VOUT(ac), 20mV / div.
VOUT(ac), 20mV / div.
ILOAD, 0.5A / div.
I
LOAD, 0.5A / div.
H scale: 1µs / div.
H scale: 1µs / div.
Figure 22. Fast Load Transient, No Load to Full Load
Figure 23. Fast Load Transient, Full Load to No Load
V
SW, 5V / div.
VSW, 5V / div.
V
OUT(ac), 20mV / div.
VOUT(ac), 20mV / div.
ILOAD = 600mA
ILOAD = 300mA
ILOAD = 50mA
ILOAD = 1mA
H scale: 20µs / div.
H scale: 20µs / div.
Figure 24. Fast Load Transient in CCM
Figure 25. Fast Load Transient in DCM
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Typical Performance Characteristics (Continued)
VIN = 3.6V, TA = 25°C, VEN = VIN, according to the circuit in Figure 1 or Figure 2, unless otherw ise specified.
VSW, 2V / div.
VSW, 5V / div.
V
OUT, 20mV / div.
VOUT, 20mV / div.
ILOAD, 0.5A / div.
I
LOAD = 300mA
ILOAD = 20mA
H scale: 20µs / div.
H scale: 2ms / div.
Figure 26. Fast Load Transient DCM – CCM – DCM
Figure 27. Slow Load Transient DCM – CCM – DCM
VOUT(ac), 20mV / div.
VOUT(ac), 20mV / div.
V
IN = 3.6V
VIN = 3.6V
VIN = 3.0V
VIN = 3.0V
H scale: 10µs / div.
H scale: 10µs / div.
Figure 28. Line Transient, 600mV, 50mA Load
Figure 29. Line Transient, 600mV, 50mA Load
VOUT(ac), 10mV / div.
VIN = 3.6V
VIN = 3.0V
ILOAD = 350mA
I
LOAD = 100mA
H scale: 5µs / div.
Figure 30. Combined Line (600mV) and Load (100mA to 350mA) Transient Response
VSW, 2V / div.
VSW, 2V / div.
IL = 0.2A / div.
IL = 0.1A / div.
VOUT(ac), 20mV / div.
VOUT(ac), 20mV / div.
H scale: 1µs / div.
Figure 31. Typical Waveforms in DCM, 50mA Load
H scale: 200ns / div.
Figure 32. Typical Waveforms in CCM, 150mA Load
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12
Physical Dimensions
3.50
2.45
3.0
A
0.15
C
2X
B
3.50
2.10
1.65
0.45
3.0
(0.70)
0.95 TYP
0.45 TYP
0.15 C
PIN #1 IDENT
2X
TOP VIEW
RECOMMENDED LAND PATTERN
0.8 MAX
0.10 C
(0.20)
0.08 C
0.05
0.00
C
SEATING
PLANE
SIDE VIEW
2.25
PIN #1 IDENT
3
1
0.45
0.20
0.40
1.65
0.2 MIN
4
6
0.30~0.45
0.10
0.95
C
C
A B
1.90
0.05
BOTTOM VIEW
A. CONFORMS TO JEDEC REGISTRATION MO-229,
VARIATION WEEA, DATED 11/2001
EXCEPT FOR DAP EXTENSION TABS
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
Figure 32. 6-Lead Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change
in any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON
Semiconductor’s worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor
products.
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13
Physical Dimensions (Continued)
F
BALL A1
INDEX AREA
A
E
(0.50)
(0.866)
(Ø0.25)
Cu PAD
B
D
0.03 C
A1
2X
(Ø0.35)
SOLDER MASK
OPENING
F
(0.433)
0.03 C
2X
RECOMMENDED LAND PATTERN (NSMD)
TOP VIEW
0.332±0.018
0.06 C
E
0.625 MAX
0.250±0.025
0.05 C
D
C
SEATING PLANE
SIDE VIEWS
(X)+/-.018
F
A. NO JEDEC REGISTRATION APPLIES
B. DIMENSIONS ARE IN MILLIMETERS.
0.005
C A B
0.50
5 X Ø0.315 +/- .025
0.50
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C
D
E
F
DATUM C, THE SEATING PLANE, IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
PACKAGE TYPICAL HEIGHT IS 582 MICRONS
+/- 43 MICRONS (539-625 MICRONS)
FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
B
A
0.433
1 2 3
BOTTOM VIEW
(Y)+/-.018
F
G. BALL COMPOSITION: Sn95.5Ag3.9Cu0.6
SAC405 ALLOY
H. DRAWING FILENAME: MKT-UC005AArev5
Product Specific Dimensions
Product
D
E
X
Y
FAN5350UCX
1.350 +/- 0.040
0.980 +/- 0.040
0.242
0.244
Figure 33. 5-Bump Wafer-Level Chip-Scale Package (WLCSP)
Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change
in any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON
Semiconductor’s worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor
products.
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