FAN5361UMP15X [ONSEMI]
6MHz，600mA/750mA 同步降压稳压器;
| 型号： | FAN5361UMP15X |
| 厂家： | 
ONSEMI |
| 描述： | 6MHz，600mA/750mA 同步降压稳压器 开关 光电二极管 稳压器 |
| 文件： | 总18页 (文件大小：1151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAN5361
6 MHz, 600 mA / 750 mA Synchronous Buck Regulator
Description
Features
The FAN5361 is a 600 mA or 750 mA, step-dow n, sw itching
voltage regulator that delivers a fixed output from a 2.3 V to
5.5 V input voltage supply. Using a proprietary architecture
w ith synchronous rectification, the FAN5361 is capable of
6 MHz Fixed-Frequency Operation
35 µA Typical Quiescent Current
Best-in-Class Load Transient Response
Best-in-Class Efficiency
delivering
a peak efficiency of 92%, w hile maintaining
600 mA or 750 mA Output Current Capability
2.3 V to 5.5 V Input Voltage Range
1.0 to 1.90 V Fixed Output Voltage
Low Ripple Light-Load PFM Mode
Forced PWM and External Clock Synchronization
Internal Soft-Start
efficiency over 80% at load currents as low as 1 mA.
The regulator operates at a nominal fixed frequency of
6 MHz, w hich reduces the value of the external components
to 470 nH for the output inductor and 4.7 µF for the output
capacitor. The PWM modulator can be synchronized to an
external frequency source.
Input Under-Voltage Lockout (UVLO)
Thermal Shutdow n and Overload Protection
6-bump WLCSP, 0.4 mm Pitch
At moderate and light loads, pulse frequency modulation is
used to operate the device in pow er-save mode w ith a
typical quiescent current of 35 µA. Even w ith such a low
quiescent current, the part exhibits excellent transient
response during large load sw ings. At higher loads, the
system automatically sw itches to fixed-frequency control,
operating at 6 MHz. In shutdow n mode, the supply current
drops below 1 µA, reducing pow er consumption. For
applications that require minimum ripple or fixed frequency,
PFM mode can be disabled using the MODE pin.
6-pin 2 x 2 mm UMLP
Applications
Cell Phones, Smart Phones
Tablets, Netbooks®, Ultra-Mobile PCs
3G, LTE, WiMAX™, WiBro®, and WiFi® Data Cards
Gaming Devices, Digital CamerasDC/DC Micro Modules
The FAN5361 is available in 6-bump, 0.4 mm pitch, Wafer-
Level Chip-Scale Package (WLCSP) and a 6-lead 2 x 2 mm
ultra-thin MLP package (UMLP).
Typical Applications
GND
EN
FB
MODE
SW
VIN
EN
1
2
3
6
5
4
A1 A2
B1 B2
C1 C2
COUT
L1
L1
4.7F
CIN
2.2F
SW
CIN
2.2F
(AGND)
470nH
470nH
FB
GND
VIN
MODE
COUT
4.7F
Figure 1. Typical Applications
All trademarks are the property of their respective owners.
© 2008 Semiconductor Components Industries, LLC.
October-2017, Rev. 2
Publication Order Number:
FAN5361/D
OrderingInformation
Output
Part Number
Package
Temperature Range
Packing
Voltage(1)
FAN5361UC123X
1.233 V
WLCSP-6, 0.4 mm Pitch
FAN5361UC182X
FAN5361UC19X
1.820 V
1.900 V
1.233 V
1.500 V
1.820 V
–40 to +85°C
Tape and Reel
FAN5361UMP123X
FAN5361UMP15X
FAN5361UMP182X
6-Lead, 2 x 2 mm UMLP
Note:
1. Other voltage options available on request. Contact a ON Semiconductor representative.
Pin Configurations
A1
B1
C1
A2
B2
C2
A2
B2
C2
A1
B1
C1
MODE
SW
VIN
EN
VIN
EN
MODE
SW
FB
GND
GND
FB
Figure 2. WLCSP, Bumps Facing Down
Figure 3. WLCSP, Bumps Facing Up
1
2
3
6
FB
GND
P1
(GND)
5
SW
EN
4
VIN
MODE
Figure 4. UMLP, Leads Facing Down
Pin Definitions
Pin #
Name
Description
WLCSP UMLP
MODE. Logic 1 on this pin forces the IC to stay in PWM mode. A logic 0 allow s the IC to
automatically sw itch to PFM during light loads. The regulator also synchronizes its sw itching
frequency to four times the frequency provided on this pin. Do not leave this pin floating. When
tying HIGH, use at least 1kΩ series resistor if VIN is expected to exceed 4.5 V.
A1
3
MODE
B1
C1
C2
2
1
6
SW Switching Node. Connect to output inductor.
FB Feedback / VOUT. Connect to output voltage.
GND Ground. Pow er and IC ground. All signals are referenced to this pin.
Enable. The device is in shutdow n mode w hen voltage to this pin is <0.4 V and enabled w hen
>1.2 V. Do not leave this pin floating. When tying HIGH, use at least 1 kΩ series resistor if VIN is
expected to exceed 4.5 V.
B2
A2
5
4
EN
VIN Input Voltage. Connect to input pow er source.
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Absolute MaximumRatings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings
are stress ratings only.
Symbol
VIN
Parameter
Min.
–0.3
–0.3
–0.3
–0.3
Max.
7.0
VIN + 0.3(2)
VIN + 0.3(2)
VIN + 0.3(2)
Unit
Input Voltage
V
V
V
V
VSW
Voltage on SW Pin
EN and MODE Pin Voltage
Other Pins
VCTRL
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
4.0
1.5
Electrostatic Discharge
Protection Level
ESD
kV
TJ
TSTG
TL
Junction Temperature
Storage Temperature
–40
–65
+150
+150
+260
°C
°C
°C
Lead Soldering Temperature, 10 Seconds
Note:
2. Lesser of 7 V or VIN+0.3 V.
RecommendedOperatingConditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend
exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
2.3
0
Typ.
Max.
5.5
Unit
V
VCC
IOUT
L
Supply Voltage Range
Output Current
Inductor
600
mA
µH
µF
µF
°C
0.47
2.2
C
IN
Input Capacitor
Output Capacitor
COUT
TA
1.6
–40
–40
4.7
12.0
+85
Operating Ambient Temperature
Operating Junction Temperature
TJ
+125
°C
ThermalProperties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured w ith four-layer 1s2p
boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(max) at a
given ambient temperate TA.
Symbol
Parameter
Typical
150
Unit
°C/W
°C/W
WLCSP
UMLP
Junction-to-Ambient Thermal Resistance
JA
49
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ElectricalCharacteristics
Minimum and maximum values are at VIN = VEN = 2.3V to 5.5V, VMODE = 0V (AUTO Mode), TA = -40°C to +85°C; circuit of
Figure 1, unless otherw ise noted. Typical values are at TA = 25°C, VIN = VEN = 3.6 V.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power Supplies
No Load, Not Sw itching
PWM Mode
35
6
55
µA
mA
µA
V
IQ
Quiescent Current
I
Shutdow n Supply Current
VIN = 3.6 V, EN = GND
Rising VIN
0.05
2.15
150
1.00
2.25
(SD)
VUVLO
Under-Voltage Lockout Threshold
VUVHYST Under-Voltage Lockout Hysteresis
mV
Logic Inputs: EN and MODE Pins
VIH
VIL
Enable HIGH-Level Input Voltage
Enable LOW-Level Input Voltage
Logic Input Hysteresis Voltage
Enable Input Leakage Current
1.2
V
V
0.4
VLHYST
100
mV
µA
I
IN
Pin to VIN or GND
0.01
1.00
Switching and Synchronization
fSW
Sw itching Frequency(3)
MODE Synchronization Range(3)
VIN = 3.6 V, TA = 25°C
5.4
1.3
6.0
1.5
6.6
1.7
MHz
MHz
fSYNC
Square Wave at MODE Input
Regulation
ILOAD = 0 to 750 mA (4)
PWM Mode(4)
1.832
1.832
1.784
1.784
1.470
1.470
1.207
1.207
1.900
1.900
1.820
1.820
1.500
1.500
1.233
1.233
180
1.957
1.938
1.875
1.856
1.545
1.530
1.272
1.259
300
1.900 V
ILOAD = 0 to 600 mA
PWM Mode
1.820 V
Output Voltage
VO
V
Accuracy
1.500 V
ILOAD = 0 to 600 mA
PWM Mode
ILOAD = 0 to 600 mA
PWM Mode
1.233 V
tSS
Soft-Start
From EN Rising Edge
µs
Output Driver
PMOS On Resistance
VIN = VGS = 3.6 V
VIN = VGS = 3.6 V
VOUT = 1.233 V, 1.5 V, 1.82 V
VOUT = 1.9 V
350
225
1100
1375
150
15
RDS(on)
m
NMOS On Resistance
900
1250
1550
PMOS Open-Loop Peak Current
Limit(5)
ILIM(OL)
mA
1180
TTSD
THYS
Thermal Shutdow n
CCM Only
°C
°C
Thermal Shutdow n Hysteresis
Notes:
3. Limited by the effect of tOFF minimum (see Figure 14 and Figure 15 in Typical Performance Characteristics).
4. Output voltage accuracy minimum: 1.862 V for VIN 2.7 to 5.5 V on 1.9 V option.
5. Refer to Operation Description and Typical Characteristics for closed-loop data.
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Typical Performance Characteristics
Unless otherw ise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C.
100%
95%
90%
85%
80%
75%
100%
95%
90%
85%
80%
75%
Auto 2.3VIN
25C
85C
-30C
Auto 2.7VIN
Auto 3.6VIN
Auto 4.2VIN
70%
65%
60%
55%
50%
70%
65%
60%
55%
50%
1
10
100
1000
1
10
100
1000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 5. Efficiency vs. Load Current and Input Supply Figure 6. Efficiency vs. Load Current and Temperature
100%
95%
90%
85%
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
80%
75%
70%
65%
60%
55%
50%
VIN=2.3V
VIN=2.7V
VIN=3.6V
VIN=4.2V
Auto PFM/PWM
Forced PWM
1
10
100
1000
1
10
100
1000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 7. 1.233 VOUT Efficiency vs. Load Current
and Supply
Figure 8. Efficiency, Auto PWM/PFM vs. Forced PWM
1.248
1.84
1.83
VIN=2.3V
1.243
VIN=2.7V
VIN=3.6V
1.238
VIN=4.2V
1.82
1.233
1.228
1.223
VIN=2.3V
VIN=2.7V
1.81
VIN=3.6V
VIN=4.2V
1.80
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0
100
200
300
400
500
600
Load Current (mA)
I LOAD Output Current (A)
Figure 9. Load Regulation
Figure 10. 1.233 VOUT Load Regulation vs. Input Supply
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Typical Performance Characteristics (Continued)
Unless otherw ise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C.
1.830
45
40
3.6VIN
5.5VIN
2.5VIN
1.825
35
30
1.820
25
20
1.815
15
10
5
1.810
1.805
Auto PWM/PFM
Forced PWM
0
1
10
100
1,000
0
100
200
300
400
500
600
I LOAD Output Current (mA)
Load Current (mA)
Figure 11. Load Regulation, Auto PFM / PWM and
Forced PWM
Figure 12. 1.82 VOUT Peak-to-Peak Output Voltage
Ripple
7
30
FPWM Mode
6
5
4
3.6VIN
25
5.5VIN
2.5VIN
20
15
10
5
3
VIN>2.9V
VIN=2.7V
2
1
VIN=2.5V
VIN=2.3V
0
0
100
200
300
400
500
600
0
0.1
0.2
0.3
0.4
0.5
0.6
Load Current (mA)
Load Current (A)
Figure 13. 1.233 VOUT Peak-to-Peak Output Voltage
Ripple
Figure 14. Effect of tOFF(MIN) on Reducing Switching
Frequency
7
350
FPWM Mode
6
5
4
3
300
Always PWM
250
200
The switching mode changes
at these borders
150
VIN>2.4V
100
2
Always PFM
50
1
PFM border
VIN=2.3V
PWMborder
0
0
2.5
3.0
3.5
4.0
4.5
5.0 5.5
0
0.1
0.2
0.3
0.4
0.5
0.6
Input Voltage (V)
Load Current (A)
Figure 16. PFM / PWM Boundaries
Figure 15. 1.233 VOUT Effect of tOFF(MIN) on Reducing
Switching Frequency
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Typical Performance Characteristics (Continued)
Unless otherw ise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C.
42
250
Always PWM
40
200
The switching mode changes
at these borders
38
150
36
100
Always PFM
34
50
PFM border
32
PWM border
VEN=VIN
VEN=1.8V
0
30
2.5
3.0
3.5
4.0
4.5
5.0 5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage(V)
VIN Input Voltage (V)
Figure 17. 1.233 VOUT PFM / PWM Boundaries
Figure 18. Quiescent Current vs. Input Voltage
0.20
0.18
VIN=5.5V
VEN=0V
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
Figure 19. Shutdown Current vs. Temperature
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Typical Performance Characteristics (Continued)
Unless otherw ise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C, 5µs/div. horizontal sw eep.
Figure 20. Line Transient 3.3 VIN to 3.9 VIN,
50 mA Load, 10 µs/div.
Figure 21. Line Transient 3.3 VIN to 3.9 VIN,
250 mA Load, 10 µs/div.
Figure 22.
Combined Line/Load Transient 3.9 to
Figure 23. Combined Line/Load Transient 3.3 to 3.9 VIN
Combined with 400 mA to 40 mA Load Transient
3.3 VIN Combined with 40 mA to 400 mA Load Transient
Figure 24. Load Transient 0 to 150 mA, 2.5 VIN
Figure 25. Load Transient 50 to 250 mA, 2.5 VIN
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Typical Performance Characteristics (Continued)
Unless otherw ise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C, 5 µs/div. horizontal sw eep.
Figure 26. Load Transient 150 to 400 mA, 2.5 VIN
Figure 27. Load Transient 0 to 150 mA, 3.6 VIN
Figure 28. Load Transient 50 to 250 mA, 3.6 VIN
Figure 29. Load Transient 150 to 400 mA, 3.6 VIN
Figure 30. Load Transient 0 to 150 mA, 4.5 VIN
Figure 31. Load Transient 50 to 250 mA, 4.5 VIN
Figure 32. Load Transient 150 to 400 mA, 4.5 VIN
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Typical Performance Characteristics (Continued)
Unless otherw ise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C, 5 µs/div. horizontal sw eep.
Figure 33. Metallic Short Applied at VOUT, 50 μs/div.
Figure 34. Metallic Short Applied at VOUT
Figure 35. Over-Current Fault Response,
Figure 36. Over-Current Fault Response, RLOAD = 1 Ω
RLOAD = 1 Ω, 50 μs/div.
Figure 37. Overload Recovery to Light Load, 50 μs/div.
Figure 38. Soft-Start, RLOAD = 50 Ω, 20 μs/div.
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Typical Performance Characteristics (Continued)
Unless otherw ise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C.
SW
Figure 39. SW-Node Jitter (Infinite Persistence), ILOAD = 200 mA, 50 ns/div.
Figure 40. Power Supply Rejection Ratio at 300 mA Load
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OperationDescription
The FAN5361 is a 600 mA or 750 mA , step-dow n, sw itching
voltage regulator that delivers a fixed output from an input
voltage supply of 2.3 V to 5.5 V. Using a proprietary
architecture w ith synchronous rectification, the FAN5361 is
capable of delivering a peak efficiency of 92%, w hile
maintaining efficiency over 80% at load currents as low as
1 mA. The regulator operates at a nominal frequency of
6 MHz at full load, w hich reduces the value of the external
components to 470 nH for the inductor and 4.7 µF for the
output capacitor.
To prevent shut-dow n during soft-start, the follow ing condition
must be met:
(2)
I
I
I
DISP
LOAD MAX(DC)
w here IMAX(DC) is the maximum load current the IC is
guaranteed to support (600 mA or 750 mA).
Table 1 show s combinations of COUT that allow the IC to start
successfully w ith the minimum RLOAD that can be supported.
Table 1. Minimum RLOAD Values for Soft-Start with
Various COUT Values
Control Scheme
The FAN5361 uses a proprietary, non-linear, fixed-frequency
PWM modulator to deliver a fast load transient response,
w hile maintaining a constant sw itching frequency over a w ide
range of operating conditions. The regulator performance is
independent of the output capacitor ESR, allow ing for the use
of ceramic output capacitors. Although this type of operation
normally results in a sw itching frequency that varies w ith input
voltage and load current, an internal frequency loop holds the
sw itching frequency constant over a large range of input
voltages and load currents.
COUT
Minimum RLOAD
VOUT / 0.60
4.7 F, 0402
2 X 4.7 F, 0402
10 F, 0603
10 F, 0805
VOUT / 0.60
VOUT / 0.60
VOUT / 0.50
Startup into Large COUT
Multiple soft-start cycles are required for no-load startup if
COUT is greater than 15 F. Large COUT requires light initial
load to ensure the FAN5361 starts appropriately. The IC
shuts dow n for 85 s w hen IDISP exceeds ILIMIT for more than
21 s of current limit. The IC then begins a new soft-start
cycle. Since COUT retains its charge w hen the IC is off, the IC
reaches regulation after multiple soft-start attempts.
For very light loads, the FAN5361 operates in Discontinuous
Current Mode (DCM) single-pulse PFM mode, w hich
produces low output ripple compared w ith other PFM
architectures. Transition betw een PWM and PFM is
seamless, w ith a glitch of less than 18 mV at VOUT during the
transition betw een DCM and CCM modes.
Combined
w ith
exceptional
transient
response
characteristics, the very low quiescent current of the
controller (35 µA) maintains high efficiency; even at very light
loads, w hile preserving fast transient response for
applications requiring tight output regulation.
MODE Pin
Logic 1 on this pin forces the IC to stay in PWM mode. A
logic 0 allow s the IC to automatically sw itch to PFM during
light loads. If the MODE pin is toggled, the converter
synchronizes its sw itching frequency to four times the
frequency on the mode pin (fMODE).
Enable and Soft-Start
When EN is LOW, all circuits in FAN5361 are off and the IC
draw s ~50 nA of current. When EN is HIGH and VIN is above
its UVLO threshold, the regulator begins a soft-start cycle. The
output ramp during soft-start is a fixed slew rate of 50 mV/s
from 0 to 1 VOUT, then 12.5 mV/s until the output reaches its
setpoint. Regardless of the state of the MODE pin, PFM mode
is enabled to prevent current from being discharged from COUT
if soft-start begins w hen COUT is charged.
The MODE pin is internally buffered w ith a Schmitt trigger,
w hich allow s the MODE pin to be driven w ith slow rise and
fall times. An asymmetric duty cycle for frequency
synchronization is also permitted as long as the minimum
time below VIL(MAX) or above VIH(MAX) is 100 ns.
Current Limit, Fault Shutdown, and Restart
A heavy load or short circuit on the output causes the current
in the inductor to increase until a maximum current threshold
is reached in the high-side sw itch. Upon reaching this point,
the high-side sw itch turns off, preventing high currents from
causing damage. The regulator continues to limit the current
cycle-by-cycle. After 21 µs of current limit, the regulator
triggers an over-current fault, causing the regulator to shut
The IC may fail to start if heavy load is applied during startup
and/or if excessive COUT is used. This is due to the current-
limit fault response, w hich protects the IC in the event of an
over-current condition present during soft-start.
The current required to charge COUT during soft-start is
commonly referred to as “displacement current” is given as:
dow n for about 85s before attempting a restart.
dV
If the fault w as caused by short circuit, the soft-start circuit
attempts to restart and produces an over-current fault after
about 32 s, w hich results in a duty cycle of less than 30%,
limiting pow er dissipation.
IDISP COUT
(1)
dt
dV
w here the
term refers to the soft-start slew rate above.
dt
The closed-loop peak-current limit, ILIM(PK), is not the same as
the open-loop tested current limit, ILIM(OL), in the Electrical
Characteristics table. This is primarily due to the effect of
propagation delays of the IC current limit comparator.
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When VIN is LOW, fixed sw itching is maintained as long as
Under-Voltage Lockout (UVLO)
VOUT
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage rises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdow n.
.
1 tOFF (MIN) fSW 0.7
V
IN
The sw itching frequency drops w hen the regulator cannot
provide sufficient duty cycle at 6MHz to maintain regulation.
This occurs w hen VOUT is greater than or equal to 1.82 V and
VIN is below 2.9 V at high load currents (see Figure 15).
Thermal Shutdown (TSD)
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the output
sw itching is disabled until the temperature on the die has
fallen sufficiently. The junction temperature at w hich the
thermal shutdow n activates is nominally 150°C w ith a 15°C
hysteresis.
The calculation for sw itching frequency is given by:
1
(3)
(4)
fSW min
,6MHz
tSW(MAX)
w here:
Minimum Off-Time Effect on Switching
Frequency
VOUT IOUT ROFF
IOUT RON VOUT
tSW(MAX) 50ns 1
tOFF(MIN) is 50 ns. This imposes constraints on the maximum
V
IN
VOUT
that the FAN5361 can provide, or the maximum
w here:
VIN
output voltage it can provide at low VIN w hile maintaining a
fixed sw itching frequency in PWM mode.
ROFF
RON
=
RDSON _N DCRL
=
RDSON _P DCRL
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ApplicationsInformation
I2
12
2
Selecting the Inductor
(8)
IRMS
IOUT(DC)
The output inductor must meet both the required inductance
and the energy handling capability of the application. The
inductor value affects average current limit, the PWM-to-
PFM transition point, output voltage ripple, and efficiency.
The increased RMS current produces higher losses through
the RDS(ON) of the IC MOSFETs, as w ell as the inductor DCR.
Increasing the inductor value produces low er RMS currents,
but degrades transient response. For a given physical
inductor size, increased inductance usually results in an
inductor w ith low er saturation current and higher DCR.
The ripple current (∆I) of the regulator is:
VOUT
VIN
VIN VOUT
L fSW
I
(5)
Table 2 show s the effects of inductance higher or low er than
the recommended 470 nH on regulator performance.
The maximum average load current, IMAX(LOAD), is related to
the peak current limit, ILIM(PK) by the ripple current, given by:
Output Capacitor
I
2
Table 3 suggests 0402 capacitors. 0603 capacitors may
further improve performance in that the effective capacitance
is higher. This improves transient response and output ripple.
(6)
IMAX(LOAD) ILIM(PK)
The transition betw een PFM and PWM operation is
determined by the point at w hich the inductor valley current
crosses zero. The regulator DC current w hen the inductor
current crosses zero, IDCM, is:
Increasing COUT has no effect on loop stability and can
therefore be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ∆VOUT, is:
1
I
2
VOUT I
ESR
(7)
IDCM
(9)
8COUT fSW
The FAN5361 is optimized for operation w ith L = 470 nH, but
is stable w ith inductances up to 1.2 H (nominal). Up to
2.2 H(nominal) may be used; how ever, in that case, VIN must
be greater than or equal to 2.7 V. The inductor should be rated
Input Capacitor
The 2.2 F ceramic input capacitor should be placed as
close as possible betw een the VIN pin and GND to minimize
the parasitic inductance. If a long w ire is used to bring pow er
to the IC, additional “bulk” capacitance (electrolytic or
tantalum) should be placed betw een CIN and the pow er
source lead to reduce ringing that can occur betw een the
inductance of the pow er source leads and CIN.
to maintain at least 80% of its value at ILIM(PK)
.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical size
typically decreases the DCR; but since ∆I increases, the RMS
current increases, as do the core and skin effect losses.
The effective capacitance value decreases as VIN increases
due to DC bias effects.
Table 2. Effects of Changes in Inductor Value (from 470 nH Recommended Value) on Regulator Performance
Inductor Value
Increase
IMAX(LOAD)
Increase
Decrease
∆VOUT
Decrease
Increase
Transient Response
Degraded
Decrease
Improved
Table 3. Recommended Passive Components and their Variation Due to DC Bias
Component Description
Vendor
Min. Typ. Max.(6)
Comment
Murata LQM21PNR47MC0
Murata LQM21PNR54MG0
Hitachi Metals HSLI-201210AG-R47
470 nH, 2012,
L1
Minimum value occurs
at maximum current
300 nH 470 nH 520 nH
90 m,1.1 A
Murata or Equivalent
GRM155R60J225ME15
GRM188R60J225KE19D
Decrease primarily due
to DC bias (VIN) and
elevated temperature
2.2 F, 6.3 V,
C
1.0 F 2.2 F 2.4 F
1.6 F 4.7 F 5.2 F
IN
X5R, 0402
4.7 F, X5R,
Murata or Equivalent GRM155R60G475M
GRM155R60E475ME760
Decrease primarily due
COUT
0402
to DC bias (VOUT)
Note:
6. Higher inductance values are also acceptable. See “Selecting the Inductor” instructions in Applications Information.
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14
PCB LayoutGuidelines
There are only three external components: the inductor and
the input and output capacitors. For any buck sw itcher IC,
including the FAN5361, it is important to place a low -ESR
input capacitor very close to the IC, as show n in Figure 41.
The input capacitor ensures good input decoupling, w hich
helps reduce noise appearing at the output terminals and
ensures that the control sections of the IC do not behave
erratically due to excessive noise. This reduces sw itching
cycle jitter and ensures good overall performance. It is
important to place the common GND of CIN and COUT as close
as possible to the FAN5361 C2 terminal. There is some
flexibility in moving the inductor further aw ay from the IC; in
that case, VOUT should be considered at the COUT terminal.
VIN
A1
B1
A2
B2
CIN
C1 C2
470nH
GND
COUT
VOUT
Figure 41. PCB Layout Guidance
The table below pertains to the Marketing Outline Draw ing on the follow ing page.
Product-SpecificDimensions
Product
D
E
X
Y
FAN5361UCX
1.370 ±0.040
0.970 ±0.040
0.285
0.285
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15
PhysicalDimensions
F
0.03 C
E
A
2X
0.40
B
D
A1
BALL A1
INDEX AREA
(Ø0.20)
Bottom of Cu Pad
0.40
F
(Ø0.30)
Solder Mask
Opening
0.03 C
2X
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.06 C
0.378±0.018
0.208±0.021
0.05 C
0.586±0.039
E
SEATING PLANE
D
C
NOTES:
SIDE VIEWS
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
Ø0.260±0.010
6X
C. DIMENSIONS AND TOLERANCES PER
ASMEY14.5M, 2009.
0.40
0.005
C A B
D. DATUM C, THE SEATING PLANE IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
C
B
A
(Y) +/-0.018
F
E. PACKAGE TYPICAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
0.40
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
1
2
(X) +/-0.018
G. DRAWING FILENAME: UC006ACrev5.
BOTTOM VIEW
Figure 42. 6-Bump WLCSP, 0.4mm Pitch
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16
Physical Dimensions
0.10 C
2.0
A
2X
B
1.60
1.50
2.0
6
4
0.50
0.10 C
2X
1.10
1.40 2.40
PIN1
IDENT
TOP VIEW
1
3
0.30
0.55 MAX
0.10 C
0.65
(0.15)
C
RECOMMENDED LAND PATTERN
0.08 C
0.05
0.00
SEATING
PLANE
SIDE VIEW
NOTES:
1.50
MAX
A. OUTLINE BASED ON JEDEC REGISTRATION
MO-229, VARIATION VCCC.
PIN1
IDENT
1
3
B. DIMENSIONS ARE IN MILLIMETERS.
1.10
MAX
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
0.35
0.25
6x
D. DRAWING FILENAME: MKT-UMLP06Crev1
6
4
0.35
0.25
6x
0.65
1.30
0.10 C A B
0.05 C
BOTTOM VIEW
Figure 43. 6-Lead, 2 x 2 mm, Ultra-Thin Molded Leadless Package (UMLP)
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