FAN54020UCX_技术文档

Is Now Part of

To learn more about ON Semiconductor, please visit our website at

www.onsemi.com

Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers

will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor

product management systems do not have the ability to manage part nomenclature that utilizes an underscore

(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain

device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated

device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please

email any questions regarding the system integration to Fairchild_questions@onsemi.com.

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number

of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right

to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and speciﬁcally disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON

Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON

Semiconductor data sheets and/or speciﬁcations can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s

technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA

Class 3 medical devices or medical devices with a same or similar classiﬁcation in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its ofﬁcers, employees, subsidiaries, afﬁliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out

of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor

is an Equal Opportunity/Afﬁrmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

November 2014

FAN54020

USB-Compliant 1.5 A Single-Cell Li-Ion Switching Charger

with DBP and OTG Boost

Features

Description

.

Fully Integrated, High-Efficiency Charger for Single-

Cell Li-Ion and Li-Polymer Battery Packs

The FAN54020 combines a highly integrated switch-mode

charger, to minimize single-cell Li-Ion charging time from a

USB power source, and a boost regulator to power a USB

peripheral from the battery.

Faster Charging / Less Dissipation than Linear

Charger

The charging parameters and operating modes are

programmable through an I2C interface. The charger and

boost regulator switch at 3 MHz and utilize the same

external components to minimize size.

Charge Voltage Accuracy:

-

0.5% at 25°C

1% from -30°C to 125°C

The FAN54020 supports battery charging in three modes:

pre-charge, constant current fast charger, and constant

voltage float charge.

.

10% Charge Current Regulation Accuracy

28 V Absolute Maximum Input Voltage

1.5 A Maximum Charge Current

To ensure USB compliance and minimize charging time,

the input current limit can be changed via I2C by the host

Support for Dead Battery Provision ( DBP ) of

USB Battery Charging Specification 1.2

Programmable through I²C Interface with Fast Mode

(400 kHz) Compatibility

processor. Charge termination is determined by

a

.

programmable minimum current level. A safety timer with

reset control provides a safety back-up for the I2C host.

Charge status is reported to the host using the I2C port.

-

Input Current

The FAN54020 automatically restarts the charge cycle

when the battery falls below an internal threshold. Charge

current is reduced when die temperature reaches a

programmable level, preventing damage.

Fast-Charge / Termination Current

Charger (Float) Voltage

.

Safety Timer with Reset Control

The FAN54020 can operate as a boost regulator on

command from the system. The boost regulator includes a

soft-start that limits inrush current from the battery.

Dynamic Input Voltage Control Automatically

Reduces Charging Current with Weak Input Sources

.

Low Reverse Leakage Prevents Battery Drain to

V_BUS

The FAN54020 includes Dead Battery Provision (DBP)

from the BC1.2 specification, including a 30 minute timer.

.

Small Footprint 1H External Inductor

The FAN54020 is available in a 25-bump, 0.4 mm pitch,

Wafer-Level Chip-Scale Package (WLCSP).

3.3 V Regulated Output from V_BUSfor Auxiliary

Circuits

L1

VBUS

1F

SW

.

5 V, 500 mA Boost Mode for USB OTG for 3.0 to

4.5 V Battery Input

1H

C_OUT

C_BUS

PGND

CSIN

0.1F

Attachment Detect Protocol (ADP) Support per

On-The-Go and Embedded Host Supplement to the

USB Rev. 2.0 Specification

PMID

4.7F

R_SENSE

68m

C_MID

VBAT

LDO

SDA

SCL

DIS

FAN54020

C_BAT

10F

SYSTEM

LOAD

+

Applications

C_LDO

1F

Battery

ILIM

DBP

STAT

.

Cell Phones, Smart Phones

D+

Tablet, Portable Media Players

Gaming Device, Digital Cameras

POK_B

Figure 1.

Typical Application

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

Ordering Information

Part Number PN R0[4:3]

Temperature Range

Package

Packing Method

25-Bump, Wafer-Level Chip-Scale

(WLCSP), 0.4 mm Pitch

FAN54020UCX

01

-40 to 85°C

Tape and Reel

Block Diagram

PMID

Q3

C_MID

4.7F

VBUS

CHARGE

PUMP

LDO

SW

LDO 3.3

C_BUS

1F

C_LDO

1F

Q1

Q2

Q1A

Q1B

L1

1H

I_IN

CONTROL

VBUS

OVP

POWER

OUTPUT

STAGE

PWM

MODULATOR

C_OUT

0.1F

R_SENSE

ISNS

PGND

68m

DAC

VREF

+

CSIN

VBAT

PMID

Battery

SDA

SCL

(5)

C_SYS

PMID

I2C

INTERFACE

C_BAT

10F

SYSTEM

LOAD

OSC

ILIM

DBP

90mA

LOGIC

AND

CONTROL

STAT

D+

POK_B

DIS

Figure 2.

IC and System Block Diagram

Table 1. Recommended External Components

Component

Description

Vendor

Parameter Min. Typ.⁽¹⁾Unit

L

0.5

1.0

85

H

m

H

Charge Currents to 1 A:

1 H, 30%, 1.3 A, 2016

Murata: LQM2MPN1R0NG0L

DCR

L

L1

0.5

1.0

55

Charge Currents above 1 A:

1 H, 20%, 1.6 A, 2520

Murata: LQM2HPN1R0MG0

DCR

m

Murata GRM188R61E105K

TDK:C1608X5R1E105K

C_BUS

C_BAT

C_MID

C

0.5

3.7

2.0

1.0

10.0

4.7

1.0 F, 10%, 16 V, X5R, 0603

10 F, 20%, 6.3 V, X5R, 0603

4.7 F, 10%, 10 V, X5R, 0603

F

Murata: GRM188R60J106M

TDK: C1608X5R0J106M

Murata: GRM188R61A475K

TDK: C1608X5R1A475K

C_LDO

C_OUT

Murata GRM155R60J105M

Murata GRM033R60J104K

C

R

0.35

0.07

1.00

0.10

68

1.0 F, 10%, 6.3 V, X5R, 0402

0.1 F, 10%, 6.3 V, X5R, 0201

68 m, 1%, 0603, I_CHG< 900 mA

F

R_SENSE

Note:

m

1. Does not reflect effects of bias, tolerance, and temperature.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

2

VBUS

PMID

C_MID

4.7F

Q3

C_BUS

1F

Q1

Q2

Q1A

Q1B

CHARGE

PUMP

L1

SW

1H

C_OUT

0.1F

PGND

R_SENSE

CSIN

VBAT

68m

(5)

+

C_BAT

10F

C_SYS

SYSTEM

LOAD

Battery

Figure 3.

Power Output Stage

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

3

Pin Configuration

VBUS

STAT SDA

SCL

A5

B5

C5

D5

E5

A4

B4

C4

D4

E4

A3

B3

C3

D3

E3

A2

B2

C2

D2

E2

A1

B1

C1

D1

E1

A1

B1

C1

D1

A2

A3

B3

C3

D3

A4

PMID

B2

DIS

B4

D+

B5

SW

C2

AGND LDO

C4

C5

D5

PGND

D2

AGND

D4

CSIN VBAT DBP POK_B ILIM

E1

E2

E3

E4

E5

Bottom View

Top View

Figure 4.

WLCSP-25 Pin Assignments

Pin Definitions

Pin #

Name

Description

Charger Input Voltage. Bypass with a 1 F capacitor to PGND.

A1, A2

VBUS

Status/Interrupt. Open-drain output indicating charge status. The IC pulls this pin LOW when charge is in

process. It is high impedance when charging is done or the charger is disabled. It is also used as a

system interrupt. 128 s pulse, then high impedance indicates to the system that a fault has occurred.

A3

STAT

A4

A5

SDA I²C Interface Serial Data.

SCL I²C Interface Serial Clock.

Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense, and

high-voltage input switch. Bypass with a minimum of 4.7 F, 6.3 V capacitor to PGND.

B1-B3

B4

PMID

DIS Disable. When pulled HIGH, the charger is disabled. Internal pull-down resistor.

Connect to the USB connector D+ pin. Charger IC sources 0.6 V on this pin whenever the IC is charging

and the DBP pin is LOW. In all other conditions, the pin is tri-stated.

B5

D+

C1-C3

SW

Switching Node. Connect to the output inductor.

C4, D4, D5 AGND Analog Ground. All analog signals are referenced to this pin. This pin can be tied to PGND under the IC.

C5

LDO 3.3 V LDO. 3.3 V regulator output.

D1-D3

PGND Power Ground. Power return for gate drive and power transistors.

Current-Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to

sense current into the battery. Bypass this pin with a 0.1 F capacitor to PGND.

E1

CSIN

Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 10 F capacitor

E2

E3

E4

E5

VBAT

to PGND if the battery is separated from other system bypass capacitance by long traces.

DBP Dead Battery Provision Disable. Pull HIGH to disable charger D+ output. Internal pull–down resistor.

V_BUSPower OK Monitor. Open-drain output that is internally pulled LOW when VBUS is greater than the

POK_B

V_BUSvalidation threshold and lower than V_BUSOVP. It is high impedance when outside this range.

ILIM Input Current Limit. This pin sets the input current limit for t_30MINcharging. Internal pull-down resistor.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above

the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended

exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum

ratings are stress ratings only.

Symbol

Parameter

Min.

Max.

Unit

V_BUS

V_I

VBUS Voltage

-2⁽²⁾

-0.3

28

V

PMID, SW Voltage

Voltage on Other Pins

6.5

(3)

V_O

dV_BUS

dt

Maximum V_BUSSlope above 5.5 V when Boost or Charger are Active

4

V/s

Human Body Model per JESD22-A114 (All Pins)

1500

500

Electrostatic Discharge

ESD

Charged Device Model per JESD22-C101 (All Pins)

Protection Level

V

IEC 61000-4-2 System (VBUS and D+ Pin)

8000

T_J

T_STG

Junction Temperature

-40

-65

+150

+260

°C

Storage Temperature

T_L

Lead Soldering Temperature, 10 Seconds

Notes:

2. 5 s maximum pulse, non-repetitive, for V_BUSslew rates faster than -5 V/ms, resulting in -0.7 V>V_BUS>-2.0 V, applies only

for an open battery condition.

3. Lesser of 6.5 V or V_BAT+ 0.3 V.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating

conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend

exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Min.

(4)

Max.

Unit

V

V_BUS

Supply Voltage

7.5

4.5

4

V_BAT(MAX)Maximum Battery Voltage when Boost enabled

V

T_A< 60°C

T_A> 60°C

dV_BUS

dt

Negative V_BUSSlew Rate during VBUS Short Circuit,



V/s

C_MID< 4.7 F

2

T_A

T_J

Ambient Temperature

-30

+85

+120

°C

Junction Temperature (see Thermal Regulation Loop section)

Note:

4. Greater of V_BATor 4 V.

Thermal Properties

Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer

2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature

T_J(max)at a given ambient temperature T_A. For measured data, see Table 3.

Symbol

Parameter

Junction-to-Ambient Thermal Resistance

Junction-to-PCB Thermal Resistance

Typical

60

Unit

°C/W

_JA

_JB

20

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

5

Electrical Specifications

Unless otherwise specified: circuit of Figure 2, recommended operating temperature range for T_Jand T_A, V_BUS= 5.0 V,

DIS = 0, (Charger Mode operation); SCL, SDA = 0 or 1.8 V; typical values are for T_J= 25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Power Supplies

V_IN(MIN)1V_BUSInput Voltage Rising

V_IN(MIN)2Minimum V_BUS

To Initiate and Pass V_BUSValidation

While Charging

4.30

3.60

4.22

-3

4.40

3.70

4.32

4.50

3.80

4.42

+3

V

V_{BUS_REF}= 01 (Reg2 [3:2])

Other V_{BUS_REF}Codes (Reg2 [3:2])

V

V_{BUS_REF}V_BUSReg. Loop Threshold

t_{VBUS_VALID}V_BUSValidation Time

%

ms

32

22

V_BUS> V_{BUS_REF}, PWM Switching

mA

V_BUS> V_{BUS_REF}; V_BAT> V_OREG

I_BUSSetting = 100 mA

I_VBUS

V_BUSCurrent

2.0

0°C < T_J< 85°C, HZ_MODE = 1, I_REG= 0 A

188

250

5.0

µA

0°C < T_J< 85°C, V_BAT= 4.2 V, V_BUS=Open,

SDA = SCL = DIS = ILIM = DBP = 0 V,

STAT = POK_B = Float

Battery Discharge Current in

Sleep Mode

I_BAT

1.7

0°C < T_J< 85°C, V_BAT=4.2 V, V_BUS=0 V,

I_BUSLKGV_BATto V_BUSLeakage Current SDA = SCL = DIS = ILIM = DBP = 0 V,

STAT = POK_B = Float

0.01

1.00

µA

Charger Voltage Regulation

Charge Voltage Range

3.38

-0.5

-1.0

-1.5

4.44

+0.5

+1.0

+1.5

15

V

T_J= 25°C

V_OREG= 4.2 V,

I_BUSLIM=No Limit

Temp. Range

T_J= 25°C

V_OREG

Charge Voltage Accuracy

%

3.38 V < V_OREG< 4.44 V

Temp. Range

VBAT Overshoot⁽⁶

See Figure 5

)

10

mV

mA

Fast Charging Current Regulation

Output Charge Current Range

350

-10

1500

0

V_BAT< V_OREG, R_SENSE= 68 m

I_OCHARGESetting >

500 mA_MAX

-5

-7

I_OCHRG

Measured as V Across

R_SENSE[V_CSIN– V_BAT

Charge Current Accuracy

%

]

I_OCHARGESetting <

500 mA_MAX

-15

0

V_BATOvershoot Test

In Figure 5, I_OCHARGE= 1.5 A (1100), V_OREG= 4.2 V. I_LOADt_R= t_F= 1 s. Charge current prior to load transient =

20mV

. Overshoot is measured as the peak voltage above V_BATlevel prior to the load transient application.

 100mA

200m

VBAT

(5)

C_SYS

C_BAT

10F

FAN54020

200m

ESR

I_LOAD

1.5A

+

V_CELL

4.18V

BATTERY MODEL

Figure 5.

V_BATOvershoot Test Conditions

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

6

Electrical Specifications

Unless otherwise specified: circuit of Figure 2, recommended operating temperature range for T_Jand T_A, V_BUS= 5.0 V,

DIS = 0, (Charger Mode operation); SCL, SDA = 0 or 1.8 V; typical values are for T_J= 25°C.

Symbol

Parameter

Conditions

Min.

Typ. Max.

Unit

Charge Termination Detection

V_BAT> V_OREG– V_RCH, V_BUS> V_{BUS_REF}

R_SENSE=68 m

Termination Current Range

50

425

mA

[V_CSIN– V_BAT] from 3 mV to 10.2 mV

[V_CSIN– V_BAT] from 10.2 mV to 20.4 mV

[V_CSIN– V_BAT] > 20.4 mV

-25

-10

-5

+25

I_(TERM)

Termination Current Accuracy

+10

%

+5

Termination Current Deglitch Time 2 mV Overdrive

Input Current Limit

Input Current Limit Threshold

Includes I_LDO

Logic Levels: DIS, SDA, SCL, ILIM, DBP

32

ms

I_BUSSet to 100 mA

I_BUSSet to 500 mA

87

93

100

500

I_BUSLIM

mA

450

475

V_IH

V_IL

I_IN

High-Level Input Voltage

Low-Level Input Voltage

Input Bias Current

1.05

V

0.4

Input Tied to GND or VBUS

0.01

1.00

A

ILIM, DBP, DIS Pull-Down

Resistance

R_PD

0.65

3.20

1.40

M

3.3 V Linear Regulator

V_LDO

3.3 V Regulator Output

LDO Quiescent Current

I_LDOfrom 0 to 40 mA

V_BAT= 3.6 V

3.30

125

3.47

V

I_{LDO_IN}

A

I_LDO= 40 mA, V_BUS= 0 V,

V_{LDO_IN}= V_BAT

V_{LDO_IN(MIN)}LDO Drop-Out Voltage

t_3.3Regulator Startup Time

Battery Recharge Threshold

270

4.5

330

5.0

mV

ms

V_BUS>V_IN(MIN)1, DBP=0 or LDO_OFF

(Reg2[4]) =1

Recharge Threshold⁽⁶⁾

Below V_OREG

120

132

mV

V_RCH

Deglitch Time

V_BATFalling below V_RCHThreshold

ms

D+ Output

V_{DBP_SRC}

I_{DBP_OFF}

Voltage on D+

0.51

-1

0.64

0.69

+1

V

DBP = 0, I_LOADon D+ from 0 to 250 A

Leakage Current

DBP = 1, V_D+from 0 to 5 V

A

STAT and POK_B Output

V_STAT(OL)STAT and POK_B Output Low

I_STAT= 10 mA

V_STAT= 5 V

0.4

1

V

STAT and POK_B High Leakage

Current

I_STAT(OH)

A

Power Switches (see Figure 3)

Q3 On Resistance (VBUS to PMID) I_IN(LIMIT)> 500 mA

160

110

220

160

170

R_DS(ON)

Q1 On Resistance (PMID to SW)

Q2 On Resistance (SW to GND)

mΩ

Continued on the following page…

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

7

Electrical Specifications (Continued)

Unless otherwise specified: circuit of Figure 2, recommended operating temperature range for T_Jand T_A, V_BUS= 5.0 V,

DIS = 0, (Charger Mode operation); SCL, SDA = 0 or 1.8 V; typical values are for T_J= 25°C.

Symbol

Parameter

Conditions

Min. Typ. Max.

Unit

Charger PWM Modulator

f_SW

Oscillator Frequency

2.7

3.0

3.3

MHz

%

D_MAX

D_MIN

Maximum Duty Cycle

Minimum Duty Cycle

100

0

%

Synchronous to Non-Synchronous Low-Side MOSFET (Q2) Cycle-by-

I_SYNC

180

mA

Current Cut-Off Threshold

Cycle Current Limit

VBUS Load Resistance

Normal Operation

1500

100

R_VBUS

VBUS to PGND Resistance



During V_BUSValidation

Protection and Timers

V_BUSOVP Accuracy

V_BUSRising

-5

+5

%

mV

V

VBUS_OVP

V_SHORT

Hysteresis

V_BUSFalling

140

2.24

160

6.00

5.75

90

Battery Short-Circuit Threshold

Hysteresis

V_BATRising

2.15

2.36

6.25

100

V_BATFalling

mV

V_BUSRising

5.80

5.50

80

V_BUSVoltage above which the I_BUS

Limit is Disabled

V_IBUS(DIS)

V

V_BUSFalling

I_SHORT

Linear Charging Current

V_BAT< V_SHORT

mA

A

I_LIMPK(CHG)

Q1 Cycle-by-Cycle I_PEAKLimit

Thermal Shutdown Threshold⁽⁶⁾

Re-Enable Threshold⁽⁶⁾

Charge or PTM Mode

T_JRising

3.3

3.8

145

T_CF

°C

s

T_SHUTDWN

T_CF

T_JFalling

Thermal Regulation Accuracy⁽⁶⁾

Relative to T_CFSetting

Charger Enabled, Boost Disabled

Charger Disabled, Boost Enabled

-10

20.5

17.0

30

+10

28.0

31.6

45

24.3

38

t_32S

32-Second Timer

s

t_30MIN

t_osc

30-Minute Timer

Min

Charge or ADP Probe

-10

10

Internal Oscillator Tolerance

%

A

Boost and ADP_Detect Modes

-30

30

Production Test Mode

20% Duty with Max. Period 10 ms,

V_BUS= 5.5 V, V_OREG< 4.2 V

I_BAT(PTM)

Production Test Output Current⁽⁶⁾

2.3

ADP Circuit (see Figure 49)

I_SRC

I_SINK

ADP Probe Source Current

ADP Probe Sink Current

V_BUS> V₇₀₀

1.20

1.15

75

1.40

1.55

100

700

600

450

290

150

60

1.60

1.95

125

750

630

510

350

mA

mV

V_BUS> V₁₀₀, ADP_SNS = 0

V₁₀₀

Lower ADP Comparator Threshold ADP_SNS = 0

V₇₀₀

700 mV ADP Threshold

V₇₀₀– V₁₀₀

650

570

390

230

100

dV_ADP

V_BUSRising

mV

ADP Sense Threshold,

ADP_SNS = 1

V_SENSE

V_BUSFalling

Hysteresis

I_REFRESH

t_REFRESH

Battery Current during Refresh

A

RDVBUS Set to STAT Pulse

1

ms

Continued on the following page…

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

8

Electrical Specifications (Continued)

Unless otherwise specified: circuit of Figure 2, recommended operating temperature range for T_Jand T_A, V_BUS= 5.0 V,

DIS = 0, (Charger Mode operation); SCL, SDA = 0 or 1.8 V; typical values are for T_J= 25°C.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Boost Mode Operation

2.5 V < V_BAT< 4.5 V,

I_LOADfrom 0 to 200 mA

4.80

4.77

5.07

300

0.5

5.17

450

V_BOOST

Boost Output Voltage at VBUS

V

3.0 V < V_BAT< 4.5 V,

I_LOADfrom 0 to 500 mA

PFM Mode, V_BAT=3.6 V, I_OUT= 0,

LDO On with No Load

I_BAT(BOOST)Boost Mode Quiescent Current

A

To within 2% of V_BOOSTFinal Value,

I_LOAD< 200 mA, C_BUS< 15 F

t_REG(BST)

Boost Startup Time⁽⁶⁾

Q2 Peak Current Limit

2.0

ms

mA

V

I_LIMPK(BST)

1350

1550

2.32

2.48

1950

While Boost Active

Minimum Battery Voltage for Boost

Operation

UVLO_BST

To Start Boost Regulator

2.70

Notes:

5. C_BATis placed as close to the charger IC as possible. An additional 30 F of distributed system capacitance (C_SYS) is

parallel with CBAT, but is located further from the IC.

6. Guaranteed by design; not tested in production.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

9

I²C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Standard Mode

Min. Typ. Max. Unit

100

Fast Mode

400

kHz

f_SCL

SCL Clock Frequency

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

3400

1700

4.7

Bus-Free Time between STOP and

START Conditions

t_BUF

s

Fast Mode

1.3

Standard Mode

4

s

t_HD;STA

START or Repeated START Hold Time

SCL LOW Period

Fast Mode

600

160

4.7

1.3

160

320

4

ns

High-Speed Mode

Standard Mode

s

Fast Mode

t_LOW

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

ns

s

Fast Mode

600

60

t_HIGH

SCL HIGH Period

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

ns

120

4.7

600

160

250

100

10

s

t_SU;STA

Repeated START Setup Time

Data Setup Time

Fast Mode

ns

High-Speed Mode

Standard Mode

t_SU;DAT

Fast Mode

ns

s

ns

High-Speed Mode

Standard Mode

0

3.45

900

70

Fast Mode

t_HD;DAT

Data Hold Time

SCL Rise Time

SCL Fall Time

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

150

1000

300

80

20+0.1C_B

10

Fast Mode

t_RCL

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

20

160

300

40

20+0.1C_B

10

Fast Mode

t_FCL

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

20

80

20+0.1C_B

10

1000

300

80

SDA Rise Time

Rise Time of SCL after a Repeated

START Condition and after ACK Bit

Fast Mode

t_RDA

t_RCL1

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

20

160

Continued on the following page…

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

10

I²C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Standard Mode

Min. Typ. Max. Unit

20+0.1C_B

300

80

Fast Mode

20+0.1C_B

t_FDA

SDA Fall Time

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

10

20

160

4

s

ns

pF

t_SU;STO

Stop Condition Setup Time

Fast Mode

600

160

High-Speed Mode

C_B

Capacitive Load for SDA, SCL

400

Timing Diagrams

t_F

t_SU;STA

t_BUF

SDA

t_R

T_SU;DAT

t_HD;STO

t_HIGH

t_HD;DAT

SCL

t_LOW

t_HD;STA

REPEATED

START

STOP

START

Figure 6.

I²C Interface Timing for Fast and Slow Modes

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

11

Charge Mode Typical Performance Characteristics

Unless otherwise specified, using circuit of Figure 2, V_OREG=4.24 V, V_BUS=5.0 V, DIS=0, SCL=SDA=1.8 V, LDO no load, and

T_A=25^°C.

100

95

90

85

80

75

100

95

90

85

80

75

I CHRG=350mA

I CHRG=900mA

I CHRG=1500mA

4.5 VBUS

5.0 VBUS

5.5 VBUS

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

300

600

900

1200

1500

Battery Voltage, VBAT (V)

Charge Current Setpoint, IBAT (mA)

Figure 7.

Efficiency vs. Battery Voltage Over-I_CHRG

Range

Figure 8.

Efficiency vs. I_CHRGOver-V_BUSRange

180

160

140

120

100

10

8

4.5 VBUS

5.0 VBUS

5.5 VBUS

6

4

- 30C

+25C

+85C

2

80

0

2

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

2.5

3

3.5

4

4.5

5

Battery Voltage, VBAT (V)

Figure 9.

HZ/Sleep Mode Battery Discharge Current,

SDA=SCL=1.8 V, DIS=DBP=0

Figure 10. Charge Current vs. Battery Voltage,

I_BUSLIM=100 mA

900

800

700

600

500

1,600

4.5 VBUS

5.0 VBUS

5.5 VBUS

4.5 VBUS

5.0 VBUS

1,400

5.5 VBUS

1,200

1,000

800

400

2.7

600

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

Battery Voltage, VBAT (V)

Figure 11. Charge Current vs. Battery Voltage,

I_BUSLIM=500 mA

Figure 12. Charge Current vs. Battery Voltage,

I_BUSLIM=900 mA

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

12

Charge Mode Typical Performance Characteristics

Unless otherwise specified, using circuit of Figure 2, V_OREG=4.24 V, V_BUS=5.0 V, DIS=0, SCL=SDA=1.8 V, LDO no load, and

T_A=25^°C.

1,600

1,400

1,200

1,000

800

3.5

3.4

3.3

3.2

3.1

3.0

V BUS_REF = 4.48V

V BUS_REF = 4.32V

4.5 VBUS

5.0 VBUS

5.5 VBUS

600

0

20

40

60

80

100

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

LDO Load Current (mA)

Battery Voltage, VBAT (V)

Figure 13. Charge Current vs. Battery Voltage, 5.2 V_BUS

,

Figure 14. LDO Regulation vs. Load Over-V_BUSRange,

4.2 V_BAT

1 A Source Limited

Figure 15. Charger Startup at V_BUSPlug-In, 3.2 V_BAT,

Figure 16. Charger Startup at V_BUSPlug-In, 3.2 V_BAT,

ILIM=DBP=0, 1 k LDO Load

ILIM=1, DBP=0, 1 k LDO Load

Figure 17. Charger Startup at HZ Bit Reset, 3.7 V_BAT

,

Figure 18. Charger Startup at V_BUSPlug-In, Dead Battery_,

ILIM=DBP=1, 1 k LDO Load, I_CHRG=1.0 A

ILIM=DBP=0, 1 k LDO Load

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

13

Charge Mode Typical Performance Characteristics

Unless otherwise specified, using circuit of Figure 2, V_OREG=4.24 V, V_BUS=5.0 V, DIS=0, SCL=SDA=1.8 V, LDO no load, and

T_A=25^°C.

Figure 19. Charger Startup at V_BUSPlug-In, No Battery_,

Figure 20. V_BUSOVP Response while Charging,

5-9-5 V_BUS, 3.7 V_BAT,I_BUSLIM=500 mA, I_CHRG=1.0 A

ILIM=DBP=0, 300  LDO Load

Figure 21. Battery Removal/Insertion while Charging,

TE_DIS=1, 3.7 V_BAT,1 k LDO Load, I_BUSLIM=500 mA,

I_CHRG=1.0 A

Figure 22. Battery Removal/Insertion while Charging,

TE_DIS=0, 3.7 V_BAT,1 k LDO Load, I_BUSLIM=500 mA,

I_CHRG=1.0 A

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

14

Charge Mode Typical Performance Characteristics

Unless otherwise specified, using circuit of Figure 2, V_OREG=4.24 V, V_BUS=5.0 V, DIS=0, SCL=SDA=1.8 V, LDO no load, and

T_A=25^°C.

Figure 23. GSM Pulse (2 A Step, t_R/t_F=5 s) Response,

3.9 V_BAT,1 k LDO Load, I_BUSLIM=500 mA, I_CHRG=1.0 A

Figure 24. GSM Pulse (2 A Step, t_R/t_F=5 s) Response,

3.9 V_BAT,1 k LDO Load, I_BUSLIM=No Limit, I_CHRG=1.0 A,

500 mA V_BUSSource Limited

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

15

Boost Mode Typical Characteristics

Unless otherwise specified, using circuit of Figure 2 V_BAT=3.6 V, DIS=0, SCL=SDA=1.8 V, LDO no load, T_A=25°C.

100

95

90

85

80

75

95

90

85

80

75

- 30C

+ 25C

+ 85C

2.7 VBAT

3.6 VBAT

4.2 VBAT

0

100

200

300

400

500

0

100

200

300

400

500

VBUS Load Current (mA)

Figure 25.

Efficiency vs. Load Current Over-Input

Voltage (V_BAT) Range

Figure 26.

Efficiency vs. Load Current

Over-Temperature Range, 3.6 V_BAT

5.15

5.10

5.05

5.00

4.95

4.90

60

50

40

30

20

10

0

2.7 VBAT

3.6 VBAT

4.2 VBAT

2.7 VBAT

3.6 VBAT

4.2 VBAT

4.85

0

100

200

300

400

500

0

100

200

300

400

500

VBUS Load Current (mA)

Figure 27.

Output Regulation vs. Load Current

Figure 28.

Output Ripple vs. Load Current Over-Input

Voltage (V_BAT) Range

Over- Input Voltage (V_BAT) Range

500

450

400

350

300

250

200

1,000

900

800

700

600

500

- 30C

+25C

+85C

- 30C

+25C

+85C

400

2

2.5

3

3.5

4

4.5

5

2

2.5

3

3.5

4

4.5

5

Battery Voltage, VBAT (V)

Figure 29.

OTG / Boost Quiescent Current vs. Input

Voltage (V_BAT) Over-Temperature

Figure 30.

OTG / Boost DC Load Current Limit

Threshold vs. Input Voltage (V_BAT) Over-Temperature

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

16

Boost Mode Typical Characteristics

Unless otherwise specified, using circuit of Figure 2 V_BAT=3.6 V, DIS=0, SCL=SDA=1.8 V, LDO no load, T_A=25°C.

Figure 32.

V_BUSOutput Fault Response

Figure 31.

Startup, 50  Load, Additional 10 F

on V_BUS

Figure 33.

Line Transient Response, 50  Load,

3.9-3.3-3.9 V_BAT, t_R/t_F=10 s

Figure 34.

Load Transient Response, 50-300-50 mA,

t_R/t_F=100 ns

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

17

Operation and Applications Description

The FAN54020 is

a USB-compliant single-cell Li-Ion

VBUS_CON

switching charger with support for dead battery provision

(DBP) within the BC1.2 specification, including a 30-minute

timer that cannot exceed 45 minutes. The maximum charge

current is rated at 1.5 A. The FAN54020 is designed to be

stable with space-saving ceramic capacitors.

The VBUS_CON bit is set after V_BUSrises above V_BATand

V_INMIN1(4.4 V)⁽⁷⁾.

As soon as V_BUSfalls below either V_IN(MIN)2(3.7 V) or V_BAT

,

the IC turns off the charger and applies 50 mA to VBUS for

66 ms. If V_BUSis below V_BATor 3.7 V at the end of this

period, VBUS_CON is reset.

Charging Stages

Figure 35 shows the different stages of Li+ charging when a

charger is connected to the USB pins and a battery is

present and discharged below 2.25 V. Generally, the

prequalification (called “PRE-CHARGE” in Figure 35) stage

is when the battery voltage is below 2.25 V when an I_SHORT

current of 90 mA charges the battery to V_SHORTvoltage of

2.25 V. Then Fast Charge starts if a battery is detected and

the current is increased considerably to a programmable

I_OCHARGElevel (“CURRENT REGULATION” in the figure).

The battery voltage climbs quickly based on the drop caused

by the current across the load elements of the battery. Then

the voltage climbs linearly until the constant voltage stage is

reached at the programmable voltage of V_OREG. The current

is monitored during this stage (“VOLTAGE REGULATION” in

The STAT pin pulses whenever the VBUS_CON bit changes

from HIGH to LOW. For VBUS_CON LOW to HIGH, the

STAT pulse occurs per timing in Figure 37 or Figure 38,

depending on whether or not charge or HZ state is entered

after VBUS is connected.

Note:

7. If V_BUSis above V_INMIN2(3.7 V), but below V_INMIN1(4.4 V);

VBUS_CON is set for 132 ms. POK_B also pulses LOW

for 132 ms.

4.4V

VBUS

3.3V

the figure) and, when it reaches the end of current I_TERM

,

charging stops.

Figure 36 shows the charge stages using a switching

charger when the input power of the charging source is

limited by the IC. During current regulation, as V_BATrises,

charge current decreases because input power is limited.

LDO

STAT

POK_B

V_OREG

VBUS_CON

I_CHARGE

load_vbat

256ms

I_OCHARGE

T

4ms

V ^BA

32ms

load_vbus

32ms

SLEEP DEBOUNCE SYS_CAP DISCHARGE VBUS_VAL WAIT

VBUS_POR

CHARGE

STATE

I_TERM

V_SHORT

Figure 37.

VBUS Plug-in Timing: Battery Present,

DBP=1, DIS = 0, HZ_MODE = 0

I_SHORT

4.4V

PRE-

CHARGE

CURRENT REGULATION

VOLTAGE

REGULATION

VBUS

3.3V

Figure 35.

Typical Charging Profile

V

OREG

LDO

STAT

POK_B

VBUS_CON

I_TERM

HZ_MODE

V

SHORT

I_SHORT

load_vbat

load_vbus

32ms

4ms

32ms

SLEEP DEBOUNCE

VBUS_POR

HZ_STATE

VBUS_VAL WAIT

CHARGE

STATE

PRE-

CHARGE

CURRENT REGULATION

VOLTAGE

REGULATION

Figure 38.

VBUS Plug-in Timing from HZ_MODE:

Battery Present, DBP = 1

Figure 36.

Charge Curve, I_INLIMLimits I_CHARGE

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

18

VBUS POR and DBP (see Figure 37)

LDO

When the IC detects that V_BUShas risen above V_IN(MIN)1

(4.4 V), Q3’s charge pump turns on. If V_BUSremains above

this threshold for 16 ms, the IC then applies a 1 mA load to

VBAT for 256 ms to ensure that, if the battery was removed

or its discharge protection switch is open, the system

capacitors across VBAT will be discharged below the

V_SHORTthreshold.

The FAN54020 contains a 3.3 V LDO available to provide

power to the USB PHY. By default, the LDO is enabled and

biased from VBAT when DBP is HIGH and V_BUS< V_BAT

.

When V_BUS> V_BAT, the LDO is biased from VBUS. If DBP is

LOW, the LDO is only biased from VBUS and off when V_BUS

< V_IN(MIN)1. When the LDO_OFF bit (Reg02[4]) is raised, the

LDO is biased from VBUS and off when V_BUS< V_IN(MIN)1

.

V_BUSvalidation is then performed to ensure a valid charging

source. Validation occurs with a 50 mA load on VBUS. To

pass validation, V_BUSmust remain above VIN(MIN)1 and below

VBUSOVP for tVBUS_VALID (32 ms) before the IC initiates

charging. If V_BUSfails validation; the load is removed, the

VALIDATION FAIL bit is set, and validation is attempted

every two seconds.

Pre-Charging Stage

A typical battery has a protection circuit within the battery

pack to prevent further discharge if its cell voltage falls below

2.25 V. This causes V_BATto decay quickly to ground since all

that is holding V_BATup is the external decoupling capacitors.

Another way V_BATcan get so low is if VBAT is shorted to

ground accidentally. Both are very rare in a typical system

because a dead battery is typically above 3 V and only goes

below 3 V via leakage over a long period of time.

Once V_BUSis validated; VBUS_CON (Reg7[7]) is set, POK_B

pulls low, and the STAT pin pulses to indicate to the system

that VBUS is connected. This point is considered to be

VBUS_POR.

When V_BUS> V_BAT, the IC takes its power from VBUS while

monitoring VBAT to determine the optimal charging profile.

If V_BUSfails validation, the POK_B pin and bit (Reg7[6]) are

raised and the STAT pin pulsed to indicate a V_BUSfault. V_BUS

validation is subsequently re-tried every two seconds.

Setting HZ_MODE or DIS prevents periodic re-validation.

V_BUSvalidation is also performed prior to entering CHARGE

state from any state where the charger is off.

At VBUS POR, the IC operates in accordance with its I²C

register settings as long as the DBP pin is HIGH. If the DBP

pin is LOW, the IC sets all registers to their default values

and the I_BUScurrent is controlled by the ILIM pin, with

If V_BATis below 2.25 V, a charging current of 90 mA is used

to trickle charge the battery. If it is not a short circuit, V_BAT

should recover very quickly above 2.25 V since it is only

charging decoupling capacitors. If there is a short circuit, the

timer continues up to 30 minutes and expires, shutting down

the charger. This limits the short-circuit current of 90 mA to

be drawn only for 30 minutes. The only way to recover from

this fault is to remove the short circuit. If the short circuit is

not removed, detaching and re-attaching the charger restarts

the dead battery provision timer for another 30 minutes

before shutting off again.

IBUS_(MAX)= 100 mA when ILIM is LOW and IBUS_(MAX)

=

500 mA when ILIM is HIGH. Once DBP returns HIGH, D+ is

tri-stated and charge parameters may be programmed by

the host. IBUS_(MAX)remains controlled by the state of the

ILIM pin until the first I²C write occurs; at which time,

IBUS_(MAX)is controlled by the I_BUSregister bits (Reg5). The

first I²C write after DBP rises stops the t_30MINtimer and starts

the 32-second timer (t_32S).

Battery Absent / Present Response

The FAN54020 detects if the battery is absent if V_BATis

below 2.25 V at the start of charging. To accomplish this, the

IC raises V_OREGto 4.0 V for up to 128 ms after V_BATis above

2.25 V. After 64 ms, V_BATis compared to 3.7 V. If V_BATrises

above 3.7 V at any time in that 64 ms period, the battery is

assumed to be absent (see Figure 39).

BC1.2 and USB 2.0 allow a portable device (defined as a

device with a battery) with a dead battery to take a maximum

of 100 mA from the USB VBUS line for a maximum of 45

minutes as long as the portable device forces the D+ line to

0.6 V typical.

If battery absence is detected; all registers are reset, the

NOBAT bit is set, an interrupt generated, and V_OREGreverts

to its default value of 3.54 V. The charger continues to

provide power to the system with STAT HIGH in DBP Mode

until otherwise instructed through I²C commands. This allows

the host processor an opportunity to detect charger type and

negotiate with the USB host for higher current.

If the DBP pin is LOW at VBUS POR or transitions from

HIGH to LOW when VBUS is valid, the FAN54020:

1. Resets its registers to default values;

2. Starts the t_30MINtimer;

The IC continues to provide current, provided that:

1. A timer (T_30MINor T_32S) is running; and

2. HZ_MODE = 0 and DIS = 0.

3. Charges with its input current limit set by the state of the

ILIM pin as described above; and

The current drawn from VBUS is determined by the state of

the ILIM pin and the I_OCHARGEsettings.

4. Sources 0.6 V to the D+ pin.

Both ILIM and DBP are internally pulled down and there is

typically nothing to force them HIGH at this point due to the

processor/system not being awake. When t_30MINexpires, the

FAN54020 removes the 0.6 V from D+ and stops charging.

The D+ pin is also tri-stated when DBP is HIGH.

Once the initial battery absence test is performed, the only

other battery absent test performed occurs if ITERM_DIS = 0

and the charge current drops below the ITERM setting.

After a t_30MINtimer expiration, charging may only be restarted

after a new VBUS POR.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

19

The NOBAT bit is reset only if one of the battery absent /

present tests is performed with battery presence detected or

after a VBUS POR with the battery present.

Constant Current / Constant Voltage Charging

In this stage, V_BATis above the pre-qualification voltage of

2.25 V, but below V_OREG. At a certain V_BATlevel, the system

begins a low-level software boot sequence and uses the

USB PHY to determine if a Dedicated Charging Port (DCP),

Charging Downstream Port (CDP), or a typical PC host (a

Standard Downstream Port (SDP)) is connected. The result

of the interrogation determines how much current the

FAN54020 can draw and remain USB compliant.

If V_BATfalls to 140 mV below V_OREG, the Fast Charge

charging cycle starts again, if VRCH_DIS = 0. A recharge

condition debounce time of 132 ms is used to prevent

transient battery load currents (such as GSM current pulses)

from triggering recharge unnecessarily.

For SDP and CDP, enumeration is required. After

enumeration, the system can raise the ILIM pin to increase

charge current to 500 mA or the host can use the I²C bus to

program the charge current via the I_OCHARGEbits in IBAT

(REG3[7:4]).

4.0V

3.7V

3.54V

2.25V

VBAT

2ms

64ms

STAT

POK_B

NOBAT

After DBP transitions from LOW to HIGH, writing to any

register through I²C stops and resets the t_30MINtimer, which

in turn enables the 32-second timer (t_32S). As long as t_32Sis

enabled, charge current is controlled by I²C register settings.

32ms

VBUS_VAL ISHORT

BATT DETECT

CHARGE

STATE

VBUS_POR

If the t_32Stimer subsequently expires, charging stops and the

IC enters IDLE state (see Figure 42). To continue charging

when t_32Sis enabled, the host must reset the t_32Stimer by

periodically setting the TMR_RST bit (Reg0A[7]). Once the

IDLE state is entered; charging can resume only after VBUS

is disconnected and reconnected, the DBP pin is lowered, or

a new I²C write starts the t_32Stimer.

Figure 39.

Battery Absent After VBUS POR

VBUS POR

The constant voltage, V_OREG, threshold is also expected to

be set based on battery type and battery temperature, which

should be monitored by the processor via separate controls.

Thermal regulation within the FAN54020 may have little

correlation to the battery temperature since the heat

dissipation of the PCB that the FAN54020 is soldered to may

be completely different from the heat dissipation within the

battery pack.

HZ_MODE

or DIS = 1

YES

HZ State

NO

DBP = 0

YES

Charge Termination and Recharge

NO

Start T_32SEC

When V_BATreaches V_OREG(Reg4[5:0]), the current charging

the battery is reduced, limited by the battery’s ESR and its

internal cell voltage. Charging continues until the I_BAT< I_TERM

(set by Reg3[3:0] bits) threshold is crossed. If ITERM_DIS =

0, charging stops (charge termination), and t_32Sstops.

Reset all registers,

D+ = 0.6V,

After charge termination, a small load is placed across VBAT

for 132 ms. The battery is presumed absent if V_BATstays

below V_RCH(140 mV below V_OREG) for the next 132 ms. The

NOBAT bit is then set and the NOBAT Fault state is entered

(see Figure 46). The charger restarts after two seconds and:

Start T_30MIN

Charge State

1. If V_BAT< V_SHORT, a battery absent/present test described

in Figure 39 is performed;

Figure 40.

VBUS_POR Flow Chart

OR

2. If V_BAT> V_SHORT, PWM charging resumes.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

20

HZ State

VBUS

Fault State

D+ = OPEN

Disable Charger,

Enunciate Fault

Stop timers

NO

YES

DISABLE

HIGH

VBUS <

VBAT

VBUS

OK?

NO

LOW

YES

DBP

HZ_MODE

=1

SLEEP

HZ or

DISABLE Pin

set?

LOW

NO

Charge State

NO

Reset all registers,

Start T30MIN

Start T32S timer

YES

Charge State

HZ STATE

Figure 43.

VBUS Fault State Flow Chart

Figure 41.

HZ State Flow Chart

IDLE State

D+ = OPEN

Reset All

Registers

NO

DBP

YES

T32Sec

Armed?

YES

DIS or

HZ_MODE =

1?

Reset all registers,

Arm T_30MIN

HZ STATE

YES

NO

Charge State

Figure 42.

IDLE State Flow Chart

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

21

CHARGE STATE

VBUS Fault State

NO

90mA charging

D+ = 0.6V

YES

V_BAT< V_SHORT

VBUS OK?

NO

YES

D+ = 0.6V

I_BUS

T_30MIN

VBUS OK?

DBP = 0?

NO

YES

per ILIM pin

Timeout?

NO

T_32SEC

YES

NO

D+ = OPEN

Enabled?

VBUS Fault State

YES

TIMER FAULT

Stop Charging

D+ = OPEN

T_32SEC

YES

Timeout?

I_CHG< I_TERM

AND

CHARGE Per

NO

register settings

D+ = OPEN

ITERM_DIS = 0 ?

IDLE STATE

YES

Battery

CHARGE DONE

STATE

VBUS OK?

YES

Present?

NO

NOBAT

Fault State

VBUS Fault State

Figure 44.

Charge State Flow Chart

Note:

8. If HZ_MODE is set, or DIS = 1, Charge State exits to HZ State.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

22

Production Test Mode

Production Test Mode (PTM) provides power for the system

from the USB port.

CHARGE

DONE

PTM is enabled when the PTM_EN bit is HIGH and the

battery is absent (NOBAT = 1). Only the OREG loop is active

and V_OREGmust be programmed by the user. The 32second

timer (T_32S) is stooped during PTM.

Disable Charger

During PTM, high-current pulses (load currents greater than

1.5 A) must be limited to 20% duty cycle with a minimum

period of 10 ms. A 50 mA minimum DC load is required.

VBAT >

VRCH

NO

Charge State

STAT Pin and Interrupts

YES

The STAT pin is used to indicate charging status, as well as

to signal the host processor of a change in the status of the

IC or system. The STAT pin emits a 125 s low-going pulse

whenever an unmasked interrupt event occurs (see Reg6 –

Reg7). The static state of the STAT pin is determined by

whether the IC is charging a battery:

YES

VBUS OK?

NO

VBUS Fault State

Table 2. STAT Pin Static State

CHARGER

NOBAT Bit

STAT Pin

Figure 45.

Charge Done State Flow Chart

ON

OFF

X

0

X

1

0

1

NOBAT

Fault State

Any interrupt pulse that occurs while STAT was statically

LOW is preceded by a 125 s STAT HIGH pulse, as shown

in Figure 47.

Enunciate NOBAT fault,

Reset all but ITERM_DIS

Start T_2SEC

Charging

Interrupt (stops charging)

STAT

Charging

Interrupt (charging resumes)

VBUS

OK?

VBUS Fault

STATE

Figure 47.

STAT Interrupt Pulse Behavior

NO

If the condition causing the interrupt also causes the charger

to stop charging (for example, a Timer fault (TC_TO)), STAT

remains HIGH after the 125 s low-going pulse. If charging

continues after the interrupt (as with TREG_FLAG interrupt),

STAT goes HIGH for 125 s after the 125 s low-going

pulse, then returns LOW.

NO

YES

T2SEC

Done?

When bits in the INTERRUPT or STATUS register are set, if

the corresponding MASK bit is reset, the INTERRUPT bit

(Reg1[0]) is set before the falling edge of STAT, which

enunciates the interrupt. The INTERRUPT bit is cleared

when the host reads Reg1. For an interrupt to be enunciated

by the STAT pin, the following conditions must ALL be true:

YES

HZ or

DISABLE Pin

set?

YES

HZ STATE

1. An interrupt condition occurs, which sets an interrupt bit

in INTERRUPT or STATUS registers; and

2. The corresponding mask bit = 0; and

3. The INTERRUPT bit (Reg1[0]) = 0.

NO

If additional interrupt conditions occur before the host

clears the INTERRUPT bit by reading Reg1, the STAT pin

does not pulse.

Charge State

Figure 46.

NOBAT Fault State Flow Chart

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

23

OVP and VBUS_IN Regulation

Safety Registers

The FAN54020 contains programmable over-voltage

protection (OVP) on VBUS, ranging from 6.5 V to 8.0 V, as

specified in the V_BUSOVPbits (Reg1[2:1), with the default

setting of 7 V. If OVP is detected, the FAN54020 suspends

charging functionality if charging is active when OVP is

detected. The FAN54020 interrupts the host when the OVP

event occurs and sets the OVP_FLAG bit.

The SAFETY register (Reg0Fh) prevents the values in V_OREG

(Reg4[5:0]) and I_OCHARGE(Reg3 [7:4]) from exceeding the

SAFETY register values of V_SAFE(Reg0Fh[3:0]) and I_SAFE

(Reg0Fh[7:4]).

After DBP pin is set HIGH, the SAFETY register may only be

written before any other register is written. After writing to

any other register, the SAFETY register is locked until DBP

is set LOW. When DBP pin transitions from LOW to HIGH,

the default value of the Safety register is loaded.

Charging resumes when V_BUSreturns below the OVP

threshold. While charging is suspended, the t_30MINor t_32S

timer continues and D+ remains at 0.6 V if DBP is LOW.

V_SAFEand I_SAFEestablish values that limit the maximum

values of OREG and ICHG. If the host attempts to write a

When V_BUSrises above V_IBUS(DIS)(6.0 V typical), the IBUS

loop is disabled and remains disabled for the next one

second. If V_BUSfalls below V_IBUS(DIS)(5.75 V), the IBUS loop

is re-enabled. This allows Q3 to be used as a linear regulator

to protect PMID from going above about 6 V, while still

allowing the charger to operate up to its OVP threshold.

When Q3 is used as a linear regulator, it can no longer be

used as a sense element for IBUS.

value higher than V_SAFEor I_SAFEto V_OREGor I_OCHARGE

,

respectively; the V_SAFEand I_SAFEvalue appears as the V_OREG

and I_OCHARGEregister values, respectively.

Boost Mode

Boost Mode can be enabled by the BOOST_EN bit

(Reg2[6]). To remain in BOOST Mode, the TMR_RST bit

must be periodically reset to prevent the t_32Stimer from

overflowing. To remain in Boost Mode, the TMR_RST must

be set by the host before the t_32Stimer times out. If t_32Stimes

out in Boost Mode; the IC resets the BOOST_EN bit and

pulses the STAT pin.

V_BUSis typically 5 V ±10%, depending on the charging

current. If the FAN54020 is programmed to a higher current

than the charger can support, a VBUS regulation loop

ensures that the “weak” source does not create a situation

where VBUS collapses due to loading. The FAN54020

attempts to lower the charger current and maintain VBUS

to the value set in the VBUS_REF bits (Reg2[3:2]). The

VBUS regulation loop is enabled by default and has a

default value of 4.3 V.

Boost PWM Control

The IC uses a minimum on-time and computed minimum off-

time to regulate V_BUS. The regulator achieves excellent

transient response by employing current-mode modulation.

This technique causes the regulator to exhibit a load line.

During PWM Mode, the output voltage drops slightly as the

input current rises. With a constant V_BAT, this appears as a

constant output resistance.

Charging is stopped if V_BUSfalls below V_IN(MIN)1(3.7 V

typical) or V_BAT, typically indicating that VBUS has been

disconnected. Charging remains stopped until V_BUSrises

above V_IN(MIN)1(4.4 V typical) and stays above this threshold.

The “droop” caused by the output resistance when a load is

applied allows the regulator to respond smoothly to load

transients with no undershoot from the load line. This can be

seen in Figure 48.

Thermal Regulation Loop

If the IC junction temperature reaches T_CF(Reg5[7:6]), the

charger reduces its output current to 300 mA to prevent

overheating and the TREG_FLAG bit is set. If the temperature

increases beyond T_SHUTDWN; charging is suspended and the

TSD_FLAG is set. While charging is suspended, the t_30MINor

t_32Stimer continues to run and D+ remains at 0.6 V if DBP is

LOW. Charging resumes at programmed current after the die

cools below T_CF. This algorithm allows for the fastest recovery

from a thermal regulation event, while still averaging a

current that keeps the temperature below T_CF.

360

320

280

240

200

160

In both cases, removal of the over-temperature conditions is

indicated via the OT_RECOV bit. Temperature is

continuously monitored whenever the charger is enabled.

2.0

2.5

3.0

3.5

4.0

4.5

Battery Voltage, VBAT (V)

Additional _JAdata points, measured using the FAN54020

evaluation board, are given in Table 3 (measured with

T_A=25°C). As power dissipation increases, the effective _JA

decreases due to the larger difference between the die

temperature and its ambient.

Figure 48.

Output Resistance (R_OUT)

V_BUSas a function of I_LOADcan be computed when the

regulator is in PWM Mode (continuous conduction) as:

V_OUT 5.07  R_OUTI_LOAD

Table 3. FAN54020 Evaluation Board ϴ_JA

At V_BAT=3.6 V and I_LOAD=500 mA, V_BUSwould drop to:

V_OUT 5.07  0.225  0.5  4.979V

Power (W)

0.504

_JA

54°C/W

50°C/W

46°C/W

At V_BAT=2.7 V and I_LOAD=200 mA, V_BUSwould drop to:

0.844

V_OUT 5.07  0.317  0.2  5.007V

1.506

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

24

PFM Mode

Attach Detection Protocol (ADP) Support

If V_BUS> VREF_BOOST(nominally 5.07 V) when the minimum

off-time has ended, the regulator enters PFM Mode. Boost

pulses are inhibited until V_BUS< VREF_BOOST. The minimum

on-time is increased to enable the output to pump up

sufficiently with each PFM boost pulse. Therefore, the

regulator behaves like a constant on-time regulator, with the

bottom of its output voltage ripple at 5.07 V in PFM Mode.

The FAN54020 supports Attach Detection Protocol (ADP) as

described in USB_OTG_and_EH_2-0-version 1_1, which

can be downloaded from: www.usb.org/developers/onthego/.

ADP support requires a mechanism for measuring the

capacitance on VBUS. A change in VBUS capacitance

signifies that a device requiring OTG power may have been

connected to VBUS. The FAN54020 supports ADP by

providing current sources, comparators, and a counter (see

Figure 49), enabling the host processor to periodically initiate

an ADP probe sequence, as described below:

Table 4. Boost PWM Operating States

Mode Description

LIN Linear Startup

SS Boost Soft-Start

BST Boost Mode

Invoked When

V_BAT> V_BUS

V_BUS< V_BST

When the OTG boost turns off, the IC turns on a 50 mA (I_DIS

)

current sink and waits until V_BUS< 0.10 V. Once V_BUS

crosses 0.1 V, the current sink is disabled and a VBUSLOW

interrupt is generated. At this point, the IC is in Sleep State

with all bias circuits turned off to minimize power drawn on

the battery.

V_BAT> UVLO_BST+ SS Completed

Shutdown State

When the boost regulator is shut down, current flow is

The host can also periodically monitor the status of VBUS by

writing a 1 to the RDVBUS bit. This causes the IC to turn on

its analog circuitry with power supplied from VBAT. The IC

issues a STAT pulse after it has refreshed VBUS_100,

VBUS_700, and VBUS_CMP to reflect the current condition

of VBUS, then powers down. The reference for VBUS_CMP

in this state is 3.9 V. After these bits are refreshed, (1 ms

maximum) the IC returns to Sleep State.

prevented from V_BATto V_BUSand from V_BUSto V_BAT

.

LIN State

When the boost is enabled, if V_BAT> UVLO_BST, the regulator

first attempts to bring PMID within 400 mV of V_BATusing an

internal 580 mA current source from VBAT (LIN State). If

PMID has not achieved V_BAT– 400 mV after 512 s, a

FAULT state is initiated.

If V_BUSfails to reach 0.1 V within 132 ms, the IBUS load is

turned off and a STAT pulse occurs. The system can

determine that VBUS failed to discharge below 0.1 V

because the VBUS_100 bit is HIGH.

SS State

When PMID > V_BAT– 400 mV, the boost regulator begins

switching with a peak current limit of about 50% of its normal

current limit. The output slews up until V_BUSis within 5% of

its set point; at which time, the regulation loop is closed and

the current limit is set to 100%.

ADP Probe

Host begins an ADP probe by setting ADP_PRB bit, which

will both turn on a 1.4 mA current and start the ADP_CNT

counter, when VBUS rises above 0.1 V.

If the output fails to achieve 95% of its set point (V_BST) within

128 s, the current limit is increased to 100%. If the output

fails to achieve 95% of its set point after this second 384 s

period, a Fault state is initiated.

If V_BUS> 0.1 V (V₁₀₀) when the host sets ADP_PRB, the

1.55 mA current sink is enabled (IBUSSINK = 1) to first

discharge VBUS to 0.1 V before enabling the current source

and ADP_CNT counter. If V_BUSfails to reach 0.1 V within

32 ms; an ADP_PRBERR interrupt is generated, ADP_PRB

is reset, and the VBUS_100 bit is set.

BST State

This is the normal operating mode of the regulator. The

regulator uses a minimum t_OFF-minimum t_ONmodulation

When V_BUSreaches 0.7 V (V₇₀₀), the current source

(IBUS_SRC) is turned off, with the count stored in the

ADP_CNT register, and an ADP_PRB interrupt is generated.

The counter counts in 40 s increments, so the capacitance

on the bus is calculated as shown in Table 5.

V

IN

scheme. The minimum t_OFFis proportional to

, which

V

OUT

keeps the regulator’s switching frequency reasonably

constant in CCM. T_ON(MIN)is proportional to V_BATand is a

higher value if the inductor current reaches zero before

t_OFF(MIN)in the prior cycle.

Table 5. ADP_CNT Equation

To ensure the V_BUSdoes not pump significantly above the

regulation point, the boost switch remains off as long as V_FB

ADP_RATE

C_BUS

ADP _CNT  40s

0.6V

> VREF_BOOST

.

1.4mA 

0

Boost Faults

If a boost fault occurs:

ADP _CNT  80s

0.6V

1

1. The STAT pin pulses (if the fault’s mask bit is reset)

with the corresponding interrupt bit set (see Table 25).

For example, for ADP_RATE = 0 (default), ADP_CNT = 50

when the VBUS capacitance is 4.7 F. Each increment of

ADP_CNT represents a capacitance of 93 nF.

2. BOOST_EN bit is reset.

3. The power stage is in High-Impedance Mode.

Boost Mode can only be re-enabled through I²C commands

since BOOST_EN is reset on boost faults.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

25

ADP Sense

CADP_THR(MIN) = 200 nF is therefore represented by an

difference of 2 between ADP_CNT readings.

The USB specification requires that a device determine

whether an attached device is performing an ADP Probe

before activating its own ADP probe. To perform an ADP

Sense, the host sets the ADP_SNS bit. This causes the

threshold of U1B in Figure 49 to be set to 400 mV and then

captures the state of U1B’s output. If U1B’s output

subsequently changes state, an ADP_SNSI interrupt is

generated and the ADP_SNS bit is reset, which indicates

that a connected device may have performed an ADP Probe.

If ADP_CNT reaches 255 while ADP_PRB = 1, it indicates the

attached capacitance exceeds 24 F, so an ADP_PRBERR

interrupt is generated and ADP_PRB is reset.

Once the PRBDONE interrupt occurs, the IC turns on the

current sink by setting the IBUSSINK bit, until either V_BUS

crosses 0.1 V (VBUS_100 bit = 0) or 32 ms elapses. If 32 ms

elapses; an ADP_PRBERR interrupt is generated,

IBUSSINK is reset, and the IC returns to full Sleep State with

VBUS_100 bit remaining HIGH.

If U1B’s output remains in the same state it was in when

ADP_SNS was set, that indicates that no other device was

conducting an ADP Probe. The host can then reset the

ADP_SNS bit to terminate ADP Sense.

ADP_CNT retains its value (either the value when

VBUS_700 rose or 255) until it is read by the host or

ADP_PRB is again set.

If V_BUSbecomes greater than V_BATduring either ADP Probe,

ADP Sense, or RDVBUS operations; the operation is

aborted and the IC starts the VBUS plug-in sequences

shown in Figure 37 or Figure 38.

To cancel or exit the ADP probe sequence, write

ADP_PRB=0.

VBAT

To exit the ADP sense sequence, write ADP_SNS bit to 0.

I_SRC

1.4mA

IBUS_SRC

U1A

VBUS

VBUS_700

VBUS_100

C_BUS

1F

0.7V

U1B

I_SINK

1.55mA

0.1V / 0.4V

IBUSSINK

Figure 49.

ADP Hardware

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

26

IC State Decode

The STATE register (Reg31) is provided for diagnostic purposes.

Table 6. STATE Register Decode

Value

STATE

Value

STATE

Production Test Mode

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

Initialization – Sleep state

Wait for POK and 30 clocks

Wait for temperature ok

V_BUSdebounce

V_BATdischarge

V_BUSPOR

20

21

22

28

29

2A

2B

2C

30

31

32

33

34

35

36

37

Production Test Mode

ADP 30 clocks, TOK

ADP sense 4 zeros

ADP sense 100 mV

ADP sense 700 mV

ADP Sense State

Boost power up

Boost strong bat

Boost linear done

Boost PWM soft-start

Top off

V_BUSvalidation V_BUSload

Charge Mode SEL

Linear charging

PWM charging

V_BUSdetect

V_BATdetect wait

Battery absent / battery full detect

Battery absent

Battery full

Run

Boost down

Post charge

High-Z State

Idle State

VBUS disconnect

No battery

Over-temperature wait

Wait OVP

Fault

Fault 0

Fault 1

Fault 2

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

27

I²C Interface

The FAN54020 serial interface is compatible with Standard,

Fast, Fast-Plus, and High-Speed Mode I²C Bus®

specifications. The FAN54020 SCL line is an input and the

SDA line is a bi-directional open-drain output; it can only pull

down the bus when active. The SDA line only pulls LOW

during data reads and when signaling ACK. All data is

shifted in MSB (bit 7) first.

During a read from the FAN54020 (Figure 55), the master

issues a Repeated Start after sending the register address

and before resending the slave address. The Repeated Start

is a 1-to-0 transition on SDA while SCL is HIGH, as shown in

Figure 53.

High-Speed (HS) Mode

The protocols for High-Speed (HS), Low-Speed (LS), and

Fast-Speed (FS) Modes are identical except the bus speed for

HS Mode is 3.4 MHz. HS Mode is entered when the bus

master sends the HS master code 00001XXX after a Start

condition. The master code is sent in Fast or Fast-Plus Mode

(less than 1 MHz clock); slaves do not ACK this transmission.

Slave Address

Table 7. I²C Slave Address Byte

7

6

5

4

3

2

1

0

1

0

1

0

1

R/W

The master then generates a Repeated Start condition

(Figure 53) that causes all slaves on the bus to switch to HS

Mode. The master then sends I²C packets, as described

above, using the HS Mode clock rate and timing.

In hex notation, the slave address assumes a 0 LSB. The

hex slave address is D6H. Other slave addresses can be

accommodated upon request; contact

Semiconductor representative.

a

Fairchild

The bus remains in HS Mode until a stop bit (Figure 52) is

sent by the master. While in HS Mode, packets are

separated by Repeated Start conditions (Figure 53).

Bus Timing

As shown in Figure 50, data is normally transferred when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

Slave Releases

t_SU;STA

t_HD;STA

ACK(0) or

NACK(1)

SLADDR

MS Bit

SDA

SCL

Data change allowed

Figure 53.

Repeated Start Timing

SDA

T_H

Read and Write Transactions

Figure 54 – Figure 57 outline the sequences for data read and

T_SU

SCL

write. Bus control is signified by the shading of the packet,

Master Drives Bus

All addresses and data are MSB first.

Table 8. Bit Definitions for Figure 54 – Figure 57

Slave Drives Bus

Figure 50.

Data Transfer Timing

defined as

and

.

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which is

defined as SDA transitioning from 1 to 0 with SCL HIGH, as

shown in Figure 51.

Symbol

Definition

START, see Figure 51

T_HD;STA

Slave Address

MS Bit

S

SDA

ACK. The slave drives SDA to 0 to acknowledge

the preceding packet.

A

SCL

NACK. The slave sends a 1 to NACK the

preceding packet.

Figure 51.

Start Bit

R

P

Repeated START, see Figure 53

STOP, see Figure 52

A transaction ends with a STOP condition, which is defined

as SDA transitioning from 0 to 1 with SCL HIGH, as shown in

Figure 52.

Slave Releases

Master Drives

t_HD;STO

ACK(0) or

NACK(1)

SDA

SCL

Figure 52.

Stop Bit

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

28

Multi-Byte (Sequential) Read and Write Transactions

Sequential Read (Figure 57)

Sequential Write (Figure 56)

Sequential reads are initiated in the same way as a single-

byte read (Figure 55), except that once the slave transmits

the first data byte, the master issues an acknowledge

instead of a STOP condition. This directs the slave’s I²C

logic to transmit the next sequentially addressed 8-bit word.

The FAN54020 contains an 8-bit counter that increments the

address pointer after each byte is read, which allows the

entire memory contents to be read in one I²C transaction.

The slave address, Reg Addr address, and the first data byte

are transmitted to the FAN54020 in the same way as in a

byte write (Figure 54). However, instead of generating a Stop

condition, the master transmits additional bytes written to

consecutive sequential registers after the falling edge of the

eighth bit. After the last byte is written and its ACK bit

received, the master issues a STOP bit. The IC contains an

8-bit counter that increments the address pointer after each

byte is written.

Figure 54.

Figure 55.

Single-Byte Write Transaction

Single-Byte Read Transaction

Figure 56.

Figure 57.

Multi-Byte (Sequential) Write Transaction

Multi-Byte (Sequential) Read Transaction

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

29

Register Descriptions

Table 9. I²C Register Address

Register

Address Bits

Name

REG#

7

6

5

4

3

2

1

0

IC_INFO

CHARGE_CTRL1

CHARGE_CTRL2

IBAT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

VOREG

4

IBUS

5

INT

6

STATUS

7

INT_MASK

ST_MASK

TMR_RST

SAFETY

8

9

0AH (10)

0FH (15)

10H (16)

1FH (31)

20H (32)

21H (33)

22H (34)

MONITOR

STATE

ADP_CTRL

ADP_CNT

TMR_CTRL

Register Bit Definitions

Default values are in bold text. Blue text indicates that operations performed on these bits map to the same physical register

bits, regardless of which slave address is used.

Table 10. Reg Addr: 0

IC_INFO

Bit

Reg Addr: 0

Default = 100X XXXX

Name

Type

Description

100: Identifies Fairchild as the supplier

7:5

4:3

2:0

VENDOR

PN

R

Part number bits, see the Ordering Info on page 2

IC Revision. Revision is 1.X, where X is the decimal of these 3 bits.

REV

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

30

Table 11. Reg Addr: 1

CHARGE_CTRL1

Reg Addr: 1

Default = 000x 0010

Bit

Name

Type

Description

Setting this bit to 1 resets all registers and operation to default values.

This bit returns 0 when read.

7

RESET

W

0: Charging is enabled.

6

5

4

3

HZ_MODE

Reserved

R/W

R

1: Charging is disabled.

This bit returns 0 when read.

0: VBUS regulation loop is active (V_BUS= V_{BUS_REF}).

1: V_BUS> V_{BUS_REF}when in charge state.

VBUS_LOOP

Reserved

R

This bit returns 0 when read.

When V_BUSis at or above this threshold, a V_BUSOVP fault is enunciated and the charger is

disabled until the fault clears.

Table 12. V_BUSOVPThreshold

[2:1] V_BUSOVPThreshold

2:1

V_BUSOVP

R/W

00

01

10

11

6.5

7.0

7.5

8.0

0: No interrupt has occurred. This bit is reset when this register is read.

0

INTERRUPT

R

1: Interrupt has occurred.

Table 13. Reg Addr: 2

CHARGE_CTRL2

Reg Addr: 2

Default = 0000 0111 (07H)

Bit

Name

Type

Description

0: Normal operation

7

PTM_EN

R/W

1: Production Test Mode is enabled if NOBAT (Reg5[0]) = 1. See Production Test Mode

description.

0: OTG boost regulator is disabled.

6

5

BOOST_EN

BOOST_UP

R/W

R

1: OTG boost regulator is enabled.

0: Boost output is either disabled or out of regulation.

1: Boost regulator is enabled and in regulation (not in a fault condition).

0: 3.3 V LDO is ON and biased from VBAT when:

(V_BUS< V_BATand the DBP pin is HIGH)

4

LDO_OFF

R/W

1: 3.3 V LDO is OFF when V_BUS< V_IN(MIN)1

Sets the V_{BUS_REF}threshold.

Table 14. V_{BUS_REF}Threshold

DEC

BIN

00

V_{BUS_REF}

4.24

0

1

2

3

3:2

VBUS_REF

R/W

01

4.32

10

4.40

11

4.48

0: Charging re-starts if V_BAT< V_OREG-V_RCH

1: Charging does not re-start automatically if VBAT drops.

.

1

0

VRCH_DIS

ITERM_DIS

R/W

0: Charging terminates at the programmed ITERM level.

1: Charging does not terminate at the programmed ITERM level.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

31

Table 15. Reg Addr: 3

IBAT

Reg Addr: 3

Default = 0000 0010 (02H)

Bit

Name

Type

Description

Table 16. I_OCHARGESettings; Current for R_SENSE= 68 m

I_OCHARGE(mA)

V_RSENSE(mV)

DEC

BIN

HEX

Typ

Max

Typ

326

372

465

570

665

760

855

950

Max

350

400

500

600

700

800

900

1,000

1,100

1,200

1,300

1,400

1,500

0

1

2

3

4

5

6

7

8

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

22.13

25.30

31.62

38.76

45.22

51.68

58.14

64.60

71.06

77.52

83.98

90.44

96.90

23.80

27.20

34.00

40.80

47.60

54.40

61.20

68.00

7:4

I_OCHARGE

R/W

74.80 1,045

81.60 1,140

88.40 1,235

95.20 1,330

102.00 1,425

9

10

11

12

13

14

15

Table 17. I_TERMSettings; Current for R_SENSE= 68 m

V_RSENSE(mV)

3.4

I_TERM(mA)

50

BIN

HEX

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

5.1

6.8

8.5

75

100

125

150

175

200

225

250

275

300

325

350

375

400

425

10.2

11.9

13.6

15.3

17.0

18.7

20.4

22.1

23.8

25.5

27.2

28.9

3:0

ITERM

R/W

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

32

Table 18. Reg Addr: 4

OREG

Reg Addr: 4

Default = 0000 1000 (08H)

Bit

Name

Type

Description

7:6

Reserved

R

These bits return 0 when read.

Table 19. OREG Settings

DEC

0

BIN

HEX V_OREG(V)

Dec

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Binary

Hex V_OREG(V)

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

3.38

3.40

3.42

3.44

3.46

3.48

3.50

3.52

3.54

3.56

3.58

3.60

3.62

3.64

3.66

3.68

3.70

3.72

3.74

3.76

3.78

3.80

3.82

3.84

3.86

3.88

3.90

3.92

3.94

3.96

3.98

4.00

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

4.02

4.04

4.06

4.08

4.10

4.12

4.14

4.16

4.18

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

4.38

4.40

4.42

4.44

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

5:0

V_OREG

R/W

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

33

Table 20. Reg Addr: 5

IBUS

Reg Addr: 5

Default = 1000 0000 (80H)

Bit

Name

Type

Description

Temperature threshold at which the current is reduced to allow the device to cool. See Thermal

Regulation Loop.

Table 21. Temperature Threshold Settings

DEC

BIN

00

T_CF

70

7:6

T_CF

R/W

0

1

2

3

01

85

10

100

120

11

5:2

1:0

Reserved

R

These bits return 0 when read.

Table 22. IBUS Settings

DEC BIN I_BUSLimit (Max.)

0

1

2

3

00

01

10

11

100 mA

500 mA

900 mA

No Limit

I_BUS

R/W

Table 23. Reg Addr: 6

INTERRUPT

Reg Addr: 6

Default = 0000 0000 (00H)

Bit

Name

Type

Description

A 1 in a given bit position indicates that a specific fault has occurred as described in the table

below. Items in blue are transient conditions, whose bits are cleared when this register is read.

The other interrupts herein are not cleared unless the underlying condition has been removed.

Table 24. Charger Interrupt Conditions

Bit # FLAG

Interrupt

7

6

5

4

3

2

1

TSD_FLAG

Thermal shutdown (TJ > 145°C).

VBUS OVP (OVP shutdown).

Charger thermal regulation is active.

T32Sec timer has timed out.

OVP_FLAG

TREG_FLAG

TC_TO

DBP_TO

Dead-Battery (DBP) timer (T30) has timed out.

Die temperature has fallen below 120°C.

VBUS OVP recovery has occurred.

OT_RECOV

OVP_RECOV

7:0

INT

R

Battery absence detected either at VBUS POR or after

charger termination.

0

NOBAT

Table 25. Boost Mode Interrupt Conditions

Bit # FLAG

Interrupt

7

6

TSD_FLAG

Thermal Shutdown (TJ > T_CF°C)

V_BUSOVP (Over-Voltage shutdown)

OVP_FLAG

Boost output is out of regulation due to sustained

current limit.

5

BOOSTOV

4

3

2

1

0

TC_TO

BAT_UV

NA

t_32Stimer has timed out.

Battery voltage below 2.7 V.

NA

N/A

This bit is always 0 in Boost Mode.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

34

Table 26. Reg Addr: 7

STATUS

Reg Addr: 7

Default = 0100 0000 (40H)

Bit

7:5

4

Name

VBUS_STAT

Reserved

Type

Description

An interrupt is generated when there is a state change in the bit, provided the

corresponding bit in the VBUS_MASK = 0. Items in blue are transient conditions, whose

bits are cleared when this register is read. The other interrupts are not cleared unless the

underlying condition has been removed.

Table 27. Interrupt Conditions

R

Bit #

FLAG

VBUS_CON 1 when VBUS is connected, 0 when VBUS is disconnected.

POK_B State of the POK_B pin.

VALIDATION 1 indicates V_BUSvalidation is attempted and failed. After a

Interrupt generated

7

6

5

FAIL failure, V_BUSvalidation is attempted every two seconds.

This bit returns 0 when read.

An interrupt is generated when there is a state change in the bit, provided the

corresponding bit in the ADP_MASK = 0. Reading this register will reset these bits.

Table 28. ADP Interrupt Conditions

Bit #

FLAG

Interrupt Generated

When VBUS reaches 700 mV (VBUS_700 ) when

IBUS_SRC = 1.

3

PRBDONE

If V_BUSfails to reach its threshold before a timer times out.

This can occur if:

3:0

ADP_STAT

R

1. ADP_PRB was set with V_BUS> 100 mV and V_BUSfailed

to fall within 32 ms while being discharged with 1.55 mA.

2

ADP_PRBERR

2. V_BUSfailed to reach 700 mV within 255 counts of

ADP_CNT (16 ms) while IBUS_SRC was on.

3. VBUS was above 0.1 V 132 ms after boost disabled.

1

0

VBUSLOW

ADP_SNSI

V_BUScrossed 0.1 V within 132 ms after boost disabled.

VBUS_100 changed state from the state it had at the rising

edge ADP_SNS

(R20[5]). When this bit rises, the ADP_SNS bit is reset.

Table 29. Reg Addr: 8

INT_MASK

Reg Addr: 8

Default = 0000 0000 (00H)

Description

Bit

Name

Type

A 1 in a bit masks the interrupt corresponding to that bit position in the INTERRUPT

7:0

INT_MASK

R/W register (Reg 6). When the interrupt is masked, the STAT pin does not pulse when the

masked event occurs, but the event is still flagged in the INTERRUPT register.

Table 30. Reg Addr: 9

ST_MASK

Reg Addr: 9

Default = 0000 0000 (00H)

Bit

Name

Type

Description

A 1 in a bit masks the interrupt corresponding to that bit position in the STATUS register

7:0

ST_MASK

R/W (Reg07). When the interrupt is masked, the STAT pin does not pulse when the masked

event occurs, but the event is still flagged in the STATUS register.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

35

Table 31. Reg Addr: 0AH (10)

TMR_RST

Reg Addr: 0AH (10)

Default = 0000 0X00

Bit

7

Name

Type

W

Description

Setting this bit to 1 resets the t_32stimer, allowing the IC to continue charging under control

of the I²C host. This bit returns 0 when read.

TMR_RST

Reserved

6

R

This bit returns 0 when read.

Monitors level of DBP pin:

0: DBP pin is LOW.

1: DBP pin is HIGH.

5

4

DBP_LEVEL

ILIM_LEVEL

R

Monitors level of ILIM pin.

0: ILIM pin is LOW.

1: ILIM pin is HIGH.

3

Reserved

R

Return 0 or 1 when read.

2:0

These bits return 0 when read.

Table 32. Reg Addr: 0FH (15)

SAFETY

Reg Addr: 0FH (15)

Default = 0111 0000 (70H)

Bit

Name

Type

Description

7:4 I_SAFE

R/W Any attempt to write a value to I_OCHARGE(Reg3[7:4]) higher than the contents of I_SAFEsets

I_OCHARGE= I_SAFE

.

Table 33. I_SAFESettings

DEC

0

BIN

HEX

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

I_SAFE

350

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

400

2

500

3

600

4

700

5

800

6

900

7

1000

1100

1200

1300

1400

1500

8

9

10

11

12

13

14

15

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

36

SAFETY

Bit

Reg Addr: 0FH (15)

Default = 0111 0000 (70H)

Name

Type

Description

3:0 V_SAFE

R/W Any attempt to write a value to V_OREG(Reg4[5:0]) higher than the contents of V_SAFEsets

V_OREG= V_SAFE

.

Table 34. V_SAFESettings

DEC

0

BIN

HEX

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

V_SAFE

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

4.38

4.40

4.42

4.44

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Table 35. Reg Addr: 10H (16)

MONITOR

Reg Addr: 10H (16)

Bit

Name

Type

Description

0: I_BAT< I_TERMreference.

1: I_BAT> I_TERMreference.

7

ITERM_CMP

R

0: V_BUS< V_BAT

1: V_BUS> V_BAT

.

6

5

4

3

2

1

VBUS_VBAT

VSHORT

DIS_LEVEL

INACTIVE

IBUS

R

0: V_BAT> V_SHORTor IC is not charging.

1: V_BAT< V_SHORTand IC is charging.

0: DIS pin is LOW.

1: DIS pin is HIGH.

0: Charger is either logically disabled or is actively charging (switcher is active).

1: Charger is enabled, but is not delivering power because V_BAT> V_OREG

.

0: IBUS loop is limiting the charge current.

1: IBUS loop is not limiting the charge current.

0: ICHG loop is limiting the charge current.

1: ICHG loop is not limiting the charge current.

ICHG

0: Charger is not in CV Mode. Charger is off or another loop (VBUS, IBUS, or ICHG) is

limiting charge current.

0

CV

R

1: Charger is on and in Constant Voltage (CV) Mode.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

37

Table 36. Reg Addr: 1FH (31)

STATE

Reg Addr: 1FH (31)

Bit

Name

Type

Description

7:0

STATE

R

Charger state machine value. See Table 6.

Table 37. Reg Addr: 20H (32)

ADP_CTRL

Reg Addr: 20H (32)

Default = 0000 00XX

Bit

Name

Type

Description

0: VBUS current sink is off.

1: VBUS current sink is on.

7

IBUSSINK

R

0: ADP probe sequence not activated.

6

5

ADP_PRB

ADP_SNS

R/W

1: ADP probe sequence active. This bit is reset once ADP probe is completed.

0: VBUS_100 comparator threshold = 100 mV and ADP Sense interrupt is

disabled.

1: VBUS_100 comparator threshold is set to 400 mV and ADP Sense interrupt is

enabled.

0: ADP_CNT increment = 40 s.

1: ADP_CNT increment = 80 s.

4

3

ADP_RATE

RDVBUS

R/W

W

Writing a 1 to this bit temporarily (about 1 ms) brings the IC out of Sleep State to refresh

all VBUS comparator bits in this register. An interrupt is issued when the IC returns to

Sleep State.

0: V_BUS< VBUS_CMP_REF.

1: V_BUS> VBUS_CMP_REF.

Table 38. V_BUSComparator Reference

2

VBUS_CMP

R

STATE

VBUS < VBAT CHARGING VALIDATION

VBUS_CMP_REF

3.9

3.7

4.4

0: V_BUS< 700 mV.

1: V_BUS> 700 mV.

1

0

VBUS_700

VBUS_100

R

0: V_BUS< 100 mV.

1: V_BUS> 100 mV.

Table 39. Reg Addr: 21H (33)

ADP_CNT

Reg Addr: 21H (33)

Default = 0000 0000

Bit

Name

Type

Description

Counter that increments every 40 s (default or 80 s if ADP_RATE=1) after V_BUScrosses

100 mV with IBUS_SRC on.

7:0

ADP_CNT

R

When VBUS_700  or when ADP_CNT reaches 255, ADP_CNT stops incrementing, which

generates an PRBDONE or ADP_PRBERR, respectively.

ADP_CNT is reset after being read by the host or when ADP_PRB is set.

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

38

Table 40. Reg Addr: 22H (34)

TMR_CTRL

Reg Addr: 22H (34)

Default = 0000 0000 (00H)

Bit

Name

Type

Description

0: Die temperature is below 135°C.

1: Die temperature is above 135°C.

7

T135

R

0: Die temperature is below T_CF(see Table 21).

1: Die temperature is above T_CF(see Table 21).

6

5

4

3

2

1

0

TCFCOMP

EN_CHG

EN_LDO

NBAT

R

0: PWM charger is disabled.

1: PWM charger is enabled.

0: LDO is off.

1: LDO is on.

R

0: A no-battery test was not completed.

1: A no-battery test was completed.

R

These bits are reset if VBUS is disconnected.

0: T30M timer has not expired.

1: T30M timer has expired.

T30M

R

0: T30M timer is enabled.

DIS_30M

WD_DIS

R/W

1: T30M timer is disabled (never expires).

0: T32Sec timer enabled.

1: T32Sec timer disabled (never expires).

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

39

PCB Layout Recommendations

Bypass capacitors should be placed as close to the IC as

possible. In particular, the total loop length for CMID should

be minimized to reduce overshoot and ringing on the SW,

PMID, and VBUS pins. All power and ground pins must be

routed to their bypass capacitors using top copper if

possible. Copper area connecting to the IC should be

maximized to improve thermal performance.

Figure 58.

PCB Layout Recommendation

Product-Specific Dimensions

D

E

X

Y

2.050 +0.030 mm

0.200 mm

www.fairchildsemi.com

FAN54020 • Rev. 1.0.1

40

0.03 C

F

E

A

2X

1.60

0.40

B

(Ø0.200)

Cu Pad

A1

BALL A1

INDEX AREA

(Ø0.300)

Solder Mask

1.60

D

0.40

0.03 C

RECOMMENDED LAND PATTERN

(NSMD PAD TYPE)

2X

TOP VIEW

0.06 C

0.625

0.378±0.018

0.208±0.021

0.547

0.05 C

E

SIDE VIEWS

C

SEATING PLANE

D

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 1994.

1.60

0.40

0.005

C A B

Ø0.260±0.02

25X

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

E

D

C

B

E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS

±39 MICRONS (547-625 MICRONS).

1.60

0.40

(Y) ±0.018

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

A

F

2

3

5

4

1

G. DRAWING FILENAME: MKT-UC025AArev3.

(X) ±0.018

BOTTOM VIEW

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

www.onsemi.com

1


型号：	FAN54020UCX
厂家：	ONSEMI
描述：	兼容 USB 1.5 A 单体锂离子开关充电器，具有 DBP 和 OTG 升压调节器开关调节器
文件：	总43页 (文件大小：1739K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN54020UCX [ONSEMI]

相关型号：

FAN5402UCX

FAN5402UCX

FAN5403

FAN5403BUCX

FAN5403UCX

FAN5403UCX

FAN5404

FAN54040

FAN54040

FAN54040UCX

FAN54040UCX

FAN54041