FAN54120 [ONSEMI]
500 mA USB Compatible Single Cell Li-Lon Linear Charger with âPower Backâ Capability;
| 型号： | FAN54120 |
| 厂家： | 
ONSEMI |
| 描述： | 500 mA USB Compatible Single Cell Li-Lon Linear Charger with âPower Backâ Capability |
| 文件： | 总13页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
500 mA USB Compatible
Single Cell Li-Lon Linear
Charger with “Power Back”
Capability
FAN54120
The FAN5120 is a small, low−cost, fully integrated single−cell
charger which supports dead battery revival, pre−charge, fast charge,
and float charge states.
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Fast charging current (I ) is set with an external resistor.
FAST
Pre−charge (I ) and charge complete (I
) currents are
PRE
CHGEND
factory set at I /5.2 and I /10, respectively.
FAST FAST
The FAN54120 is specifically designed for ease−of−use as
a stand−alone charger. It requires no user interaction or active
supervision.
DFN6 2x2, 0.65P
CASE 506DQ
WLCSP6 1.36x0.76
CASE 567XQ
An open−drain STAT pin provides charge and/or fault status
indication.
“Power Back” capability to source accessories from the battery.
The FAN54120 is available in a 2x2 DFN package or
a 1.36x0.76 mm WLCSP.
MARKING DIAGRAM
1
XX M
Features
• Fully Integrated Charger for Single Cell Li−Ion or Li−Polymer
Batteries
• Factory Configured Charge Voltage (Ordering Option)
XX= 20, Specific Device Number
M = One Digit Date Code
= Pb Free
•
0.5% Charge Voltage Accuracy
• User Determined Fast Charge Current Via External Resistor
• +4% Charge Current Accuracy
• 28 V Maximum Input Voltage, 6 V Operating
• Ultra−low Battery Discharge Current (<120 nA)
• True Reverse Current Blocking
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
• Adaptive Thermal Regulation
• Supports JEITA Safe−to−Charge Operation with an External NTC
• “Power Back Functionality to Power Accessories from the Battery
FAN54120
VIN
VIN
BAT
+
C
IN
STAT
NTC
Application
C
OUT
LOAD
NTC
GND ISET
• IoT Devices
• E−Cigs / Vapes
R
SET
• Personal Mobile Devices (Games, Camera, etc.)
• Toys
Figure 1. Typical Application
• Point−of−Sale Instruments
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
FAN54120/D
November, 2019 − Rev. 0
FAN54120
Table 1. ORDERING INFORMATION
†
Part Number
V
(V)
Package
Packing Method
FLOAT
4.20
4.25
4.35
4.20
4.25
4.35
DFN6, 2x2 mm
(Pb Free)
3000 / Tape & Reel
FAN54120MP420X
FAN54120MP425X
FAN54120MP435X
FAN54120UC420X
FAN54120UC425X
FAN54120UC435X
WLCSP−6, 1.36x0.76 mm
3000 / Tape & Reel
(Pb Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
BLOCK DIAGRAM
Q1A Q1B
VIN
BAT
Q2
Q1
+
LOAD
CIN
COUT
CHARGE
PUMP
OSC
REF
RSTAT
OVP
CHARGE
CONTROL
and
LOGIC
STAT
GND
ISET
NTC
RSET
NTC
Figure 2. Simplified Block Diagram
Table 2. RECOMMENDED EXTERNAL COMPONENTS
Component
Description
Supplier
Parametr
Unit
Typ.
C
1.0 mF, 25 V, 10%, X5R, 0603
1.0 mF, 10 V, 10%, X5R, 0402
Murata GRM188R61E105KAAD
Murata GRM155R61A105KE15
Murata NCP15XH103F03RC
C
C
mF
mF
1.0 (Note 2)
1.0 (Note 2)
10
IN
C
(Note 1)
OUT
NTC
10 KW, 1%, B
= 3380, 0402
R
KW
25/85
25
1. The minimum required C
value is shown. The expected bypass capacitance range is 1 μF to 10 μF. For applications with large dynamic
OUT
OUT
pulsed loads, additional C
may be necessary to constraint voltage deviations.
2. The typical (face) value does not include the effects of applied voltage or temperature de−rating.
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2
FAN54120
PIN CONNECTIONS
6
VIN
1
BAT
GND
STAT
BAT
GND
STAT
VIN
A1
B1
C1
A2
B2
C2
A
ISET
2
3
5
4
ISET
NTC
Top View
(GND)
NTC
6
1
2
3
A2
B2
C2
A1
B1
C1
Bottom View
A
5
4
(GND)
Figure 4. WLCSP Package
Figure 3. DFN Package
Table 3. PIN DEFINITIONS
DFN Pin
WLCSP Pin
Pin Name
VIN
Description
1
2
A2
B2
Input Voltage. Connect C bypass directly to VIN and GND pins on top layer.
IN
ISET
Set Charge Current. Connect R
directly to GND to set the maximum input/charging
SET
current (I
).
FAST
3
4
C2
C1
B1
A1
NTC
STAT
GND
BAT
NTC input. Connect to battery pack NTC to provide JEITA “safe−charging” functionality.
See “NTC Pin” applications section for additional usage information.
Status. Open−drain output used to indicate charge and/or fault status. Internally, there is
a weak pull−up (R ) to BAT. This pin is also used to enable Power Back operation.
STAT
5, A
6
Ground. Connect to system GND plane. C and C
also connect directly to this pin on
IN
OUT
top layer.
Output. Connect to system load and positive terminal of battery. Bypass with C
connected directly to BAT and GND pins on top layer.
,
OUT
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
Max.
Unit
V
Voltage on VIN Pin
−1.2
28.0
10
V
V/msec
V
IN
V
VIN Rise Time, V > 6 V
IN_SLEW
IN
V
BAT
Voltage on BAT Pin
−0.3
−0.3
6.3
V
Voltage on All Other Pins
(Note 3)
1500
2000
100
V
X
ESD
Electrostatic Discharge Protection Level, HBM per JESD22−A114
Electrostatic Discharge Protection Level, CDM per JESD22−C101
Latch Up per JESD78, Class I, 25°C
V
V
LU
mA
°C
T
Junction Temperature
−40
−65
+150
+150
+260
J
T
STG
Storage Temperature
°C
T
LS
Lead Soldering Temperature, 10 Seconds
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Lesser of 6.3 V or the higher of V +0.3 V or V
+0.3 V.
IN
BAT
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3
FAN54120
Table 5. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
4
Max.
6
Unit
V
V
IN
Voltage on VIN Pin
Battery Voltage
V
BAT
2.5
−30
−30
4.5
V
T
A
Ambient Temperature
Junction Temperature
+85
+120
°C
°C
T
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
NOTE: The Recommended Operating Conditions table defines the conditions for actual device operation using the circuit of Figure 1,
with the Recommended External Components shown in Table 2. Recommended operating conditions are specified to ensure
optimal performance to the datasheet specifications. On Semiconductor does not recommend exceeding them or designing to
the Absolute Maximum Ratings.
Table 6. THERMAL PROPERTIES
Symbol
Parameter
Thermal Resistance, Junction to Ambient
Typical
Unit
θ
JA
°C/W
DFN−6
CSP−6
DFN−6
CSP−6
75
140
50
θ
JB
Thermal Resistance, Junction to Board (Note 4)
°C/W
70
NOTE: Thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p boards in accordance
with JEDEC standard JESD51. Special attention must be paid to not exceed junction temperature T at a given ambient
J(max)
temperature T .
A
4. θ measured using On Semiconductor evaluation board.
JB
Table 7. ELECTRICAL CHARACTERISTICS (Unless otherwise specified, circuit of Figure 1 with V = 5.0 V, V
= 4.2 V,
IN
FLOAT
V
BAT
= 3.9 V, R = 1.0 kW, over recommended T operating temperature range. Typical values are at 25°C.)
SET A
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
POWER SOURCES
V
V
V
V
Rising UVLO Threshold
Falling UVLO Threshold
V
V
V
V
V
≤ 3.9 V
≤ 2.9 V
4.25
3.00
4.40
4.55
3.30
V
V
IN(RISE)
IN
BAT
BAT
IN
3.15
80
IN(FALL)
IN
Sleep Comparator Threshold
V
− V
Rising
mV
mV
msec
W
SLP_R
BAT
BAT
V
− V
Falling
30
SLP_F
IN
IN
t
VIN Validation Time (Note 7)
VIN Validation Load
> V
32
IN_VALID
IN(RISE)
R
100
200
IN_VALID
V
VIN Validation Hysteresis
V
IN
Drop, from V , During
IN(RISE)
mV
VAL_HYST
Validation
I
VIN Quiescent Current
5.0 V , I
SET
= 0, NTC = GND,
600
720
mA
IN_Q
IN BAT
R
= 10 kW
V
Drop−Out Voltage (V – V
)
V
V
V
= 4.75 V, RSET = 1 kW
280
120
450
300
300
6.6
mV
nA
nA
V
DROP
IN
BAT
IN
I
Battery Discharge Current, Sleep Mode
BAT−to−VIN Leakage Current
= 4.2 V, VIN Open
BAT_LKG
BAT
BAT
I
= 4.2 V, V = 0 V
IN
VIN_LKG
V
VIN Over−Voltage Protection Threshold
Rising V
6.0
6.3
IN_OVP
IN
CHARGER VOLTAGE REGULATION
V
FLOAT
Float Voltage Range, V
Fixed Factory Set−point, 50 mV
Increments
4.20
4.35
V
BAT
Float Voltage Accuracy, V
0 ≤ T ≤ +50°C
−0.5
−1.2
−1.5
2.9
0.5
+1.0
+1.0
3.3
%
%
BAT
J
−10 ≤ T ≤ +85°C
J
−30 ≤ T ≤ +120°C
%
J
V
Pre−to−Fast Charge Threshold
Rising V
3.1
V
BATMIN
BAT
V
RCH
Battery Recharge Indicator Threshold
V
V
Falling Below V –
FLOAT
120
mV
BAT
RCH
V
Battery Short Circuit Threshold
Rising V
2.1
2.2
2.3
V
SHORT
BAT
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FAN54120
Table 7. ELECTRICAL CHARACTERISTICS (Unless otherwise specified, circuit of Figure 1 with V = 5.0 V, V
= 4.2 V,
IN
FLOAT
V
BAT
= 3.9 V, R = 1.0 kW, over recommended T operating temperature range. Typical values are at 25°C.) (continued)
SET A
SYMBOL
CHARGER VOLTAGE REGULATION
Battery Short Circuit Hysteresis
CHARGER CURRENT REGULATION
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
V
Falling V
100
mV
SC_HYST
BAT
I
Fast Charge Current Range
10 kΩ ≥ R
≥ 1.0 kW
50
460
180
40
500
500
205
56
mA
mA
mA
mA
mA
FAST
SET
Fast Charge Current Accuracy (Note 5)
R
R
R
V
= 1.0 kW
= 2.5 kW
= 10 kW
< V
480
192
48
SET
SET
SET
I
Pre−Charge Current
< V
I
I
/
/
PRE
SHORT
BAT
BATMIN
FAST
5.2
Pre−Charge Current Accuracy
(Note 5) (Note 6)
R
= 1.0 kW
−6
−8
+6
+8
%
%
SET
SET
SET
R
R
= 2.5 kW
= 10 kW
−10
+10
%
I
Charge Complete Current
mA
CHGEND
FAST
10
Charge Complete Current
(Note 5) (Note 6)
R
R
R
= 1.0 kW
= 2.5 kW
= 10 kW
−8
+8
%
%
SET
SET
SET
−10
−15
+10
+15
%
t
Charge Complete Qualification Time
(Note 7)
Operating in V
Mode
32
1
msec
CHGENE
FLOAT
R
Minimum R
Value
R
< R Results
SET_SC
900
W
SET_SC
SET
SET
in Output Fault State
T
Shorted R
Qualification Time
SET
msec
RSET_SC
(Note 7)
STAT PIN
I
STAT Pin Leakage
V
= 4.5 V
100
0.4
nA
V
STAT(HI)
STAT
V
STAT Sink Capability
STAT Internal Pull−Up
I
= 5 mA
STAT(LO)
STAT
R
1
MW
STAT
NTC PIN
I
Source Current
mA
V
Valid, 100 mV < VNTC < 2.0 V
48
50
Off
52
NTC
IN
NTC = GND
Rising V , Charging Ceases
T
Cold Non−Charging Threshold
1225
255
1255
270
1285
280
mV
mV
0C
NTC
T
Warm Charging Threshold
Falling V
(T
, Charge Reduction
JEITA JEITA
45C
NTC
, I
)
T
Hot Non−Charging Threshold
Falling V
, Charging Ceases
160
109
170
1
180
130
mV
sec
mV
%
60C
NTC
t
NTC pin Sampling Interval (Note 7)
100 mV < V
< 2.0 V
NTC
NTC
T
V
FLOAT
Reduction
T
45C
T
45C
≥ V
≥ V
≥ T
≥ T
200
20
JEITA
JEITA
NTC
NTC
60C
I
I
Reduction
FAST
60C
THERMAL PROTECTION
T
REG
Thermal Regulation Threshold
(Note 7) (Note 8)
T Rising
J
120
20
°C
T
Thermal Regulation Hysteresis (Note 7)
Adaptive Thermal Regulation Foldback
T Falling
J
°C
REG_HYST
I
40
80
%
FAST
TREG
I
T
Thermal Shutdown Threshold
(Note 7) (Note 8)
T Rising
J
130
145
160
°C
SDOWN
Hysteresis(Note 7)
T Falling
J
T
REG
°C
t
Thermal Shutdown Qualification Time
(Note 7)
T Rising
J
1
msec
TSD_QUAL
t
Die Temperature Sampling Rate (Note 7)
32
msec
DIE_T
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5
FAN54120
Table 7. ELECTRICAL CHARACTERISTICS (Unless otherwise specified, circuit of Figure 1 with V = 5.0 V, V
= 4.2 V,
IN
FLOAT
V
BAT
= 3.9 V, R = 1.0 kW, over recommended T operating temperature range. Typical values are at 25°C.) (continued)
SET A
SYMBOL
TIMERS
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
t
Pre−Charge Fault Timer (Note 7)
32
2
msec
%
PRE_SC
t
Internal Oscillator Accuracy
Applies to All Timers/Counters
−15
+15
0.4
OSC
IN_REVAL
t
Input Re−Validation Attempt Period
(Note 7)
sec
POWER BACK
VSTAT
STAT Pin Input Logic HIGH Threshold
STAT Pin Input Logic LOW Threshold
Power Back UVLO Threshold
No V Applied, V
> V
> V
1.2
V
V
IN(HI)
IN(LO)
IN
BAT
BATMIN
VSTAT
No V Applied, V
IN
BAT
BATMIN
V
Not Start if V
<V
V
V
PBAK(UVLO)
BAT
BATMIN
BATMIN
t
Power Back Start Delay (Note 7)
Falling STAT until VIN Rise
Commences
2.7
msec
PBACK(ST)
I
Power Back Start−Up Inrush (Note 7)
3.9 V , No VIN Load
180
100
mA
PBACK(ST)
BAT
I
Power Back Quiescent Current
150
mA
Q_PBACK
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Current accuracies are specified with minimum 50 mV overhead (V − V
)
IN
BAT
6. Specified accuracy relative to actual/nominal I
level.
FAST
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Not tested in production.
8. Power Back mode uses T as thermal shutdown threshold.
REG
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FAN54120
TYPICAL CHARACTERISTIC
Unless otherwise specified, circuit of Figure 1 with V = 5.0 V, V
= 4.2 V, V
= 3.8 V, R = 1.0 kW, T = 25°C.
SET A
IN
FLOAT
BAT
250
200
150
100
50
−30C
+25C
+85C
0
2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8
Battery Voltage, V (V)
BAT
Figure 5. Sleep Mode Discharge Current
Figure 7. Start−Up at VIN Insertion, VBAT = 2.9 v
Figure 6. Start−Up VIN Insertion, VBAT = 3.8 V
160
0
140
120
100
80
−100
−200
−300
−400
−30C
−30C
+25C
+25C
+85C
+85C, 3.0VBAT
+85C
60
2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8
Battery Voltage, V (V)
0
100
200
300
400
500
Load Current (mA)
BAT
Figure 9. Power Back Mode Output Regulation
Figure 8. Power Back Mode Quiescent Current
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FAN54120
OPERATION / APPLICATION INFORMATION
At temperatures below the cold threshold (< T ) or above
0C
the hot threshold (>T ), charging is suspended and the pin
60C
ISET Pin – Setting the Charge Current (IFAST
)
tri−states.
R , connected to the ISET pin, is used to establish
SET
At temperatures between the warm threshold (> T
)
45C
the maximum charging current (I ). Input current will
FAST
and hot threshold (< T ), V
is internally reduced by
60C
FLOAT
be slightly higher due to the quiescent current of the device
flowing to GND.
V
and I
is internally reduced by I
to prevent
JEITA
FAST
JEITA
an unsafe charging condition. The STAT pin remains
asserted low.
For applications where the NTC device is undesired or not
IFAST(mA) + 500 B RSET(kW)
valid R range: 1.0 kW ≤ R ≤ 10 kW
SET
SET
available, using a fixed 10 kW R will allow full charging
SET
The accuracy/tolerance of the chosen R will directly
SET
without JEITA limitations. I
remains on.
NTC
influence the tolerance/accuracy of I
.
FAST
Similarly, connecting the NTC pin to GND will result in
being turned off and the JEITA thresholds disabled.
Selecting an R value outside the specified range can
SET
I
NTC
result in a non− charging state.
Leaving the NTC pin open/floating will result in
a non−charging state.
An open ISET pin will set I ~0, resulting in battery
FAST
discharge into the prevailing system load, even though
the IC may attempt to regulate V
It is the system designer’s responsibility to ensure a safe
charging environment, particularly when the JEITA
feature is not utilized.
.
FLOAT
Selecting
R
≤
R
also results in
SET
SET_SC
a non−charging state. In this case, the IC will enter
the Output Fault State, where it is latched off until
Input Power Connection and Validation
the input power (V ) is recycled.
With no V present (sleep state), Q2 and Q1 are off
IN
IN
and the Q1A body switch is open.
STAT Pin
Once V rises above V
, Q2 is gradually
IN
IN(RISE)
In Charge mode, the STAT pin, when asserted LOW,
indicates that the battery is being actively charged. STAT
will remain HIGH during non−charging or fault states.
enhanced. Q1 remains off until Input Validation completes.
If V ≥ V , Q1 remains off until V falls below
IN
IN_OVP
IN
V
and Input Validation occurs.
After Q2 is enhanced for ~16msec, Input Validation
occurs. A load (R ) is applied to the input for
IN_OVHYS
The STAT pin asserts LOW when:
Charging (I or I
)
IN_VALID
PRE
FAST
t
. V must remain above the V
IN_VALID
IN VAL_HYST
Thermal regulation
threshold for successful validation. If V does not remain
IN
Re−charge, battery drops below V
−V
with
FLOAT RCH
above V
, R
is suspended and validation
VAL_HYST IN_VALID
a valid V present
fails. If Input Validation fails, periodic validation attempts
will be repeated at a rate of t while V remains
IN
T
≤ V
≤ T (warm charging, JEITA
IN_REVAL
IN
45C
NTC
60C
above the higher of V
or V + V
.
IN(FALL)
BAT
SLP
reduction)
The STAT pin is HIGH during:
CHARGING
Charging does not commence until the Input Validation,
cycle completes. Q1 remains disabled and the STAT pin is
open−drain until charging starts.
Absence of a validated V
IN
Charge done (I ≤ I
)
BAT CHGEND
Thermal shutdown
Input Over−Voltage (V
Charging States
Figure 10 illustrates a common Li+ charging profile,
starting with a depleted battery:
) state
IN_OVP
Output Fault state (V ≤ V
)
BAT
SHORT
V
V
> T (cold non−charging threshold)
0C
NTC
< T (hot non−charging threshold)
V
FLOAT
NTC
60C
V
BAT
The STAT pin is also used to enable Power Back Mode
(see Power Back Operation section).
V
BATMIN
I
BAT
NTC Pin − JEITA Functionality
I
FAST
The FAN54120 supports the JEITA Safe−to−Charge
profile using the battery pack internal NTC device or
a discrete NTC placed in close proximity to the battery.
The fixed threshold voltages are designed consistent
I
PRE
I
CHGEND
PRE−
CHARGE
CURRENT
REGULATION
VOLTAGE
REGULATION
with I
and B
sourcing a nominal NTC value of 10 kW, 1%
= 3380. Other NTC devices can be used, although
NTC
Figure 10. Typical Charging Profile
25/85
the corresponding threshold temperatures may shift.
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FAN54120
During the pre−conditioning stage (Pre−Charge),
While in the thermal regulation state, charge current is
modulated to maintain device temperature between
a constant current I
(I
/5.2) is applied until
FAST
PRE
the battery voltage reaches V
.
the T
and T thresholds and STAT remains
BATMMIN
REG
REG_HYS
Once V
is applied. I
≥ V
FAST
, the fast charging current (I )
asserted.
BAT
BATMIN
FAST
is set with a discrete resistor (R ) at the
SET
Thermal Shutdown
To prevent potentially catastrophic device failure, a 2
level of thermal protection is provided. If T reaches
the thermal shutdown threshold (T
stopped until the device cools to T
the STAT pin will be open−drain.
ISET pin. The instantaneous jump of V , at V
representative of the charging current increase across
the series resistance of the battery path. The Current
Regulation stage is maintained until V
During the Voltage Regulation stage, charge current
diminishes as the actual battery cell voltage approaches
, is
BATMIN
BAT
nd
J
), charging will be
. During this time,
SDOWN
reaches V
.
BAT
FLOAT
REG
V
. I
is continuously monitored and, when it
FLOAT BAT
Disable
decreases to the charge complete (I
) threshold
CHGEND
FAN54120 does not have a dedicated Enable/Disable pin.
With a valid V present, the system can disable charging by
forcing the NTC pin higher than 1.5 V or creating an open
circuit on the NTC pin. Although charging will cease,
the device does not fully enter the low power sleep state.
Battery discharge current will remain minimal due to device
(I
/10), the battery is considered fully charged. Prior to
FAST
IN
entering the charge complete state, V
maintained, uninterrupted, for t
control must be
FLOAT
. The IC continues
CHGEND
V
FLOAT
operation to support the load.
Once End−of−Charge is established, the STAT pin
tri−states until a new or re−charge cycle starts. A re−charge
cycle is entered when V <V −V , where
I being drawn from VIN.
Q
BAT
FLOAT
RCH
the STAT pin re−asserts LOW until END−of−Charge is
POWER BACK OPERATION
reached.
Power Back provides an un−regulated output on the VIN
pin to power peripheral accessories, using the battery as
Output Fault State
This state is entered whenever V
charging commences or R
prevent potentially destructive currents in the device.
An Output Fault State will result in Q1, Q1A, and Q2
being latched off until input power (V ) is fully recycled.
Output Fault state is also entered at commencement of
charging if I
the power source. For a given battery voltage (V
),
BAT
≤ V
after
during start−up to
BAT
SHORT
the output will exhibit a finite output impedance equivalent
≤ R
SET
SET_SC
to FAN54120 R plus battery and protection switch ESR.
DS
Power Back operation is initiated by forcing a transition
of the STAT pin from HIGH to below V
. The IC
STAT(LO)
IN
ignores this input signal if
V
IN
is present,
V
V
or if V
was never greater than
BAT ≤ PBAK(UVLO), STAT
fails to to charge V
> V
before
PRE
timer expires.
BAT
SHORT
V
prior to forcing it LOW. The normal STAT pin
STAT(HI)
the t
PRE_SC
functionality, associated with charging, is disabled during
Power Back operation.
A soft−start feature is employed to limit inrush current
from the battery to charge potentially large accessory input
Input Disconnect/Detach
Upon removal of the input voltage source, as V falls
below the higher of V
IN
or V
+ V , Q1 opens
IN(FALL)
BAT SLP
capacitors, parallel to C .
IN
and R
is applied to discharge input caps. If V
IN_VALID
IN
During Power Back operation, the thermal shutdown
remains below the V
Otherwise, periodic re−validation attempts occur.
level, sleep state is entered.
IN(FALL)
protection threshold is T
. Thermal shutdown will result
REG
in latching open the current path between the BAT and VIN
pins. To restore Power Back operation, the STAT pin must
be recycled HIGH, then back LOW.
Input Over−Voltage Protection
When rising V reaches the input over−voltage threshold
IN
(V
), Q1 turns off, charging stops, and the STAT pin
In the event that a charging source is applied at the VIN
pin while in Power Back mode, Power Back operation is
automatically disabled, momentarily forcing the device into
Sleep State during the Charging Validation Cycle.
IN_OVP
becomes open drain. Automatic re−start occurs,
with soft−start, once V falls below V
re−validated.
and is
IN
IN_OVHYS
Thermal Regulation
The FAN54120 autonomously reduces power dissipation
upon reaching the thermal regulation temperature threshold
(T ≥ T
J
). It employs an adaptive scheme (I
), which
REG
TREG
incrementally reduces charge current to nullify excessive
temperature rise. It results in a higher average charging
current being maintained than more traditional methods, for
instance, reducing the charge current by half until the device
cools.
www.onsemi.com
9
FAN54120
PCB Layout Guideline
The GND side of R
should be routed with a trace
SET
directly to IC GND, rather than using a via to the GND plane.
This prevents transient currents in GND plane from
influencing the IC’s current regulation.
The same practices should be applied to the WLCSP
version. Due to the lack of a DAP on the CSP, the GND side
of C should be connected by via to the system GND plane.
IN
Figure 11. Example Layout, FAN54120MP (DFN)
Place C and C
as close possible to the IC. Connect
IN
OUT
the capacitors directly to the appropriate IC pins on the top
layer. Reference the circuit to the system GND plane,
typically on an inner layer, using a via in the IC DAP and/or
at the GND side of C
.
Figure 12. Example Layout, FAN54120UC (CSP)
OUT
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN6 2x2, 0.65P
CASE 506DQ
ISSUE O
DATE 31 AUG 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13618G
DFN6 2X2, 0.65P
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP6 1.36x0.76x0.581
CASE 567XQ
ISSUE O
DATE 03 APR 2019
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON02370H
WLCSP6 1.36x0.76x0.581
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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© Semiconductor Components Industries, LLC, 2018
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ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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