FAN5602MP5X [ONSEMI]
电荷泵，调节步升/步降 DC-DC 转换器;
| 型号： | FAN5602MP5X |
| 厂家： | 
ONSEMI |
| 描述： | 电荷泵，调节步升/步降 DC-DC 转换器 泵 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAN5602
Universal
(Step-Up/Step-Down) Charge
Pump Regulated DC/DC
Converter
www.onsemi.com
Description
The FAN5602 is a universal switched capacitor DC/DC converter
capable of step−up or step−down operation. Due to its unique adaptive
fractional switching topology, the device achieves high efficiency over
a wider input/ output voltage range than any of its predecessors. The
FAN5602 utilizes resistance−modulated loop control, which produces
lower switching noise than other topologies. Depending upon actual
load conditions, the device automatically switches between
constant−frequency and pulse−skipping modes of operation to extend
battery life.
1
WDFN8 3x3, 0.65P
CASE 511CD
MARKING DIAGRAM
The FAN5602 produces a fixed regulated output within the range of
2.7 V to 5.5 V from any type of voltage source. High efficiency is
achieved under various input/ output voltage conditions because an
internal logic circuit automatically reconfigures the system to the best
possi− ble topology. Only two 1 mF bucket capacitors and one 10 mF
output capacitor are needed. During power on, soft−start circuitry
prevents excessive current drawn from the supply. The device is
protected against short−circuit and over−temperature conditions.
The FAN5602 is available with 4.5 V and 5.0 V output voltages in a
3x3 mm WDFN8 package.
602
ALYWG
G
602 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Features
• Low−Noise, Constant−Frequency Operation at Heavy Load
• High−Efficiency, Pulse−Skip (PFM) Operation at Light Load
• Switch Configurations (1:3, 1:2, 2:3, 1:1, 3:2, 2:1, 3:1)
• 92% Peak Efficiency
PIN ASSIGNMENTS
VIN
1
2
3
4
8
7
6
5
ENABLE
C1+
C2+
C2−
VOUT
• Input Voltage Range: 2.7 V to 5.5 V
GND
C1−
• Output Current: 4.5 V, 100 mA at V = 3.6 V
IN
•
3% Output Voltage Accuracy
3x3mm 8−Lead MLP
• I < 1 mA in Shutdown Mode
CC
• 1 MHz Operating Frequency
ORDERING INFORMATION
See detailed ordering and shipping information on page 2
of this data sheet.
• Shutdown Isolates Output from Input
• Soft−Start Limits Inrush Current at Startup
• Short−Circuit and Over−Temperature Protection
• Minimum External Component Count
• No Inductors
• This is a Pb−Free Device
Applications
• Cell Phones
• Handheld Computers
• Portable RF Communication Equipment
• Core Supply to Low−Power Processors
• Low−Voltage DC Bus
• DSP Supplies
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
July, 2019 − Rev. 0
FAN604P/D
FAN5602
ORDERING INFORMATION
Part Number
†
Output Voltage, N
Package
Packing Method
VOM
FAN5602MP45X
4.5 V
5.0 V
WDFN8 3x3, 0.65P (Pb−Free)
WDFN8 3x3, 0.65P (Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
FAN5602MP5X
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
Application Diagram
Input 2.7V to 5.5V
V
IN
ENABLE
1
2
8
6
C2+
C2−
C
IN
V
OUT
OUT
FAN5602
C1+
C1−
C
B
C
7
5
3
4
GND
Figure 1. Typical Application Diagram
Block Diagram
V
ENABLE
IN
C1−
C1+
BAND GAP
V
OUT
FB
BG
ERROR
AMP
SOFT−START
EN
S
W
I
CURRENT
SENSE
C2 +
T
Light load
C
H
FB
EN
PFM
BG
R
A
Y
REF
DRIVER
MODE
SC
V
IN
C2−
150mV
V
OUT
1.6V
UVLO
V
IN
OSCILLATOR
GND
V
IN
V
OUT
Figure 2. Block Diagram
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2
FAN5602
Pin Assignments
VIN
C2+
C2−
GND
1
2
3
4
8
ENABLE
7
6
5
C1+
VOUT
C1−
3x3mm 8−Lead MLP
Figure 3. Pin Assignments
Table 1. PIN DESCRIPTIONS
Pin #
Name
Description
1
2
3
4
5
Supply Voltage Input.
VIN
C2+
C2−
GND
C1−
Bucket Capacitor2. Positive Connection.
Bucket Capacitor2. Negative Connection.
Ground
Bucket Capacitor1. Negative Connection.
Regulated Output Voltage. Bypass this pin with 10 mF ceramic low−ESR capacitor.
6
7
VOUT
C1+
Bucket Capacitor1. Positive Connection.
Enable Input. Logic high enables the chip and logic low disables the chip, reducing the supply current to
less than 1 mA. Do not float this pin.
8
ENABLE
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−3.0
−3.0
Max
Unit
V
VIN
VIN, VOUT, ENABLE, Voltage to GND
Voltage at C1+,C1−,C2+, and C2−to GND
Power Dissipation
6.0
VIN + 0.3
V
PD
TL
TJ
Internally Limited
Lead Soldering Temperature (10 seconds)
Junction Temperature
300
150
150
2
°C
°C
°C
kV
kV
T
STG
Storage Temperature
−55
Human Body Model (HBM)
ESD
Charged Device Model (CDM)
2
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Using Mil Std. 883E, method 3015.7 (Human Body Model) and EIAJ/JESD22C101−A (Charged Device Model).
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Input Voltage
Condition
Min
Typ
Max
5.5
Unit
VIN
1.8
V
VIN < 2 V
4.5 & 5.5,VIN = 3.6 V
30
IL
Load Current
mA
100
+85
TA
Ambient Temperature
−40
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Refer to Figure 9 in Typical Performance Characteristics
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3
FAN5602
Table 4. DC ELECTRICAL CHARACTERISTICS
V
IN
= 2.7 V to 5.5 V, C = C = 1 mF, C = C
= 10 mF, ENABLE = V , T = −40°C to +85°C unless otherwise noted. Typical values are
OUT IN A
1
2
IN
at T = 25°C.
A
Symbol
Parameter
Condition
Min
1.5
Typ
1.7
Max
2.2
Unit
v
Input Under−Voltage Lockout
Output Voltage
V
UVLO
VIN ≥ 0.75 x VNOM, 0 mA < ILOAD < 100 mA
V
OUT
VNOM
0.97 x VNOM
1.03 x VNOM
V
IQ
Quiescent Current
170
0.1
300
1.0
mA
mA
VIN ≥ 1.1 x VNOM, ILOAD = 0 mA
ENABLE = GND
Off Mode Supply Current
Output Short−Circuit
VOUT < 150 mV
200
mA
VIN = 0.85 x VNOM, ILOAD
30 mA
=
4.5, 5.0 V
4.5, 5.0 V
80
Efficiency
%
VIN = 1.1 x VNOM, ILOAD
30 mA
=
92
f
Oscillator Frequency
TA = 25°C
0.7
1.0
1.3
MHz
°C
OSC
Thermal Shutdown Threshold
T
145
15
SD
Thermal Shutdown Threshold
Hysteresis
T
°C
SDHYS
ENABLE Logic Input High
Voltage
V
1.5
−1
V
V
IH
ENABLE Logic Input Low
Voltage
V
0.5
1
IL
ENABLE Logic Input Bias
Current
I
ENABLE =VIN or GND
mA
EN
VIN = 0.9 x VNOM, ILOAD = 0 mA,10% to
90%
t
VOUT Turn−On Time
0.5
10
ms
ON
VOUT Ripple
VIN = 2.5 V, ILOAD = 200 mA
mVpp
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
FAN5602
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, V
= 4.5 V unless otherwise noted.
A
OUT
80
180
160
140
120
100
80
70
60
50
40
30
60
20
10
0
40
20
0
1
2
3
4
5
6
1.5
2.5
3.5
4.5
5.5
Input Voltage (V)
Input Voltage (V)
Figure 4. Quiescent Current vs. Input Voltage
Figure 5. Shutdown Current vs. Input Voltage
100
90
80
70
60
50
4.55
4.50
I
V
= 100mA
= 4.5V
LOAD
OUT
4.45
4.40
4.35
4.30
Load Current = 10mA
Load Current = 50mA
Load Current = 100mA
Load Current = 150mA
40
30
20
2.500
3.000
3.500
4.000
4.500
5.000
5.500
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Voltage
Input Voltage (V)
Figure 7. Efficiency vs. Input Voltage
Figure 6. Line Regulation
4.6
4.5
4.4
4.3
4.2
4.1
700.0
600.0
V
= 3.6V
DV
OUT
DV
OUT
< 10%
< 3%
IN
500.0
400.0
300.0
200.0
100.0
0.0
4.0
1
2
2.5
3
3.5
4
4.5
5
50
100
150
200
250
300
350
Load Currrent (mA)
Input Voltage (V)
Figure 8. Load Regulation
Figure 9. Output Current Capacity vs. Input voltage
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5
FAN5602
4.5
4.45
4.4
5
4.5
4
Load Current = 10mA
3.5
3
Load Current = 10mA
Load Current = 50mA
Load Current = 100mA
Load Current = 150mA
Load Current = 200mA
4.35
4.3
2.5
2
−60 −40 −20
0
20
40
60
80
100 120 140
2
3
4
5
6
Input Voltage (V)
Ambient Temperature (C)
Figure 10. Output Voltage vs. Input Voltage
Figure 11. Output Voltage vs. Ambient Temperature
1.4
1.3
1.2
1.1
1
80
75
70
65
60
VIN = 3.6V
0.9
0.8
0
50
100
150
200
250
300
2
2.5
3
3.5
4
4.5
5
5.5
6
Figure 13. Enable Threshold vs. Input Voltage
Figure 12. Peak Efficiency vs. Load Current
5.5
Mode 1
5
4.5
Mode 2
4
3.5
3
Mode 3
2.5
2
Mode 4
0
50
100
150
200
Load Current (mA)
Figure 14. Mode Change Threshold and Hysteresis
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6
FAN5602
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
T = 25°C, C = C
= 10 mF, C = 1 mF, V
= 4.5 V unless otherwise noted.
A
IN
OUT
B
OUT
I
= 200mA
I
= 200mA
OUT
OUT
= 3.6V
V
= 2.5V
V
IN
IN
Time (100 μs/div)
Time (100 μs/div)
Figure 15. Output Ripple
Figure 16. Output Ripple
I
= 200mA
OUT
I
= 300mA
OUT
V
= 4.2V
IN
V
= 2.5V
IN
Time (100 μs/div)
Time (100 μs/div)
Figure 17. Output Ripple
Figure 18. Output Ripple
I
= 300mA
= 4.2V
I
= 300mA
OUT
OUT
V
V
= 3.6V
IN
IN
Time (100 μs/div)
Time (100 μs/div)
Figure 19. Output Ripple
Figure 20. Output Ripple
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7
FAN5602
FUNCTIONAL DESCRIPTION
FAN5602 is a high−efficiency, low−noise switched
to a half of the input voltage. In pumping phase, the flying
capacitors are placed in parallel. The input is connected to
the bottom the capacitors so that the top of the capacitors is
boosted to a voltage that equals VIN/2 + VIN, i.e., 3/2 x VIN.
By connecting the top of the capacitors to the output, one can
ideally charge the output to 3/2 x VIN. If 3/2 x VIN is higher
than the needed VOUT, the linear regulation loop adjusts the
on− resistance to drop some voltage. Boosting the voltage of
the top of the capacitors to 3/2 x VIN by connecting VIN the
bottom of the capacitors, boosts the power efficiency 3/2
times. In 2:3 mode, the ideal power efficiency is VOUT/1.5 x
VIN. For example, if VIN = 2 V, VOUT = 2 x VIN = 4 V, the ideal
power efficiency is 100%.
When 2 x VIN > VOUT > 1.5 x VIN, the 1:2 mode (step−up)
shown in Figure 23 is used. Both in the charging phase and
in pumping phase, two flying capacitors are placed in
parallel. In charging phase, the capacitors are charged to the
input voltage. In the pumping phase, the input volt− age is
placed to the bottom of the capacitors. The top of the
capacitors is boosted to 2 x VIN. By connecting the top of the
capacitors to the output, one can ideally charge the output to
2 x VIN. Boosting the voltage on the top of the capacitors to
2VIN boosts the power efficiency 2 times. In 1:2 mode, the
ideal power efficiency is VOUT/2 x VIN. For example, VIN =
2V, VOUT = 2 x VIN = 4V, the ideal power efficiency is 100%.
When 3 x VIN > VOUT > 2 x VIN, the 1:3 mode (step−up)
shown in Figure 24 is used. In charging phase, two flying
capacitors are placed in parallel and each is charged to VIN.
In the pumping phase, the two flying capacitors are placed
in series and the input is connected to the bottom of the series
connected capacitors. The top of the series connected
capacitors is boosted to 3 x VIN. The ideal power efficiency
is boosted 3 times and is equal to VOUT/ 3VIN. For example,
VIN = 1 V, VOUT = 3 x VIN = 3 V, the ideal power efficiency is
100%. By connecting the output to the top of the series
connected capacitors, one can charge the output to 3 x VIN.
The internal logic in the FAN5602 monitors the input and
the output compares them, and automatically selects the
switch configuration to achieve the highest efficiency.
The step−down modes 3:2, 2:1, and 3:1 can be under−
stood by reversing the function of VIN and VOUT in the above
discussion.
capacitor DC/DC converter capable of step−up and
step−down operations. It has seven built−in switch
configurations. Based on the ratio of the input voltage to the
output volt− age, the FAN5602 automatically reconfigures
the switch to achieve the highest efficiency. The regulation
of the output is achieved by a linear regulation loop, which
modulates the on−resistance of the power transistors so that
the amount of charge transferred from the input to the flying
capacitor at each clock cycle is controlled and is equal to the
charge needed by the load. The current spike is reduced to
minimum. At light load, the FAN5602 automatically
switches to Pulse Frequency Modulation (PFM) mode to
save power. The regulation at PFM mode is achieved by
skipping pulses.
Linear Regulation Loop
The FAN5602 operates at constant frequency at load
higher than 10 mA. The linear regulation loop consisting of
power transistors, feedback (resistor divider), and error
amplifier is used to realize the regulation of the out− put
voltage and to reduce the current spike. The error amplifier
takes feedback and reference as inputs and generates the
error voltage signal. The error voltage signal is then used as
the gate voltage of the power transistor and modulates the
on−resistance of the power transistor and, therefore, the
charge transferred from the input to the output is controlled
and the regulation of the output is realized. Since the charge
transfer is controlled, the FAN5602 has a small ESR spike.
Switch Array
Switch Configurations
The FAN5602 has seven built−in switch configurations,
including 1:1, 3:2, 2:1 and 3:1 for step−down and 2:3, 1:2
and 1:3 for step−up.
When 1.5 x VOUT > VIN > VOUT, the 1:1 mode shown in
Figure 21 is used. In this mode, the internal oscillator is
turned off. The power transistors connecting the input and
the output become pass transistors and their gate voltages are
controlled by the linear regulation loop, the rest of power
transistors are turned off. In this mode, the FAN5602
operates exactly like a low dropout (LDO) regulator and the
ripple of the output is in the micro−volt range.
The built−in modes improve power efficiency and extend
the battery life. For example, if VOUT = 5 V, mode 1:2 needs
a minimum VIN = 2.5 V. By built−in 1:3 mode, the minimum
battery voltage is extended to 1.7 V.
When 1.5 x VIN > VOUT > VIN, the 2:3 mode (step−up)
shown in Figure 22 is used. In the charging phase, two flying
capacitors are placed in series and each capacitor is charged
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8
FAN5602
Switch Array Modes
TOP
TOP
S1A
S1A
S2A
C1+
C1+
C1−
C1+
C1−
S1A
MID
C2
C1
C1
S3A
S2A
MID
S3B
S4B
S5
C1−
GND
GND
Figure 21. Mode 1 (1:1)
Figure 22. Mode 2 (2:3 or 3:2) All Switches Set for
Phase 1 and Reverse State for Phase 2
TOP
TOP
S1A
S2A
C2+
C1+
S1A
S2A
S1B
S2B
C2+
C1+
S2B
MID
S5
C2
C1
MID
C1
S3B
S4B
C2
S3A
S4A
S3B
S4B
C2−
S4A
C1−
C2−
C1−
GND
Figure 23. Mode 3 (1:2 or 2:1) All Switches Set for
Phase 1 and Reverse State for Phase 2
Figure 24. Mode 4 (1:3 or 3:1) All Switches Set for
Phase 1 and Reverse State for Phase 2
Light−Load Operation
Short Circuit
The power transistors used in the charge pump are very
large in size. The dynamic loss from the switching the power
transistors is not small and increases its propor− tion of the
total power consumption as the load gets light. To save
power, the FAN5602 switches, when the load is less than
10mA, from constant frequency to pulse−skip− ping mode
(PFM) for modes 2:3(3:2), 1:2(2:1) and 1:3(3:1), except
mode 1:1. In PFM mode, the linear loop is disabled and the
error amplifier is turned off. A PFM comparator is used to
setup an upper threshold and a lower threshold for the
output. When the output is lower than the lower threshold,
the oscillator is turned on and the charge pump starts
working and keeps delivering charges from the input to the
output until the output is higher than the upper threshold.
The oscillator shuts off power transistors and delivers the
charge to the output from the output capacitor. PFM
operation is not used for Mode 1:1, even if at light load.
Mode 1:1 is designed as an LDO with the oscillator off. The
power transistors at LDO mode are not switching and
therefore do not have the dynamic loss.
When the output voltage is lower than 150mV, the
FAN5602 enters short−circuit condition. In this condition,
all power transistors are turned off. A small transistor
shorting the input and the output turns on and charges the
output. This transistor stays on as long as the VOUT < 150 mV.
Since this transistor is very small, the current from the input
to the output is limited. Once the short at the output is
eliminated, this transistor is large enough to charge the
output higher than 150mV and the FAN5602 enters
soft−start period.
Soft Start
The FAN5602 uses a constant current, charging a low−
pass filter to generate a ramp. The ramp is used as reference
voltage during the startup. Since the ramp starts at zero and
goes up slowly, the output follows the ramp and inrush
current is restricted. When the ramp is higher than bandgap
voltage, the bandgap voltage supersedes ramp as reference
and the soft start is over. The soft start takes about 500 ms.
Thermal Shutdown
The FAN5602 goes to thermal shutdown if the junction
temperature is over 150°C with 15°C hysteresis.
Switching from linear operation to PFM mode
(ILOAD < 10 mA) and from PFM to linear mode
(ILOAD > 10 mA) is automatic, based on the load current,
which is monitored all the time.
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9
FAN5602
APPLICATION INFORMATION
Using the FAN5602 to Drive LCD Backlighting
3% output regulation, it is not a problem. The backlight and
flash LEDs still produce opti− mal brightness at the reduced
regulation. When building this circuit, use ceramic
capacitors with low ESR. All capacitors should be placed as
close as possible to the FAN5602 in the PCB layout.
The FAN5602 4.5V option is ideal for driving the back−
lighting and flash LEDs for portable devices. One FAN5602
device can supply the roughly 150mA needed to power both
the backlight and the flash LEDs. Even though drawing this
much current from the FAN5602 drives the part out of the
FOL216CIW
FOL625CIW
VIN
VOUT
BATTERY
3.2 to 4.2V
10μF
1μF
10μF
1μF
FAN5602
50
50
50
50
20
FLASH
BACKLIGHT
Figure 25. Circuit for Backlighting / Flash Application
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3x3, 0.65P
CASE 511CD
ISSUE O
1
SCALE 2:1
DATE 29 APR 2014
NOTES:
A
B
E
L
L
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
PIN ONE
REFERENCE
ALTERNATE
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
0.80
0.05
2X
0.10
C
A
A1
A3
b
0.70
0.00
0.20 REF
A3
EXPOSED Cu
MOLD CMPD
2X
0.10
C
0.25
0.35
TOP VIEW
D
D2
E
3.00 BSC
2.05
2.25
DETAIL B
A
3.00 BSC
A1
0.05
0.05
C
E2
e
K
L
L1
1.10
0.65 BSC
0.20
0.30
0.00
1.30
DETAIL B
ALTERNATE
−−−
0.50
0.15
CONSTRUCTIONS
C
A3
SEATING
PLANE
NOTE 4
A1
C
SIDE VIEW
D2
GENERIC
MARKING DIAGRAM*
DETAIL A
8X
L
XXXXX
XXXXX
ALYWG
G
1
4
E2
A
L
= Assembly Location
= Wafer Lot
Y
= Year
W
G
= Work Week
= Pb−Free Package
K
5
8
8X
b
e/2
e
0.10
0.05
C
C
A
B
(Note: Microdot may be in either location)
NOTE 3
BOTTOM VIEW
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
RECOMMENDED
SOLDERING FOOTPRINT*
8X
0.63
2.31
PACKAGE
OUTLINE
3.30
1.36
1
8X
0.65
PITCH
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON84944F
WDFN8, 3X3, 0.65P
PAGE 1 OF 1
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