FAN6080HMX [ONSEMI]
Offline Quasi-Resonant PWM Controller;
| 型号： | FAN6080HMX |
| 厂家： | 
ONSEMI |
| 描述： | Offline Quasi-Resonant PWM Controller |
| 文件： | 总16页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Offline Quasi-Resonant
PWM Controller
FAN6080HMX
The FAN6080HMX is an advanced PWM controller aimed at
3
achieving power density of ≥10 W/in in universal input range AC/DC
flyback isolated power supplies. It incorporates Quasi−Resonant (QR)
control with proprietary valley switching. QR switching provides high
efficiency by reducing switching losses.
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®
FAN6080HMX features MWSAVER burst mode operation with
extremely low operating current (300 mA) and significantly reduces
standby power consumption to meet the most stringent efficiency
regulations such as Energy Star’s 5−Star Level and CoC Tier II
specifications.
SOIC8
CASE 751EB
FAN6080HMX includes several features aimed at optimizing
efficiency, EMI and protections. FAN6080HMX has a wide blanking
frequency range that improves light load efficiency. The maximum
operating frequency is optimized to minimize components
temperature while maximizing the full load efficiency. The minimum
peak current is also set to optimize to balance the standby power
consumption and the audio noise. It also includes several rich
programmable protection features such as over−voltage protection
(OVP) and precise constant output current regulation (CC).
FAN6080HMX is available in SOIC8 package.
MARKING DIAGRAM
6080H
ALYWX
•
6080H= Specific Device Code
Features
A
L
= Assembly Location
= Wafer Lot Traceability
• High Efficiency Across Wide Input and Output Conditions in a Small
Form Factor
YW = Date Code
X
= Manufacture Flow
• Quasi−Resonant Switching Operation with Wide Blanking Frequency
Range (24 kHz~125 kHz)
•
= Pb Free
• Optimization Transformer Design for Adaptive Charger Application
• Precise Constant Output Current Regulation with Programmable Line
Compensation
PIN ASSIGNMENT
HV
NC
1
2
3
4
8
7
6
5
GND
FB
• MWSAVER Technology for Ultra Low Standby Power Consumption
(<20 mW)
• Forced and Inherent Frequency Modulation of Valley Switching for
Low EMI Emissions and Common Mode Noise
• Built−In and User Configurable Over−Voltage Protection (OVP) and
Under−Voltage Protection (UVP)
FAN6080HMX
CS
VS
GATE
VDD
• Built−In Over−Temperature Protection (OTP)
• Fully Programmable Brown−In and Brownout Protection
• Built−In High−Voltage Startup to Reduce External Components
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
Typical Applications
• Battery Charges for Smart Phones, Feature Phones, and Tablet PCs
• AC−DC Adapters for Portable Devices or Battery Chargers that
Require CV/CC Control
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
August, 2020 − Rev. 0
FAN6080HMX/D
FAN6080HMX
RSNS CSNS
TX
LF
DR
CO
NP
NS
VO
CSNP
RSNP
Bridge
Fuse
XC
Choke
CBLK1
CBLK2
AC IN
RHV1
DSNP
RBias1
RBias2
RHV2
Photo
CComp2
coupler
RF1
RGR
HV
GATE
RComp
CComp1
Shunt
Regulator
RGF
DG
FAN6080HMX
CS
RF2
NA
RCS.COMP
CCSF
FB
RCS
VDD
VS
GND
DAUX
Photo
CFB
RVSH
coupler
CVDD
CVS
RVSL
Figure 1. FAN6080HMX Typical Application
HV
1
HV
Brown−In
Burst Mode
V
FB
VDD UVLO
HV
Start−up
VDD UVLO
17.2 V / 6 V
I
Brown OUT
VS
VDD UVLO
V
V
V
OVP Fault
UVP Fault
OVP Fault
DD
Auto−Restart
Protection
S
S
VDD
GND
5
8
Debounce
V
OVP Fault
DD
OTP Fault
V
VDD−OVP
V
VS−SH
V
OVP Fault
UVP Fault
S
S/H
VS Protection
VDD
Maximum
On Time
V
S
S/H = Sampling and Hold
Driver
Control
4
GATE
D
Q
Q
VD
Valley
Forced Frequency
Modulation
OSC
6
CLK
VS
V
FB
C
Detection
I
VS
t
DIS
V
CS−LIM
5 V
V
V
Fault
CS Protection
CS
5.325 V
I
COMP
Z
FB
V
CS
3
CS
LEB
7
A
V
CS
FB
Peak Value
V
CS−IMIN
t
A
V−CC
I
O
Estimator
DIS
V
CS
Figure 2. FAN6080HMX Block Diagram
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2
FAN6080HMX
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
HV
Description
1
2
3
High Voltage. This pin connects to DC bus for high−voltage startup.
No Connect.
NC
CS
Current Sense. This pin connects to a current−sense resistor to sense the MOSFET current for
Peak−Current−Mode control for output regulation. The current sense information is also used to
estimate the output current for CC regulation.
4
5
6
GATE
VDD
VS
PWM Signal Output. This pin has an internal totem−pole output driver to drive the power MOSFET. The
gate driving voltage is internally clamped at 8 V.
Power Supply. IC operating current and MOSFET driving current are supplied through this pin. This pin is
typically connected to an external VDD capacitor.
Voltage Sense. The VS voltage is used to detect resonant valleys for quasi−resonant switching. This pin
detects the output voltage information and diode current discharge time based on the auxiliary winding
voltage. It also senses input voltage for Brown−out protection.
7
8
FB
Feedback. Typically Opto−Coupler is connected to this pin to provide feedback information to the internal
PWM comparator. This feedback is used to control the duty cycle in CV regulation.
GND
Ground.
MAXIMUM RATINGS
Symbol
Rating
Value
600
Unit
V
V
HV
Maximum Voltage on HV Pin
DC Supply Voltage
V
VDD
60
V
V
Maximum Voltage on GATE Pin
Maximum Voltage on FB Pin
−0.3 to 30
−0.3 to 6.5
−0.3 to 6
770
V
GATE
V
V
FB
V
Maximum Voltage on Low Power Pins (Except Pin 1, Pin 4, Pin 5, Pin 7)
V
max
P
D
Power Dissipation (TA = 25_C)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Top)
Operating Junction Temperature
mW
°C/W
°C/W
°C
q
162
JA
Y
20
JT
T
J
−40 to +150
−40 to +150
2.0
T
Storage Temperature Range
°C
STG
ESD
Human Body Model, JEDEC:JESD22_A114
Charged Device Model, JEDEC:JESD22_C101
kV
0.5
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All voltage values, except differential voltages, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
RECOMMENDED OPERATING RANGES
Symbol
Rating
Min
50
7
Max
500
50
Unit
V
V
HV
HV Pin Supply Voltage
VDD Pin Supply Voltage
VS Pin Supply Voltage
CS Pin Supply Voltage
FB Pin Supply Voltage
Operating Temperature
V
VDD
V
V
0.7
0
2.9
V
VS
CS
V
0.85
4.55
+85
V
V
FB
0
V
T
A
−40
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
FAN6080HMX
ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to 125°C, V = 15 V; unless otherwise noted)
J
J
DD
Symbol
Parameter
Test Conditions
Min
Typ
Max Unit
HV SECTION
I
Supply Current Drawn from HV Pin
Leakage Current Drawn from HV Pin
Brown−In Threshold Voltage
V
V
= 120 V, V = 0 V
1.2
0
2.0
0.8
92
10
10
mA
mA
V
HV
HV
DD
I
= 600 V, V = V
+ 1 V
HV−LC
HV
DD
DD−OFF
V
R
= 360 kW
75
115
Brown−IN
HV
V
DD
SECTION
V
Turn−On Threshold Voltage
Turn−Off Threshold Voltage
Output Short Detection Threshold (Note 3)
Startup Current
V
V
Rising
Falling
15.3 17.2 18.7
V
V
DD−ON
DD−OFF
DD
V
5.5
6.0
−
6
6.5
−
6.5
7.0
60
3
DD
V
V
DD−VS−DET
I
V
DD
= V − 0.16 V
DD−ON
mA
mA
DD−ST
I
Operating Supply Current
V
CS
V
DD
= 5.0 V, V = 3 V, V = 3 V,
= 15 V, C
−
2
DD−OP
VS
GATE
FB
= 1 nF
I
Burst−Mode Operating Supply Current
V
V
C
= 0.3 V, V = 0 V, V = 0 V;
−
−
300
100
600
−
mA
DD−Burst
CS
DD
VS
FB
= V
→ V
→ 10 V,
DD−ON
DD−OVP
= 1 nF
GATE
t
I
Operation Enable Debounce Time
Over−Voltage−Protection Level
V
FB
< V
ms
V
IDD−Burst
DD−Burst
FB−Burst−L
V
V
V
56.2 57.2 58.2
VDD−OVP
DD
t
Over−Voltage−Protection Debounce Time
−
70
150
ms
D−VDDOVP
DD
OSCILLATOR SECTION
f
Maximum Blanking Frequency
V
V
V
V
> V
, V
115
21
125
24
135
27
kHz
kHz
kHz
kHz
kHz
ns
BNK−MAX
FB
FB
VS
VS
FB−BNK−HL−H
FB−BNK−LL−H
, V
FB−BNK−HL−L FB−BNK−LL−L
f
Minimum Blanking Frequency
< V
BNK−MIN
f
f
Minimum Frequency for DCM
= 0 V
= 1 V
19
21.5
21.5
100
270
2.5
24
OSC−MIN−DCM
OSC−MIN−CRM
Minimum Frequency for CRM
19
24
F
Maximum Blanking Frequency Limit for High Line
Forced Frequency Modulation Range
Forced Frequency Modulation Period (Note 3)
90
110
325
2.9
MAX−HL
Dt
Dt
V
V
> V
> V
215
2.1
FM−Range
FM−Period
FB
FB−Burst−H
ms
FB
FB−Burst−H
FEEDBACK INPUT SECTION
Z
FB Pin Input Impedance
37.0 40.5 43.5
1/3 1/3.5 1/4
kW
V/V
V
FB
A
Internal Voltage Attenuator of FB Pin (Note 3)
FB Pin Pull−Up Voltage
V
= 120 V, V = 0 V
V
HV DD
V
FB Pin Open
4.55 5.325 6.10
2.30 2.40 2.50
1.90 2.00 2.10
1.90 2.00 2.10
1.50 1.60 1.70
0.90 1.05 1.20
0.85 1.00 1.15
FB−Open
FB−BNK−HL−H
V
Modulated Blanking Frequency Upper/Lower V
Limit for High Line
V
FB
V
V
V
FB−BNK−HL−L
Modulated Blanking Frequency Upper/Lower V
Limit for Low Line
V
FB−BNK−LL−H
FB
V
V
FB−BNK−LL−L
V
FB Threshold to Enable/Disable Gate Drive in
Burst Mode
V
V
Rising
Falling
V
FB−Burst−H
FB
V
V
FB−Burst−L
FB
VOLTAGE−SENSE SECTION
I
Maximum VS Source Current Capability
−
−
3
mA
VS−MAX
t
VS Sampling Blanking Time 1 after GATE Pin
Pull−Low
V
V
< 2.0 V
> 2.2 V
0.84
1.0
1.23
ms
VS−BNK1
FB
t
VS Sampling Blanking Time 2 after GATE Pin
Pull−Low
1.45 1.80 2.15
ms
VS−BNK2
FB
V
VS Clamping Voltage (Note 3)
−
0
−
V
S−Clamp
t
Delay from VS Voltage Zero Crossing to PWM ON
(Note 3)
V
VS
= 0 V, C
= 1 nF
100
175
250
ns
ZCD−to−PWM
GATE
I
VS Source Current Threshold to Enable
1.290 1.440 1.590 mA
VS−HL
V
from Low to High Line
FB−BNK−HL−H/L
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4
FAN6080HMX
ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to 125°C, V = 15 V; unless otherwise noted) (continued)
J
J
DD
Symbol
VOLTAGE−SENSE SECTION
VS Source Current Threshold to Enable
Parameter
Test Conditions
Min
Typ
Max Unit
I
1.208 1.350 1.492 mA
VS−LH
V
from High to Low Line
FB−BNK−LL−H/L
t
Line Detection Debounce Time for I
11
17
23
ms
D−VS−LD
VS−LH
I
VS Source Current Threshold to Enable Brown−out Set I = 2.161 mA at 264 V
,
370
450
520
mA
VS−Brown−Out
VS
AC
brown out level = 55 V
AC
t
Brown−Out Debounce Time
12.5 16.5
21
−
ms
D−Brown−Out
N
Brown−Out Recheck Debounce Cycle Counts after
−
3
Cycle
Brown−Out
No Gate Signal during t
D−Brown−Out
V
Output Over−Voltage−Protection with Vs Sampling
Voltage
2.9
3.0
3.1
V
VS−OVP
V
Output Under−Voltage−Protection with Vs Sam-
pling Voltage
0.260 0.300 0.340
V
VS−UVP−L
N
Output Over−Voltage−Protection Debounce Cycle
Counts
Enabled during I
operation
operation
−
−
3
3
−
−
Cycle
Cycle
ms
VS−OVP
VS−UVP
DD−Burst
N
Output Under−Voltage−Protection Debounce Cycle Enabled during I
Counts
DD−Burst
t
Output Under−Voltage Protection Blanking Time at
start−up
25
−
40
3
55
−
VS−UVP−BLANK
N
Auto−Restart 3 Cycles Mode Counts for Low Line
V
VS−SH
< V
, V
> V ,
VS−OVP
Cycle
VDD−Hiccup−L
VS−UVP VS−SH
Initial state before startup,
Enabled by I < I
VS
VS−LH
N
Auto−Restart 6 Cycles Mode Counts for High Line
V
< V
, V
VS−HL
> V
−
−
6
−
−
Cycle
VDD−Hiccup−H
VS−SH
VS−UVP VS−SH
VS
VS−OVP
Enabled by I > I
OVER−TEMPERATURE PROTECTION SECTION
Threshold Temperature for Over−Temperature−Protection (Note 3)
CURRENT−SENSE SECTION
T
OTP
140
°C
V
Current Limit Threshold Voltage
Current Sense Threshold Voltage
GATE Output Turn−Off Delay
Leading−Edge Blanking Time
FB Pin Open
0.85 0.90 0.95
0.18 0.20 0.22
V
V
CS−LIM
V
CS−IMIN
t
−
−
50
100
−
ns
ns
PD
t
300
LEB
CONSTANT CURRENT CORRECTION SECTION
I
High Line Compensation Current
Low Line Compensation Current
I
I
= 2.391 mA
90
32
100
36
110
40
mA
mA
COMP−H
VS
I
= 814 mA
COMP−L
VS
CONSTANT CURRENT ESTIMATOR SECTION
V
Constant Current Control Reference Voltage
−
1.60
−
V
V
REF−CC
V
Closed Loop of Constant Current Control
Reference Voltage
V
T = V
× A
× A × T /
DIS
2.118 2.184 2.250
REF−CC−CL
REF−CC−CL
V−CC
PK
REF−CC
A
PK
Peak Value Amplifying Gain (Note 3)
−
3.3
−
V/V
GATE SECTION
V
Gate Output Voltage Low
Rising Time
0
−
1.5
180
70
V
GATE−L
t
r
V
V
= 0 V, V = 0 V, C
= 1 nF
= 1 nF
100
30
135
50
ns
ns
CS
VS
GATE
t
f
Falling Time
= 0 V, V = 0 V, C
VS
CS
GATE
T = 25°C
J
V
Gate Output Clamping Voltage
Maximum On Time
V
DD
V
FB
= 25 V
6.8
8.0
22
8.5
V
GATE−CLAMP
t
= 3 V, V = 0.3 V
18.5
25.5
ms
ON−MAX
CS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Design guaranteed.
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5
FAN6080HMX
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. Operating Supply Current (IDD−OP
vs. Temperature
)
Figure 4. Burst Mode Operating Supply Current
(IDD−Burst) vs. Temperature
Figure 5. Startup Current (IDD−ST) vs. Temperature
Figure 6. Closed Loop of Constant Current Control
Reference Voltage (VREF−CC−CL) vs. Temperature
Figure 7. Turn−ON Threshold Voltage (VDD−ON
vs. Temperature
)
Figure 8. Turn−Off Threshold Voltage (VDD−OFF
vs. Temperature
)
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6
FAN6080HMX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Figure 9. VDD Over−Voltage Protection Level
Figure 10. Supply Current drawn from HV Pin (IHV
vs. Temperature
)
(VDD−OVP) vs. Temperature
Figure 11. Maximum Blanking Frequency
(fBNK−MAX) vs. Temperature
Figure 12. Minimum Blanking Frequency
(fBNK−MIN) vs. Temperature
Figure 13. Minimum Frequency for DCM
(fOSC−MIN−DCM) vs. Temperature
Figure 14. Forced Frequency Modulation Range
(DtFM−Range) vs. Temperature
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7
FAN6080HMX
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Figure 15. Current Limit Threshold Voltage
Figure 16. Current Sense Threshold Voltage
(VCS−IMIN) vs. Temperature
(VCS−LIM) vs. Temperature
Figure 17. Output Over−Voltage Protection with
VS Sampling Voltage (VVS−OVP) vs. Temperature
Figure 18. Output Under−Voltage Protection with
VS Sampling Voltage (VVS−UVP−L) vs. Temperature
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8
FAN6080HMX
OPERATION PRINCIPLE
FAN6080HMX is an offline PWM controller which
IDS
operates in a quasi−resonant (QR) mode and significantly
enhances system efficiency and power density. The
maximum operating blanking frequency is optimized to
minimize the components temperature while maximizing
system efficiency. It offers constant output voltage (CV)
regulation through opto−coupler feedback circuitry.
VDS
Line voltage compensation gain can be programmed
using an external resistor to minimize the effect of line
voltage variation on output current regulation due to
turn−off delay of the gate drive circuit. Minimum peak
Blanking window
Blanking window
Time−out Window
current (I
), which controls the burst mode entry/exit and
MIN
improves light load efficiency, is also optimized to make a
balance between the standby power consumption and
audible noise.
Figure 20. Blanking Window and Time−out Window
Limit the Frequency Range
Valley Switching
Valley Detection
Quasi−resonant (QR) switching is a method to reduce
MOSFET switching losses especially in high line. In order
to perform QR turn−on of the Primary MOSFET, the valley
of the resonance occurring between transformer
In FAN6080HMX, valley detection is done by detecting
the downward zero−crossing of the VS pin. The VS pin is
connected to the transformer auxiliary winding through a
resistor divider configured with R
The effective resistance, R (R
and R
.
VSH
VSL
magnetizing inductance (L ) and MOSFET effective output
m
//R ) will form an
VS VSH VSL
capacitance (C
) must be detected. Typically, during the
oss.eff
RC filter with pin capacitance, C and delay the detection
VS
turn−off time, there can be several valleys as the load
reduces as shown in Figure 19. In order to limit the
maximum switching frequency, a blanking window is
introduced. To limit the minimum switching frequency, the
maximum allowable time or Time−out window is fixed.
These two windows allow the flyback converter to operate
in a narrow user−configurable frequency range. Figure 20
shows these two windows in a switching cycle. In
by T . Furthermore, there will be a logic propagation delay
RC
from VS zero−crossing detection (VS−ZCrD) to IC Gate
turn on and a MOSFET gate drive propagation delay from
GATE pin to MOSFET turn−on. We can assume the sum of
these propagation delays to be t . Typical values
ZCD−to−PWM
of these parameters are T (30 − 50 ns) and t
RC
ZCD−to−PWM
(100 − 150 ns). As soon as blanking time, t
expires, and
BNK
VS−ZCrD has occurred, the turn−on decision is made and
the IC gate can turn on. For any system, if Equation 1 holds
true, and the turn−on decision is made at VS−ZCrD, perfect
valley switching occurs.
FAN6080HMX, the time−out window (f
) is
OSC−MIN−DCM
the same as the minimum frequency for CRM
(f ), which is 21.5 kHz.
OSC−MIN−CRM
Tresonance
TRC ) tZCD*to*PWM
+
(eq. 1)
4
However, if T
/ 4 is larger than T
+
RC
resonance
IDS
t
, the switching occurs away from the valley
ZCD−to−PWM
causing higher losses. The time period of resonant ringing
depends on L and C . Typically, T lies
m
oss.eff
resonance
between 1 ms and 1.5 ms depending on the system
parameters. Hence, the switching may occur at a point
different from the valley depending on the system.
Forced Frequency Modulation (FFM)
VDS
In order to maintain good EMI performance for low and
high lines, forced frequency modulation is provided by
modulating the turn−on instant of the next switching cycle
near the valley point.
Blanking Window
Figure 19. Valleys Formed by Resonant Ringing
Increase in Number as Load Decreases
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9
FAN6080HMX
Line Voltage Detection
From Equations 3 and 4, R
can be determined
VSH
The FAN6080HMX indirectly senses the line voltage
through the VS pin while the MOSFET is turned on. During
MOSFET turn−on period, the auxiliary winding voltage,
considering tolerances of I
and I
as
VS−HL
VS−LH
130 VAC
215 VAC
NA
NA
@
t RVSH
t
@
(eq. 5)
NP IVS*LH.MIN
NP IVS*HL.MAX
V
, is proportional to the input bulk capacitor voltage,
, due to the transformer coupling between the primary
AUX
V
BLK
where I
is 1.208 mA and I
is
VS−HL.MAX
VS−LH.MIN
and auxiliary windings. During the MOSFET conduction
time, the line voltage detector can detect the line voltage
using Equation 2.
1.590 mA.
CV/CC Operation Mode
Figure 21 shows the simplified CV PWM control circuit
of FAN6080HMX. In constant voltage (CV) regulation, the
output voltage is sensed via a voltage divider and compared
with the internal reference of shunt−regulator to generate a
compensation signal. The compensation signal is
transferred to the primary side through an opto−coupler and
fed to FB pin. The FB signal is level shifted, and scaled down
by an internal attenuator AV to generate the COMV signal.
The COMV signal is then applied to the PWM comparator
to determine the PWM duty cycle, as shown in Figure 21.
In constant current (CC) regulation, the output current
estimator calculates the output current using the transformer
primary side current and the rectifier diode conduction time
which is sensed on the VS pin. By comparing the estimated
output current with an internal reference signal, COMI
signal is generated, which determines the PWM duty cycle,
as shown in Figure 21.
VBLK NA
IVS
+
@
(eq. 2)
RVSH NP
Modulated Blanking Frequency
The FAN6080HMX is an adaptive hybrid QR PWM
controller that adaptively changes its control method
according to the load condition (valley switching with fixed
blanking frequency at heavy and light load and valley
switching with modulated blanking frequency at medium
load) to maximize the efficiency. Also, low line blanking
frequency curve is separated from high line blanking
frequency curve to reduce conduction loss at low line and
switching loss at high line.
In case of high line, the blanking frequency f
BNK
(= 1 / t
) for valley detection is fixed by f
BNK
BNK−MAX
(125 kHz) at heavy load condition above V = 2.4 V, where
FB
t
is the blanking time (= the blanking window period).
BNK
Two internal comparators are used to compare the COMV
and COMI signals with sawtooth waveform (V
For medium load condition between V = 2.0 V and
FB
) in order
SAW
V
FB
= 2.4 V, f
is modulated as a function of V
BNK FB
to determine the PWM duty cycle. As shown in Figure 21,
the outputs of the two comparators are combined with an OR
gate to determine the MOSFET turn−off instant. The lower
between the COMV and COMI signals determines the
PWM duty cycle. In CV mode, COMV determines the PWM
duty cycle while COMI signal is saturated to high level.
Whereas, in CC mode, COMI determines the PWM duty
cycle while COMV signal is saturated to high level.
corresponding to load. f
decreases in order to reduce the
BNK
switching loss, as load decreases. For light load condition
below V = 2.0 V, f is fixed by f (24 kHz). In
FB
BNK
BNK−MIN
case of low line, f
is fixed by f
at heavy load
BNK
BNK−MAX
condition above V = 2.0 V. For medium load condition
FB
between V = 1.6 V and V = 2.0 V, f is modulated
FB
FB
BNK
as a function of V corresponding to load. For light load
FB
condition below V = 1.6 V, f
is fixed by f
.
FB
BNK
BNK−MIN
High line blanking frequency curve is enabled when I
VBLK
VS
becomes higher than I
(typ. 1.440 mA), while low line
Vo
VS−HL
blanking frequency curve is enabled. Low line blanking
frequency curve is enabled when I becomes less than
ON TRIG
GATE
OSC
PWM Control
Logic Block
VS
OFF TRIG
I
(typ. 1.350 mA), while high line blanking frequency
VS−LH
ZCOMP
curve is enabled. High line voltage judgement level,
, corresponding to I and low line voltage
V
HL.BNK
VS−HL
judgement level, V
determined as
, corresponding to I
are
LL.BNK
VS−LH
COMV
FB
VSAW
AV
CS
RVSH
VCCR
1.6 V
COMI
VHL.BNK + IVS*HL
@
(eq. 3)
NA ń NP
Z
RVSH
IO
Estimator
VS
VLL.BNK + IVS*LH
@
(eq. 4)
Zero Current
Detector
NA ń NP
where it is recommended to set V
lower than
HL.BNK
215 V for a high line blanking frequency curve at 230 V
AC
AC
Figure 21. Simplified PWM Control Circuit
and V
higher than 130 V for a low line blanking
LL.BNK
AC
frequency curve at 115 V
.
AC
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10
FAN6080HMX
Leading−Edge Blanking (LEB)
V , the PWM output shuts off, and the output
FB−Burst−L
Each time the power MOSFET is switched on, a turn−on
voltage spike is induced across the sense resistor. To avoid
premature termination of the switching pulse due to the
voltage drops at a rate which is dependent on the load current
level. This causes the feedback voltage to rise. Once V
FB
exceeds V
, FAN6080HMX resumes switching.
FB−Burst−H
voltage spike, a 300 ns leading−edge blanking time (t ) is
The feedback voltage then falls and peak current reduces.
Once the FB voltage drops below the corresponding I
LEB
built in. External RC filtering can therefore be omitted.
During this blanking period, the current−limit comparator is
disabled and it cannot switch off the gate driver.
,
MIN
the peak current, during each switching cycle, is fixed to
regardless of FB voltage. Thus, more power is
I
MIN
delivered to the load than required, and once FB voltage
decreases lower than V , switching stops. In this
manner, the burst mode operation alternately enables and
disables switching of the MOSFET to reduce the switching
losses at light load condition.
CCM Prevention
Time−out window sets the frequency to f
FB−Burst−L
as
OSC−MIN−DCM
explained in “Valley Switching” section. However, if the
secondary side current does not reduce to zero within Time
out window, FAN6080HMX does not initiate turn−on.
When the secondary current reaches zero, the transformer
winding voltage begins to drop sharply, and hence, the VS
pin voltage drops as well. When VS pin voltage drops
enough, FAN6080HMX turns on the primary MOSFET
ensuring Boundary Conduction Mode (BCM) operating.
Thus, FAN6080HMX does not allow the converter to enter
CCM operation. During CCM prevention, FAN6080HMX
VO
V
determines the
CS−IMIN
minimum peak current
VFB
VCS−IMIN
can reduce the frequency down to f
.
VFB−Burst−H
OSC−MIN−CRM
VFB−Burst−L
HV Startup and Brown−In
An internal JFET provides a high voltage current source.
To improve reliability and surge immunity, it is typical to use
Figure 22. Burst−Mode Operation with IMIN
a R resistor between the HV pin and the bulk capacitor
HV
voltage.
The current consumption of FAN6080HMX is reduced to
During startup, the internal startup circuit is enabled and
the bulk capacitor voltage supplies the current I to charge
the hold−up capacitor, C
reaches V
the sampling circuit is turned on to sample the bulk capacitor
voltage. When this bulk capacitor voltage is higher than the
internal brown−in reference, PWM switching starts. The
I
to minimize power consumption if FB voltage
DD−Burst
HV
stays lower than V
for more than t
FB−Burst−L
IDD−Burst
, through R . When V
VDD
HV DD
(100 ms). Once feedback voltage is more than V
,
FB−Burst−H
, the internal startup circuit is disabled and
DD−ON
IC resumes switching with normal operating current,
I
.
DD−OP
Protections
brown−in voltage is trimmed at 92 V with 360 kW of R
If line voltage is lower than the brown−in voltage,
FAN6080HMX goes in auto−restart mode.
.
When the Auto−restart mode protection is triggered,
switching is terminated, and the MOSFET remains off,
HV
causing V
to drop because of IC operating current
DD
Once switching starts, the internal HV startup circuit is
disabled. Once the HV startup circuit is disabled, the energy
I
(VDD−OVP, AOCP and TSD), as shown in
DD−OP
Figure 23. When V drops to the V turn−off voltage,
DD
DD
stored in C
supplies the IC operating current until the
V , the protection is reset, and the supply current
DD−OFF
VDD
transformer auxiliary winding voltage reaches the nominal
value. Therefore, C should be properly designed to
drawn from HV pin begins to charge the V
hold−up
DD
capacitor. When V reaches the turn−on voltage, V
,
VDD
DD
DD−ON
prevent V
from dropping below V
threshold
FAN6080HMX resumes normal operation. In this manner,
the auto−restart alternately enables and disables the
switching of the MOSFET until the abnormal condition is
eliminated.
DD
DD−OFF
(typically 6 V) before the auxiliary winding builds up
enough voltage to supply V . During startup the IC current
is limited to I
DD
.
DD−ST
When 3 and 6 cycles Auto−Restart mode protection is
triggered at low and high lines respectively, for the case of
VS−OVP or VS−UVP, the switching stops to avoid
switching losses while 3 (or 6) cycles of AR are repeated, as
shown in Figure 24. The multi−cycles AR operation is
implemented to reduce input power consumption during
output short condition.
Burst Mode Operation
FAN6080HMX features burst mode operation with a
trimmable burst mode entry load condition using minimum
peak current (I
) control, which enables light load
MIN
efficiency to be optimized for a given application. The I
can be selected by trim options to select minimum V
threshold level for burst mode entry.
Figure 22 illustrates the operation of the burst mode
feature in FAN6080HMX. When V drops below
MIN
CS−IMIN
There is no Latch mode protection in FAN6080HMX.
FB
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11
FAN6080HMX
VDS
Power
On
Line Voltage Compensation
The output current estimation is also affected by the
turn−off delay of the MOSFET. The actual MOSFET
turn−off time is delayed due to the MOSFET gate charge and
gate driver capability, resulting in peak current detection
error as
VDD−OVP
occurs
VBLK
VDD
PK
DIDS
+
@ tOFF.DLY
(eq. 7)
V DD−OVP
Lm
where L is the transformer primary side magnetizing
VDD−ON
m
inductance. Since the output current error is proportional to
the line voltage, the FAN6080HMX incorporates line
voltage compensation to improve output current estimation
accuracy. The line compensation gain is programmed by
V DD−OFF
Fault
removed
using CS pin series resistor, R
depending on the
CS.COMP
IDD
MOSFET turn−off delay, t
as shown in Equations
OFF.DLY
IDD−OP
8~10. I
creates a voltage drop, V
, across
OFFSET
COMP
R
. This line compensation offset is proportional to
CS.COMP
IDD−ST
the DC link capacitor voltage, V
and turn−off delay,
BLK
t
.
OFF.DLY
Figure 23. Auto−restart Mode Operation
(e.g. VDD−OVP)
NA
1
ICOMP + VBLK
@ 0.04167
(eq. 8)
NP RVSH
V DS
Power
On
VBLK
* ǒ Ǔ
Lm
PK
+ ƪ
)ƫ
DVCS
Ids
@ (tON * tOFF.DLY @ RCS
(eq. 9)
DVCS
RCS.COMP
+
(eq. 10)
ICOMP
VS−OVP
occurs
VDD
VDD−ON
VDD−OFF
where R
is given by Equation (5).
VSH
VDD Over−Voltage−Protection (VDD−OVP)
VDD over−voltage protection prevents IC damage from
over−voltage stress. It operates in the Auto−restart mode.
Fault
removed
When the V voltage exceeds V
for the debounce
DD
DD−OVP
time, t
due to abnormal condition, the protection
IDD
D−VDDOVP
is triggered. This protection is typically caused by an open
circuit of secondary side feedback network.
IDD−OP
IDD−Burst
IDD−ST
Brown−Out Protection
Brown−out protection is operated in Auto−restart mode.
Figure 24. 3 Cycle Auto−restart Mode Operation
(e.g. VS−OVP)
When the current on VS pin is smaller than I
for
VS−Brown−Out
longer than t , the brown−out protection is
D−Brown−Out
triggered. The input bulk capacitor voltage to trigger
brown−out protection is given as
Programming Constant Current (CC) Level
The constant current (CC) level can be programmed by
the current sense resistor (R ) selection. FAN6080HMX
CS
RVSH
VBLK.BO + 450 m @
estimates the output current of the converter using primary
side peak current information and secondary rectifier
conduction time. The CC level can be programmed by
setting the current sensing resistor as
(eq. 11)
NA ń NP
where R
is given by Equation 5.
VSH
IC Internal Over−Temperature−Protection (OTP)
The internal temperature−sensing circuit disables the
PWM output if the junction temperature exceeds 140°C
VREF*CC
NP
1
2
1
RCS
+
@
@
@
(eq. 6)
NS IO*CC
APK
(T ), and the FAN6080HMX enters Auto−restart mode
OTP
protection.
V
(1.6 V) is the inverting input of the error
REF−CC
amplifier of the current regulator, A (3.3) is peak gain, and
PK
I
is the desired CC level.
O−CC
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12
FAN6080HMX
VS Over−Voltage−Protect (VS−OVP)
Pulse−by−Pulse Current Limit
VS over−voltage protection prevents damage caused by
output over−voltage condition. It is operated in Auto−restart
mode. When abnormal system conditions occur, which
During startup or overload condition, the feedback loop is
saturated, and is unable to control the primary peak current.
To limit the current during such conditions, FAN6080HMX
has pulse−by−pulse current limit protection which forces the
GATE to turn off when the CS pin voltage reaches the
cause VS sampling voltage to exceed V
for more
), PWM
VS−OVP
than 3 consecutive switching cycles (N
VS−OVP
pulses are disabled, and FAN6080HMX enters Auto−restart
protection. VS over−voltage conditions are usually caused
by open circuit of the secondary side feedback network or a
fault condition in the VS pin voltage divider resistors. The
desired VS−OVP is calculated as follows
current limit threshold, V
.
CS−LIM
CS Short Protection
To prevent any inductance saturation or thermal failure
due to a short circuit on the CS pin, a CS short protection
feature is implemented in FAN6080HMX, as illustrated in
Figure 25. In every switching cycle, the voltage on the CS
NS
NA
RVSH
@ ǒ1 ) Ǔ
RVSL
VO*OVP
+
@ VVS*OVP
(eq. 12)
pin (V ) is compared against a reference voltage,
CS
V
= 0.1 V. If V voltage is less than V
after
where V
is the output over−voltage protection
CS.Short
CS
CS.Short
O−OVP
a t
time period, CS short protection will be
level.
BNK.CS.Short
triggered, and turn off the GATE immediately. The CS short
protection is operating pulse−by−pulse manner.
VS Under−Voltage−Protection (VS−UVP)
In the event of an output short, output voltage will drop
and the primary peak current will increase. To prevent
operation for a long time in this condition, FAN6080HMX
incorporates under−voltage protection. The output voltage
is indirectly sensed through VS pin. When VS sampling
PWM
PWM
GATE−IC
GATE−IC
GATE−MOS
GATE−MOS
voltage is less than V
longer than debounce cycles
VS−UVP−L
0.1 V
0.1 V
CS Normal
N , VS−UVP is triggered and the FAN6080HMX
VS−UVP
VCS
VCS CS Short
enters the Auto−restart Mode.
CS Short Protect!!
t
BNK.CS.Short
t BNK.CS.Short
To avoid VS−UVP triggering during the startup sequence,
Normal operation
CS pin short protection
a startup blanking time, t
, is included for
VS−UVP−BLANK
system power−on. For VS pin voltage divider design, R
Figure 25. CS−Short Protection Operation
VSH
is calculated using Equation 5 for a certain high/low line
voltage judgement level. Then, R is designed in order to
have both VS−OVP and VS−UVP level within the desired
range using Equations 12 and 13.
Abnormal Over Current Protection (AOCP)
VSL
The AOCP protection triggers when a shoot−through
current occurs which means primary and secondary
MOSFETs turn on simultaneously. This protection is set at
1.6 V. When the PWM goes high, a leading edge blanking
NS
NA
RVSH
@ ǒ1 ) Ǔ
RVSL
VO*UVP
+
@ VVS*UVP*L
(eq. 13)
time (t ) starts blanking this protection. Once the counter
LEB
expires, the V is measured and compared to the reference
where V
is the output under−voltage protection
CS
O−UVP
voltage 1.6 V. If V is greater than 1.6 V, FAN6080HMX
level.
CS
will shut off, and stop switching. It is a one switching cycle
protection, and after it gets triggered the system enters the
Auto−restart mode.
ORDERING INFORMATION
†
Device
FAN6080HMX
Operating Temperature Range
−40°C to + 125°C
Package
Shipping
8−Lead, Small Outline Package (SOIC),
JEDEC MS−012, .150−Inch Narrow Body
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
13
FAN6080HMX
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
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14
FAN6080HMX
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