FAN65005A [ONSEMI]
同步 PWM 降压稳压器，高性能，电压模式，65 V，8 A;
| 型号： | FAN65005A |
| 厂家： | 
ONSEMI |
| 描述： | 同步 PWM 降压稳压器，高性能，电压模式，65 V，8 A 开关 稳压器 |
| 文件： | 总26页 (文件大小：1562K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Synchronous PWM Buck
Regulator, Voltage Mode,
High Performance, 65 V, 8 A
PQFN35 6x6
CASE 483BE
FAN65005A
Description
MARKING DIAGRAM
FAN65005A is a wide VIN highly efficient synchronous buck
regulator, with integrated high side and low side power MOSFETs.
The device incorporates a fixed frequency voltage mode PWM
controller supporting a wide voltage range from 4.5 V to 65 V and can
handle continuous currents up to 8 A.
FAN65005A includes a 0.67% accurate reference voltage to achieve
tight regulation. The switching frequency can be programmed from
100 kHz to 1 MHz. To improve efficiency at light load condition, the
device can be set to discontinuous conduction mode with pulse
skipping operation.
ZXYYKK
FAN
65005A
1
Z
X
YY
KK
= Assembly Location
= Year / Lead Free
= Week
= Lot
FAN65005A = Specific Device Code
FAN65005A has dual LDOs to minimize power loss and integrated
current sense circuit that provides cycle−by−cycle current limiting.
This single phase buck regulator offers complete protection features
including Over current protection, Thermal shutdown, Under−voltage
lockout, Over voltage protection, Under voltage protection and
Short−circuit protection.
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of
this data sheet.
®
FAN65005A uses onsemi’s high performance PowerTrench
MOSFETs that reduces ringing in switching applications.
FAN65005A integrates the controller, driver, and power MOSFETs
into a thermally enhanced, compact 6 x 6 mm PQFN package. With an
integrated approach, the complete DC/DC converter is optimized from
the controller and driver to MOSFET switching performance,
delivering a high power density solution.
Features
• Wide Input Voltage Range: 4.5 V to 65 V
• Continuous Output Current: 8 A
• Fixed Frequency Voltage Mode PWM Control with Input Voltage
Feed−forward
• 0.6 V Reference Voltage with 0.67% Accuracy
• Adjustable Switching Frequency: 100 kHz to 1 MHz
• Dual LDOs for Single Supply Operation and to Reduce
Power Loss
• Selectable CCM PWM Mode or PFM Mode for Light
Loads
• External Compensation for Wide Operation Range
• Adjustable Soft−Start & Pre−Bias Startup
• High Performance Low Profile 6 mm x 6 mm PQFN
Package
• This Device is Pb−Free and RoHS Compliant
Applications
• High Voltage POL Module
• Telecommunications: Base Station Power Supplies
• Networking: Computing, Battery Management
Systems, USB−PD
• Enable Function with Adjustable Input Voltage
Under−Voltage−Lock−Out (UVLO)
• Power Good Indicator
• Industrial Equipment: Automation, Power Tools, Slot
Machines
• Over Current Protection, Thermal Shutdown, Over
Voltage Protection, Under Voltage Protection and
Short−circuit Protection
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
May, 2022 − Rev. 4
FAN65005A/D
FAN65005A
TYPICAL APPLICATION
VIN
4.5 V~65 V
RBOOT
C3
R2
C2
C1
VCC
R3
EN /
UVLO
SYNC
R5
PGOOD
C4
PVCC
EXTBIAS
L
R4
VO
C5
SW
VCC
C7
R8
COMP
MODE
R9
C6
R6
R7
R10
R11
SS
RT
C10
C9
C8
FB
Figure 1. Typical Application
Table 1. APPLICATION DESIGN EXAMPLE
C
from
Phase
margin
(⁰)
O
V
L to be
C
V
from
C
V
from
C
to be
used
R11
(W)
R9
(W)
R8
(W)
C9
(F)
C7
(F)
C8
(F)
f
CO
RT
O_RIPPLE
O
O
O
(mF)
used (mH)
(mF)
(mF)
(Hz)
18.0k
22.6k
22.6k
(=R6) (W)
V
(V)
V
(V) L (mH)
O
R10 (W)
OS
US
IN
35
24
28
16.762
12.444
9.524
2.6
2.2
2.1
2.6
2.2
2.1
2.6
2.2
2.1
30.9
65.2
718.2
613.4
571.6
718.2
613.4
571.6
718.2
613.4
571.6
69.4
67.5
67.5
35
35
48
48
48
60
60
60
22.7
19.8
30.9
22.7
19.8
30.9
22.7
19.8
83.5
103.6
30.9
31.4
32.3
20.8
19.9
19.8
30
24
28
30
24
28
30
26.667
25.926
25.000
32.000
33.185
33.333
22.00
75.2
28010
365
1.0k
2.7n 220n 470p
3.75E+04
NOTE: *Iout = 5 A, Fsw = 300 KHz
www.onsemi.com
2
FAN65005A
BLOCK DIAGRAM
6 − 4
1 0 − 7
Figure 2. Block Diagram
www.onsemi.com
3
FAN65005A
PIN CONFIGURATION
1
2
VIN
VIN
31 32 33 34 35
27
26
28
29 30
EXTBIAS
GND
25
24
23
22
21
20
19
18
17
PVCC
VCC
3
4
VIN
PGND
EN/UVLO
SYNC
PGOOD
RT
5
6
PGND
PGND
12
GND
16 15 14 13
11 10
9
8
7
SS
Figure 3. Pin Assignment (Bottom View)
Description
Table 2. PIN DESCRIPTION
Name
Pin/Pad
VIN
1−3, 31−35,
VIN Pad
Input voltage to power stage
PGND
4−6, PGND
Power ground for power stage and PVCC
Pad
SW
NC
7−10
11
Switching node, junction of high- and low-side MOSFETs
No Connection
LG
12
Gate of low side MOSFET
MODE
ILIM
13
Configures pulse modulation/frequency synchronization modes. See MODE description for details
Connect a resistor to GND to set the high-side MOSFET peak current limit
Feedback Voltage Input
14
FB
15
COMP
SS
16
Output of internal error amplifier for external compensation
Set up soft-start time. Connect a capacitor between SS and PGND to set the soft start time
Analog ground for VCC, RT, SYNC, MODE, etc.
17
GND
RT
18, 25
19
Connect a resistor to GND to set switching frequency
PGOOD
SYNC
EN/UVLO
20
Power good indicator, open-drain output. Level HIGH indicates V
is within set limits
OUT
21
The pin is used to synchronize frequency in when in Non-Master mode or out when in master mode
22
Enable/VIN Under-Voltage-Lockout set pin. When used as enable function in-dependent of input
voltage, connect this pin to a voltage > 1.22 V to enable or PGND to disable. When used as enable func-
tion at specific input voltage level, connect a resistor divider between input voltage and PGND to this pin
VCC
PVCC
23
24
26
27
Bias power for internal analog circuits
LDO output and the bias supply for gate driver circuit
EXTBIAS
HVBIAS
Input voltage to the secondary LDO. Typically connect to V when V ≥ 5 V
O O
Input voltage to the primary LDO. Also used for the feed-forward function. Connect it to power stage
input with a small RC filter
VINMON
BOOT
PH
28
29
30
Current sense positive pin. Do NOT connect anything
Bootstrap supply for high-side driver. Connect a low impedance capacitor between this pin and PH pin
High-side source connection (SW node) for the bootstrap capacitor
www.onsemi.com
4
FAN65005A
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−5.0
−7.5
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−
Max
70
Unit
V
VIN Pin Voltage (System Supply) with regard to PGND
HVBIAS Pin Voltage with regard to PGND
EXTBIAS Pin Voltage with regard to PGND
EN/UVLO Pin Voltage with regard to PGND
PH Pin Voltage with regard to PGND
V
IN
HVBIAS
V
70
V
70
EXTBIAS
EN/UVLO
V
8.4
70
V
PH
V
SW
SW Pin Voltage with regard to PGND
SW Pin Voltage with regard to PGND (Pulse, 100 ns)
SW Pin Voltage with regard to PGND (Pulse, 30 ns)
BOOT Pin Voltage with regard to PGND
BOOT Pin Voltage with regard to PH Pin
ILIM Pin Voltage with regard to GND
70
75
75
V
BOOT
75
6.5
6.5
6.5
V
ILIM
V
PVCC
PVCC Pin Voltage with regard to PGND
FB Pin Voltage with regard to GND
V
FB
V
V
V
+ 0.3
CC
CC
CC
V
COMP
COMP Pin Voltage with regard to GND
PGOOD Pin Voltage with regard to GND
LG Pin Voltage with regard to PGND
+ 0.3
+ 0.3
V
PGOOD
V
LG
V
+ 0.3
PVCC
V
MODE
MODE Pin Voltage with regard to GND
RT Pin Voltage with regard to GND
V
V
V
V
+ 0.3
+ 0.3
+ 0.3
+ 0.3
CC
CC
CC
CC
V
RT
V
SS
SS Pin Voltage with regard to PGND
V
SYNC
SYNC Pin Voltage with regard to GND
GND Pin Voltage with regard to PGND
Human Body Model, ANSI/ESDA/JEDEC JS−001−2012
Charged Device Model, JESD22−C101
Thermal Calculation
V
GND
0.3
ESD
1000
500
−
T
JN
−
T
HS
= k • Q + k • Q
+ k •
j3
Lead25 Lead25
• T
amb a
°C
°C
jn
j1
Lead5
LS
j2
Lead5
Controller
(Note 1)
Q
+ k
• T
+ k
• T
+ k
• T
+ k
Lead32
Lead32
T
J
Junction Operating Temperature
Device Storage Temperature
−55
−55
150
150
T
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2
2
1. Units, temperatures must be in degrees Celsius, power values (Q) must be in watts. Measured on 2s2p board, 80 x 80 mm with 546 mm
top layer spreader. Use coefficients as per below table:
FAN65005A
k
k
k
k
k
k
k
amb
j1
j2
j3
Lead5
Lead25
Lead32
2
2s2p board, 80 mm x 80 mm with 546 mm top layer spreader
LS coefficients
LDO coefficients
HS coefficients
6.8
4.0
2.8
4.1
45.8
2.0
2.4
1.9
6.4
0.46
0.26
0.19
0.09
0.29
0.05
0.21
0.17
0.54
0.24
0.28
0.22
www.onsemi.com
5
FAN65005A
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
4.5
−0.3
4.5
−
Typ
−
Max
65
Unit
V
VIN Pin Voltage (System Supply) with regard to PGND
HVBIAS Pin Voltage with regard to PGND
SW Pin Voltage with regard to PGND (DC)
EXTBIAS Pin Voltage with regard to PGND
EN/UVLO Pin Voltage with regard to PGND
PGOOD Pin Voltage with regard to GND
Operating Ambient Temperature
V
IN
HVBIAS
V
−
65
V
SW
−
V
IN
V
−
65
7.5
5.4
125
125
EXTBIAS
EN/UVLO
PG_SPLY
V
−
V
−
−
T
A
−40
−40
−
°C
°C
T
J
Junction Operating Temperature
−
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 5. ELECTRICAL CHARACTERISTICS
(Typical application circuit shown in Figure 1 is used. Unless otherwise noted, V = V
= 48 V, V
= 5 V, V = V = 5 V,
PVCC CC
IN
HVBIAS
OUT
−40°C < T = T < +125°C. T = T = +25°C for typical values)
J
A
A
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY
I
Forced CCM Quiescent Cur-
rent
V
= 2.0 V, MODE = 5 V through a
−
−
1.2
1.4
−
−
mA
HVBIAS_Q_PWM
EN
100 kW resistor, V = 0.64 V
FB
I
DCM with Pulse Skipping Qui-
escent Current
V
EN
= 2.0 V, MODE = 0 V through a
HVBIAS_Q_PSM
100 kW resistor, V = 0.64 V
FB
I
Shutdown Current
V
= 0 V
−
−
−
5
9
−
−
mA
HVBIAS_SDN
EN
V
HVBIAS UVLO Threshold
HVBIAS UVLO Hysteresis
HVBIAS Rising
HVBIAS Falling
3.92
1.0
V
HVBIAS_TH
V
HVBIAS_HYS
LDOs
V
PVCC
LDO Output Voltage
I
= 1 mA and EXTBIAS pin is
4.75
5.00
5.25
V
PVCC
open
V
V
= 12 V, I
= 1 mA
4.75
5.00
1.0
5.25
2.0
EXTBIAS
PVCC
V
LDO1 Dropout Voltage
LDO2 Dropout Voltage
= 5.0 V, LDO Output
HVBIAS
Current = 150 mA
−
HVBIAS_D
V
V
= 5.0 V, LDO Output
−
−
0.33
4.7
0.66
EXTBIAS_D
EXTBIAS
Current = 150 mA
V
Switchover Voltage above
which LDO1 is Disabled and
LDO2 is Enabled
V
is rising
−
LDOSWO
EXTBIAS
V
Switchover Voltage Hysteresis
V
V
is falling
−
−
100
5.5
−
−
mV
V
LDOSWO_HYS
EXTBIAS
V
Threshold Voltage above
which the LDO is in LDO mode
or V
or V
is rising
is falling
SWTOLDO
HVBIAS
EXTBIAS
V
Threshold Voltage below which
the LDO is in switch mode
V
−
5.4
−
LDOTOSW
HVBIAS
EXTBIAS
VCC SUPPLY
V
V
CC
V
CC
V
CC
Start Voltage
V
V
Rising
3.8
3.6
−
4.0
3.8
0.2
4.4
4.1
−
V
CC_ON
CC
V
UVLO Threshold
UVLO Hysteresis
Falling
CC_UVLO
CC
V
CC_UVLO_HYS
www.onsemi.com
6
FAN65005A
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(Typical application circuit shown in Figure 1 is used. Unless otherwise noted, V = V
= 48 V, V
= 5 V, V = V = 5 V,
PVCC CC
IN
HVBIAS
OUT
−40°C < T = T < +125°C. T = T = +25°C for typical values)
J
A
A
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
REFERENCE VOLTAGE
Reference Voltage
V
T = 25°C, V = 4.5 V to 65 V
0.596
0.594
0.600
0.604
0.606
V
REF
J
IN
T = −40°C to 125°C (Note 2)
J
−
ENABLE AND UNDER VOLTAGE LOCK OUT
V
EN/UVLO Threshold
EN/UVLO Hysteresis
EN/UVLO Rising
EN/UVLO Falling
1.141
1.22
115
500
1.296
V
EN_TH
V
−
−
−
−
mV
kW
EN_HYS
R
EN/UVLO Internal Pull down
Resistance
EN_PD
V
R
EN/UVLO Clamp Voltage
EN/UVLO Clamp Resistance
EN/UVLO Clamp Current
TBD
−
−
−
2.5
200
22
−
−
−
V
EN_CLP
EN_CLP
EN_CLP
kW
mA
I
V
EN
= 2.5 V
MODE
R
Resistor Connected to Mode
Pin for Master
70
1
100
130
5
kW
kW
MASTER
Synchronization Mode
R
Resistor Connected to Mode
Pin for Non-Master Synchro-
nization Mode
−
NON_MASTER
OSCILLATOR
f
Frequency Range
100
85
−
1000
125
kHz
SW
f
Switching Frequency Set by
RT
R = 199 kW
100
1000
250
500
SW1
SW2
SW3
SW4
T
f
f
f
R = 8.0 kW
T
900
215
425
1200
280
RT Pin is Short-Circuited to VCC Pin
RT Pin is Short-Circuited to GND Pin
575
FREQUENCY SYNCHRONIZATION
V
SYNC Input Logic HIGH
2
−
−
−
−
0.8
−
V
SYNC_IN_H
V
SYNC Input Logic LOW
SYNC_IN_L
t
Input HIGH Level Pulse Width
Input LOW Level Pulse Width
Synchronizable Frequency
150
150
70
−
−
ns
HIGH_IN_MIN
t
−
−
LOW_IN_MIN
f
Percentage of frequency set by RT
−
130
−
%
SYNC
RT_SYNC_DL
t
Transition Delay from RT Set
Frequency to Sync Frequency
In Number of External Clock Cycles
in 2 ms time period
64
Cycles
R
SYNC Pin Pull down Resis-
tance
−
−
−
−
−
100
10
13
50
−
−
−
kW
SYNC_PD
R
SYNC output Driver Pull-up
Resistance
W
SYNC_DR_PU
SYNC_DR _PD
R
SYNC output Driver Pull-down
Resistance
−
D
SYNC Output Frequency Duty
Cycle
−
%
SYNC_OUT
C
SYNC Pin Lead Capacitance
200
pF
L_SYNC
www.onsemi.com
7
FAN65005A
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(Typical application circuit shown in Figure 1 is used. Unless otherwise noted, V = V
= 48 V, V
= 5 V, V = V = 5 V,
PVCC CC
IN
HVBIAS
OUT
−40°C < T = T < +125°C. T = T = +25°C for typical values)
J
A
A
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RAMP AND PWM MODULATOR
PWM Modulator Gain,
k
V
IN
= V = 4.5 to 65 V
HVBIAS
−
25
−
V/V
ns
PWM
V
/DV
IN
RAMP
T
PWM Minimum ON time
PWM Minimum OFF time
−
−
150
150
200
200
ON_MIN
T
OFF_MIN
ERROR AMPLIFIER
GBW
G
Unit Gain Bandwidth
−
−
10
80
5
−
−
MHz
dB
DC Gain
I
FB Bias Current
COMP Source Current
COMP Sink Current
V
FB
= 0.6 V
−50
2
50
−
nA
FB
COMP_SOURCE
I
7
mA
mA
I
2
8.5
−
COMP_SINK
SOFT START
t
Enable High to Soft Start
Ramp Start Delay
−
1
5
3
ms
SS_DL
I
SS
Charging Current to SS
Capacitor
4.3
5.9
mA
BOOT
V
Bootstrap Switch Voltage Drop BOOT Current, I
= 50 mA
−
−
0.1
−
−
V
BT_SWITCH
BOOT
V
BOOT UVLO Voltage with re-
gard to PH
BOOT Falling
3.20
BT_UVLO_TH
V
BOOT UVLO Hysteresis with
regard to PH
BOOT Rising
−
0.35
−
BT_UVLO_HYS
CURRENT PROTECTION
I
Current Source Creating
Current Limit Reference
Voltage on R_ILIM
−
−
−
8.5
−
−
−
mA
LIM_S
k
High-side MOSFET current
limit scale factor
59.5
19.6
mA/W
ILIM_HS
(I
= k
× R
)
LIM_HS
ILIM_HS
ILIM
k
Low-side MOSFET current
limit scale factor
ILIM_LS
(I
= k
× R
)
LIM_LS
ILIM_LS
ILIM
n
Number of Switching Cycle(s)
before Entering Hiccup Mode
I
I
≤ I
< 130% I
LIM_HS
−
−
1024
1
−
−
Cycle
CYCLE_OCP
LIM_HS
SEN_PEAK
n
≥ 130%I
LIM_HS
CYCLE_SCP
SEN_PEAK
POWER GOOD
V
FB Pin Voltage for PGOOD to
Be De-asserted When Down
from Regulation
FB Falling
FB Rising
FB Falling
FB Rising
88
110
−
92
115
110
94
96
120
−
%V
REF
FB_NPG_TH
FB Pin Voltage for PGOOD to
Be De-asserted When up into
OVP1
V
FB Pin Voltage for PGOOD to
Be Asserted When Down from
OVP1
FB_PG_TH
FB Pin Voltage for PGOOD to
Be Asserted When up
into Regulation
−
−
www.onsemi.com
8
FAN65005A
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(Typical application circuit shown in Figure 1 is used. Unless otherwise noted, V = V
= 48 V, V
= 5 V, V = V = 5 V,
PVCC CC
IN
HVBIAS
OUT
−40°C < T = T < +125°C. T = T = +25°C for typical values)
J
A
A
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
POWER GOOD
t
PGOOD Delay
Time from when FB Reaches
FB_PG_TH
becomes HIGH
−
500
−
−
ms
PG_DL
V
to when PGOOD
t
PGOOD De-glitch Filter
Duration
−
−
5
6
ms
PG_FLT
V
PGOOD Output LOW
Voltage
V
FB
= 70%V , I = −1 mA
REF PGOOD
10
mV
PG_L
VOLTAGE PROTECTION
V
FB Pin Voltage for Level 1
Over Voltage Detection
FB Voltage Rising
FB Voltage Falling
110
124
−
115
130
35
120
136
−
%V
REF
FB_OVP1
V
FB Pin Voltage for Level 2
Over Voltage Detection
FB_OVP2
V
FB Pin Voltage for Under
Voltage Detection
FB_UVP_TH
HICCUP
Hiccup Time
−
1
−
s
tHICCUP
THERMAL SHUTDOWN
T
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Temperature Rising
Temperature Falling
−
−
150
20
−
−
°C
J_SD
J_SD_HYS
T
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design
www.onsemi.com
9
FAN65005A
TYPICAL PERFORMANCE CHARACTERISTICS
(Test at T = 25°C, V
= V = 48 V and V = 5 V unless otherwise specified)
A
HVBIAS
IN
O
0.0020
0.0018
0.0016
0.0014
0.0012
0.0010
0.0008
20
F
SW
= 300 KHz
19
18
0.0006
0.0004
17
16
0.0002
0
−50
−25
0
25
50
75
100 125
−40 −20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4. Line Regulation vs. Temperature
Figure 5. VIN Quiescent Current vs. Temperature
5.4
5.2
5.0
4.8
4.6
4.86
Vin = 48 V
Vout = 12 V
Fsw = 300 KHz
R_LIM = 115 K
4.84
4.82
4.80
4.78
4.76
4.74
4.4
4.2
4.72
4.70
−40 −20
0
20
40
60
80
100
120
−40 −20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Over Current vs. Temperature
Figure 7. Shutdown Current vs. T at VHVBIAS = 48 V
4.3
4.2
4.1
3.3
3.2
3.1
4.0
3.9
3.8
3.0
2.9
2.8
3.7
3.6
2.7
2.6
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. HVBIAS Rising Threshold vs. T
Figure 9. HVBIAS Falling Threshold vs. T
www.onsemi.com
10
FAN65005A
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at T = 25°C, V
= V = 48 V and V = 5 V unless otherwise specified)
A
HVBIAS
IN
O
0.6010
0.6005
0.6000
0.5995
0.5990
0.5985
1.2210
1.2205
1.2200
1.2195
1.2190
1.2185
0.5980
1.2180
1.2175
0.5975
0.5970
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. VREF vs T at VHVBIAS = 48 V
Figure 11. EN/UVLO Threshold Voltage vs. T
at VHVBIAS = 48 V
1200
1000
800
160
150
140
130
120
110
100
600
400
200
0
90
80
−40 −20
0
20
40
60
80
100 120
0
20 40 60 80 100 120 140 160 180 200
TEMPERATURE (°C)
RT (kW)
Figure 12. EN/UVLO Hysteresis Voltage vs. T
at VHVBIAS = 48 V
Figure 13. Switching Frequency vs. RT at
VHVBIAS = 48 V and T = 255C
1020
1019
1018
1017
251.5
251.0
250.5
250.0
249.5
1016
1015
249.0
248.5
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Switching Frequency vs. T at
HVBIAS = 48 V and RT = 8.06 kW
Figure 15. Switching Frequency vs. T at
VHVBIAS = 48 V and RT shorted to VCC
V
www.onsemi.com
11
FAN65005A
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at T = 25°C, V
= V = 48 V and V = 5 V unless otherwise specified)
A
HVBIAS
IN
O
520
518
516
514
512
510
24.9
24.8
24.7
24.6
24.5
24.4
508
506
24.3
24.2
504
502
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Switching Frequency vs. T at
HVBIAS = 48 V and RT shorted to GND
Figure 17. PWM Modulator Gain, VIN / DVRAMP
,
V
vs. T at VHVBIAS = 48 V
154.2
154.0
153.8
153.6
153.4
153.2
153.0
152.8
154.6
154.4
154.2
154.0
153.8
153.6
153.4
153.2
153.0
152.8
152.6
152.4
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. TON_MIN vs. T at VHVBIAS = 48 V
Figure 19. TOFF_MIN vs. T at VHVBIAS = 48 V
16
14
12
10
8
6
4
2
0
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
Figure 20. 8.5 mA Current Source for Current
Limit Purpose vs. T at VHVBIAS = 48 V
www.onsemi.com
12
FAN65005A
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at T = 25°C, V
= V = 48 V and V = 5.0 V unless otherwise specified)
A
HVBIAS
IN O
Figure 21. System Startup with No Load
Figure 22. System Startup with No Load
Figure 23. System Startup with 25% Pre-bias
www.onsemi.com
13
FAN65005A
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at T = 25°C, V
= V = 48 V and V = 5.0 V unless otherwise specified)
A
HVBIAS
IN
O
Figure 24. System Startup with 75% Pre-bias
Figure 25. Show 64 Cycles of Transition Delay from
RT Set Frequency to Sync Frequency
Figure 26. SYNC Output Frequency Duty Cycle in
Master Mode
Figure 27. Over-current Protection with 250 kHz
Switching Frequency
Figure 28. Power Good at Startup with No Load
Figure 29. Power Good at Startup with No Load
www.onsemi.com
14
FAN65005A
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at T = 25°C, V
= V = 48 V and V = 5.0 V unless otherwise specified)
A
HVBIAS
IN O
Figure 30. OVP1 at VFB . 115% VREF
Figure 32. OVP2 at VFB . 130% VREF
Figure 34. UVP due to Deep Over-current
Figure 31. OVP1 Release at VFB 3 110% VREF
Figure 33. OVP2 Release at VFB 3 100% VREF
Figure 35. Switching and Voltage Ripple
www.onsemi.com
15
FAN65005A
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
(Test at T = 25°C, V
= V = 48 V and V = 5.0 V unless otherwise specified)
A
HVBIAS
IN O
94
92
90
88
86
84
82
80
5A_24Vin
5A_36Vin
5A_48Vin
5A_60Vin
1
2
3
4
5
Load Current (A)
6
7
8
Figure 36. Load Step between 50% and 100% Load
Figure 37. System Efficiency
0.10%
5
4
3
2
1
0
12V
12V
24V
VIN = 35V
48V
60V
VO = 5V
fSW = 250kHz
24V
VIN = 35V
0.05%
48V
60V
VO = 5V
fSW = 250kHz
0.00%
- 0.05%
- 0.10%
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Load Current (A)
Load Current (A)
Figure 38. Load Regulation
Figure 39. System Power Loss
NOTE: EXTBIAS is connected to V for Figures 21−39
O
Functional Description
the output voltage will be reduced in current limiting
condition. Other protection functions include over
temperature shut-down and over-voltage protection.
At the beginning of each switching cycle, the clock signal
initiates a PWM signal to turn on high-side MOSFET, and
at the same time, the ramp signal starts to rise up. A reset
pulse is generated by the comparator when the ramp signal
intercepts the COMP signal. This reset pulse turns off
high-side MOSFET and turns on low-side MOSFET until
next clock cycle comes. In the case that current limit is hit,
a peak current limiting (PCL) signal is generated to turn off
the high-side MOSFET until the next PWM signal. This is
cycle by cycle current limit protection. When certain faulty
condition is met, the device enters hiccup mode to further
protect itself.
FAN65005A is a high-efficiency synchronous buck
converter with integrated controller, driver and two power
MOSFETs. It can operate over a 4.5 V to 65 V input voltage
range, and delivers 8 A load current. The internal reference
voltage is 0.6 V 1% over −40°C to 125°C temperature
range.
FAN65005A uses voltage mode PWM control scheme
with input voltage feed-forward feature for the wide input
voltage range. The high bandwidth error amplifier monitors
the output voltage and generates the control signal for the
pulse width modulation block. By adjusting the external
compensation network, the system performance can be
optimized based on the application parameters.
The switching frequency is set by an external resistor and
can be synchronized to an external clock signal. To improve
light load efficiency (low I mode), either low-side
MOSFET is turned off when the inductor current drops to
zero or pulse skipping is implemented when load current
further decreases. The high-side MOSFET current sense
circuit is adopted for the peak current limiting function and
LDOs
Q
Two LDOs are included in FAN65005A to provide
internal supply and to balance power loss from them.
The LDO block diagram is shown below.
www.onsemi.com
16
FAN65005A
PVCC
BOOT
together with a ceramic capacitor between VCC and AGND
to form a filter for the VCC bias supply for the internal
control circuits. When VCC voltage drops below its UVLO,
the regulator control circuit blocks are disabled.
EXTBIAS
V
V
LDO2
LDO1
EXT
:
R1
HVBIAS
IN
Sync
Control
4.5 V~65 V
C2
Enable and Under Voltage Lock-Out
EN/UVLO signal is used for device enable/disable when
Internal Bias and
Feed-forward Feature
REG
its voltage is higher/lower than the threshold, V
,
EN_TH
which is typical 1.22 V. The precision threshold voltage of
this signal can also be used to set a system input voltage
level, above which FAN65005A will be enabled and below
which disabled. Figure 41 shows the EN/UVLO block
diagram and application configuration.
Figure 40. LDO Block Diagram
Since LDO1 input, HVBIAS, is also used for initial
internal bias and for input voltage feed-forward
compensation, system input voltage, VIN, should always be
connected to HVBIAS pin and an RC filter is recommended
between VIN and HVBIAS to filter any noise from high
frequency switching. During power up, LDO1 is always
selected. After the system finishes soft start, which LDO
block is selected depends on voltages appearing on both
HVBIAS and EXTBIAS pins. If there is a voltage at
EXTBIAS pin and it is above 4.7 V, LDO2 will be selected,
otherwise LDO1 will continue to supply power to the
device. EXTBIAS can be left open for single LDO operation
all the time. In the case that EXTBIAS is connected to a
A resistor divider (R2 and R3, as shown in Figure 1) can
be used to set the level of input voltage, V
, which
IN_UVLO
enables the device. Selection of R3 is determined by
Equation 1.
(eq. 1)
V
R2 R
EN_PD1
EN_TH
R3 +
V
R
* V
R2 * V
R
EN_TH EN_PD1
IN_UVLO
EN_PD1
EN_TH
R2 and R3 are both in kW.
Assuming i, in mA, is the current flowing through R2
when working input voltage is V , then R2 is determined by
IN
voltage, V , and V
> 4.7 V and also V
> V
,
EXT
EXT
EXT
HVBIAS
Equation 2.
LDO2 will be selected. This makes power loss on LDO2
greater than that on LDO1 if LDO1 were selected. So it’s the
V
IN_UVLO * VEN_TH
VIN
i
(eq. 2)
R2 +
VIN_UVLO
designer’s responsibility to make sure V
< V
EXT
HVBIAS
while V
> 4.7 V. Both LDOs work in switch mode when
EXT
V
= 4.5 V~65 V
IN
their input voltages are lower than 5.4 V. This allows very
low voltage drop on both LDOs and ensures high enough
voltage level on PVCC for internal bias and MOSFET drive.
VCC
i
R2
Assuming V
< V
while V
> 4.7 V, Table 6
EXT
HVBIAS
EXT
R
= 200 kW
EN_CLP
> 1 V
EN/UVLO
shows which LDO will be selected and the LDO work status.
(• indicates which LDO and mode are selected and × means
disabled)
2.5 V
V
< 1 V
V
EN
R3
EN
EN/UVLO
Threshold
1.22 V
Table 6. LDO SELECTION AND WORK MODE
Work Mode
PGND
LDO1
LDO2
Input
EXTBIAS
HVBIAS
(V)
(V)
Switch
LDO
Switch
LDO
4.5−4.7
4.7−5.5
4.5−4.7
4.5−4.7
4.7−5.5
4.5−4.7
4.7−5.5
5.5−50
•
•
×
×
×
•
×
×
•
×
×
×
×
×
•
Figure 41. EN/UVLO Block Diagram
For example, a converter has nominal input voltage of
= 48 V. It’s desired that the device is enabled when input
×
×
×
×
V
IN
5.5−65
×
•
voltage is above 35 V, which makes V
= 35 V. If
IN_UVLO
×
×
50 mA is chosen, then Equations 1 and 2 yield R2 and R3 in
Equations 3 and 4 respectively:
×
48 (35 * 1.22)
(eq. 3)
(eq. 4)
R2 +
+ 926.5 kW
35 50 10*6 103
Both LDOs are designed to deliver up to 150 mA current.
A 4.7 mF ceramic capacitor between PVCC and PGND
placed as close as possible to PVCC pin is recommended to
decouple any noise from high frequency driver currents.
A 1 W resistor can be used between PVCC and VCC
1.22 926.5 150
R3 +
35 150 * 1.22 926.5 * 1.22 150
+ 43.1 kW
www.onsemi.com
17
FAN65005A
Pre-bias Startup
Choose the closest standard 1% resistor values of
R1 = 931 kW and R2 = 43.2 kW. What value is chosen for i
is a power loss matter. The greater the i is, the greater the
power loss will be, and vice versa. But if the current is too
low, the EN/UVLO signal will be vulnerable to noise.
Choose the highest possible current that only creates
negligible power loss to the system. In the example shown
A pre-biased regulator is one that, before the regulator is
powered, has output voltage above 0, and so for the FB pin.
FAN65005A is able to start in such a case. When soft start
is initiated, both high- and low-side MOSFETs are forced off
until the SS pin is charged up to the pre-biased FB voltage.
The following startup process will be a normal soft start
process as stated in “Soft Start” section.
above, the power loss in this EN/UVLO branch is P = V
i = 48 V × 50 mA = 2.4 mW.
×
IN
Switching Frequency
The internal clock generator can be programmed from
100 kHz to 1 MHz by a resistor connected between the R
pin and the AGND pin. To set the desired switching
frequency, the resistor can be calculated by Equation 5 as
shown below:
When the device is disabled, only a few micro-ampere
current is required to support essential blocks like bandgap.
Only after the device is enabled, major functions like, LDO,
oscillator, soft start, driver, logic control, start to run. The
device is disabled if the EN/UVLO pin is floating.
T
104
Soft Start
+ min ƪ
) 50, 1000ƫ
(eq. 5)
fSW
The soft start block diagram is shown in Figure 42.
RT ) 2.5
where f is in kHz and RT is in kW.
SW
VCC
The switching frequency vs. the external resistor curve is
shown below.
FB
SS
5 mA
Switching Frequency, f
vs. RT
SW
1200
1000
800
_
EA
+
+
C6
600
V
REF
400
200
Figure 42. Soft Start Block Diagram
0
0
20
40
60
80 100 120 140 160 180 200
The soft start function is enabled with a delay of maximum
3 ms after EN is high. During the delay, the SS capacitor is
discharged if there is any residual voltage. If SS voltage is
still not 0 after this delay, a fault condition is created and the
device enters hiccup mode, otherwise soft start process is
initiated. A typical 5 mA constant current flows out of SS pin
to charge the capacitor at SS pin. The error amplifier
regulates the converter output voltage according to the lower
value of SS pin voltage and the fixed 0.6 V reference
voltage. With the constant current, SS voltage linearly ramps
up from 0, and the regulator output voltage follows the SS
voltage to ramp up. SS voltage continues to rise after it
exceeds the 0.6 V reference voltage, at which point, the SS
voltage is out of the loop and the converter output voltage is
regulated to the reference voltage of 0.6 V. When SS
capacitor is charged to 1.5 V, the SS timer stops counting and
RT (kW)
Figure 43. Relationship between RT and fSW
As soon as the device is enabled, it will go through a set
of routine to check the RT pin configuration to determine the
switching frequency or if there is any fault. If RT is tied to
VCC, the switching frequency is 250 kHz, and 500 kHz if
short-circuited to AGND. If RT pin is floating initially or
becomes open from any non-open state, the device enters
hiccup mode.
Frequency Synchronization
FAN65005A can be set to work in either master mode or
non-master mode. When in master mode, it sends out clock
signal through SYNC pin; when in non-master mode, it
either takes in clock signal from an external source on SYNC
pin in 30% of RT set frequency or uses RT to set its clock.
Both modes are configured via MODE pin.
the device checks if FB has reached 94% V . If not, the
REF
device enters hiccup mode, otherwise, the device considers
the soft start successful and continues to charge SS capacitor
until it reaches VCC.
1. Master mode: A 100 kW resistor connected
between MODE pin and either VCC or AGND
If the SS pin is floating, device enters hiccup.
www.onsemi.com
18
FAN65005A
will enable master mode. In this mode,
Pulse modulation refers to continuous conduction fixed
frequency pulse width modulation (short-formed Forced
CCM) and discontinuous conduction with pulse skipping
modulation (Short-formed DCM with Pulse Skipping).
When in DCM with Pulse Skipping, device works in
discontinuous conduction mode when inductor current hit 0
and may skip pulses when load becomes even lighter; device
transits to fixed frequency operation and works in
continuous conduction mode when inductor current valley
is higher than 0. Frequency synchronization refers to master
or non-master mode.
If low output voltage ripple is desired, Forced CCM PWM
operation can be selected. In this mode, continuous
conduction fixed switching frequency applies regardless of
light load or heavy load and negative current appears at light
load condition. This results in greater power loss at light
load.
FAN65005A generates its ramp and PWM signal
by its own and sends out PWM clock through
SYNC pin with 180 degree phase shift and 50%
duty cycle. If an external clock is detected on
SYNC pin that is in conflict with the internal one,
FAN65005A makes SYNC pin high impedance
until fault is cleared.
2. Non-master mode: The MODE pin connected to
either VCC or AGND through a 1 kW~5 kW
resistor or left floating enables this mode. In this
mode, the device keeps checking the SYNC pin
for incoming clocks every 2 ms. If 64 cycles of
clock are detected and the clock frequency is in
30% of RT set frequency, the device is in sync
with the clock appearing on SYNC pin. If no
clocks are detected, the number of clocks in 2 ms
does not reach 64, or the clock frequency is not
within 30% of RT set frequency, the device uses
RT to set the clock. The synchronization block
diagram is shown below.
To reduce the power loss at light load, DCM with Pulse
Skipping can be chosen. When at light load, the device
works in discontinuous conduction mode and skips pulses,
so that the power loss is reduced.
The relationship between the MODE configuration and
the actual mode is illustrated in the following table:
VCC
Table 7. OPERATION MODES WITH MODE
CONFIGURATION
CLK_PWM
10 W
Operation Mode
Master Mode
SCLK
MODE Pin
Configuration
HiZ
SYNC
AGND
Pulse Modulation
Freq Sync
10 W
VCC ←
R = 1 kW~5 kW →
MODE
Forced CCM
Non-master
RX
100 kW
SCLK_Present
SCLK_IN
VCC ←
R = 100 kW 30%
→ MODE
Forced CCM
Master
Non-master
Master
GND ←
R = 1 kW~5 kW →
MODE
DCM with Pulse
Skipping
Figure 44. Frequency Synchronization
Block Diagram
GND ←
R = 100 kW 30%
→ MODE
DCM with Pulse
Skipping
FAN65005A implements fault protection in case SYNC
pin is short-circuited to either AGND or VCC. The logic
checks voltage levels of both internal driving clock and
SYNC pin except for a 100 ns time period at every clock
transition, which is used to mask the transition glitches due
to propagation delay. These 2 logic levels are expected to be
the same when there is no pin fault. When SYNC pin fault
is detected, the driver is disabled by using high impedance
for 8 clock cycles, which makes worst case duty cycle of
~1.67% with 1 MHz frequency.
Floating
Forced CCM
Non-master
Power Good
A comparator monitors the FB voltage and controls an
open drain MOSFET. The PGOOD pin is connected to the
Drain of this MOSFET. To correctly use the PGOOD signal,
a pull-up resistor connected to an external voltage source is
required. When FB voltage exceeds 94% of V
0.6 V), PGOOD signal is asserted after a delay, t
(typical
REF
SYNC pin fault is only a local fault and doesn’t trigger
global hiccup or stop device operation. Figure 44 shows the
frequency synchronization block diagram.
, and
PG_DL
when it’s below 92% of V
it is de-asserted. PGOOD
REF
signal is valid only after device is enabled and soft start is
completed (SS ramps above 0.6 V). When OVP1 is
detected, PGOOD is de-asserted. PGOOD is re−asserted
with 5% hysteresis. Figure 45 shows the internal circuitry
connected to PGOOD pin.
Operation Modes
The MODE pin controls 2 functions: pulse modulation
and frequency synchronization.
www.onsemi.com
19
FAN65005A
External
Voltage
The worst case of over current is such conditions as
short-circuited output or saturated inductor, in which the
current exceeds 130% of current limit. In this case, device
initiates short circuit protection and enters hiccup mode
immediately.
VCC
R
PG
For low-side MOSFET, FAN65005A performs cycle by
cycle protection if its current limit is hit. At each cycle of
low-side MOSFET turn-on, its current is checked. If the
PGOOD
NOT
Power
Good
current exceeds its current limit, I , the low-side
LIM_LS
MOSFET will be turned off immediately and remains off
until next switching cycle. This process repeats until
the over current event is released (low-side MOSFET
current becomes less than I
). Low-side MOSFET
LIM_LS
Figure 45. PGOOD Block Diagram
Setting Current Limit
A resistor, R_ILIM, connected between ILIM pin and
GND is used to set the current limit for both high- and
low-side MOSFETs. An 8.5 mA internal current source
flows through R_ILIM, creating a reference voltage, and the
over current protection doesn’t affect high-side MOSFET
switching, i.e. high-side MOSFET remains normal
switching if high-side MOSFET over current event does not
occur.
Hiccup Mode
Hiccup mode is described as follows. When a fault
condition is met, both high- and low-side MOSFETs turn off
voltage drops on R
of both high- and low-side
DSON
MOSFETs are used to compare with this reference voltage.
This comparison generates an over current event. The
high-side MOSFET current is monitored in forward
direction, i.e. current flows from drain to source, while
low-side MOSFET current is monitored in a reverse
direction. When low-side MOSFET turns on in a normal
condition, its current flows from ground to switching node.
Current is NOT monitored in this case. If current flows from
switching node to ground, it is considered abnormal and is
monitored. The current limit for both high- and low-side
for a period of time, t
capacitor is discharged. Then device enters soft start. After
soft start, if the fault condition is met again, both high- and
low-side MOSFETs turn off for t
capacitor is discharged…System returns to normal
operation after the fault event is released.
(typical 1 s), and soft start
HICCUP
again and soft start
HICCUP
Over Voltage Protection (OVP)
There are 2 levels of over voltage protection: over voltage
protection 1 (OVP1) and over voltage protection 2 (OVP2),
which are defined below respectively.
MOSFETs is calculated the same way, I
= k
× R
,
LIM
ILIM
ILIM
1. OVP1 is protection when FB voltage is above
and k
parameters for both high- and low-side MOSFETs
ILIM
115% but below 130% of V . When OVP1 is
triggered, both high- and low-side MOSFETs are
turned off immediately. When FB falls to or below
REF
are shown in the Electrical Characteristic Table. If ILIM is
tied to VCC, system is in standby mode, enabling all blocks
except driver.
R_ILIM below 60 kW is defined as short-circuit, above
350 kW is considered to be open.
V , the system returns to normal operation and
REF
initiates a new PWM signal at the next clock cycle.
2. OVP2 is protection when FB voltage is above
130% of V . When OVP2 is triggered, the
Over Current Protection (OCP) and
Short Circuit Protection (SCP)
REF
high-side MOSFET is turned off immediately
while the low-side MOSFET is turned ON. If over
current event occurs during the low-side
MOSFET ON time, cycle by cycle protection will
be performed as described in “Over Current
Protection (OCP) and Short Circuit Protection
(SCP)” section. As soon as over current event is
released, the low-side MOSFET will be kept on
FAN65005A implements over current protection for
high- and low-side MOSFETs in a different way.
For high-side MOSFET, FAN65005A sets two levels of
over load protection according to the current limit setting:
over current protection (OCP) and short circuit protection
(SCP). OCP happens when the high-side MOSFET current,
i , is in the range of 100% I
DS_HS
≤ i
<
≥
LIM_HS
DS_HS
130% I
130% I
,
and SCP occurs when
i
again until FB voltage drops to or below V
.
LIM_HS
DS_HS
REF
. FAN65005A monitors MOSFET current
LIM_HS
One hiccup cycle is initiated once output voltage
reaches 100% level. After the hiccup, the part will
go into a soft start sequence and try to regulate.
If OVP2 happens during the hiccup timing period,
nothing will happen.
constantly and provides cycle by cycle peak current limit.
The high-side MOSFET is turned off whenever its current
exceeds the limit.
Once the current limit is hit, FAN65005A counts. If 1024
consecutive OCP events have reached, regardless of the FB
voltage, the system enters hiccup mode.
In the case of OVP, power good signal is de-asserted and
re-asserted after V comes down to 110% V
.
FB
REF
www.onsemi.com
20
FAN65005A
2
Under Voltage Protection (UVP)
Under voltage is a condition when output voltage is below
35% of its regulated level (checked on FB pin). If V ≤35%
L @ IPK
CMIN
+ ǒV
Ǔ2
(eq. 10)
(eq. 11)
2
OV ) VOUT * VOUT
FB
is met, then under voltage protection (UVP) is initiated,
where IC enters hiccup mode.
where I is defined as:
PK
DIL
2
I
PEAK + IOUT,MAX )
Over Temperature Protection (OTP)
The device keeps monitoring the junction temperature.
When the sensed temperature is above the protection point,
Where CMIN is the minimum value of output capacitor
required, L is the output inductor, IPK is the peak load
current, VOV is the increase in output voltage during a load
release, VOUT is output voltage.
T
, over temperature protection (OTP) event occurred
J_SD
and the system shuts down. OTP is released when the sensed
temperature is 20° lower than the trip point, T
, where the
J_SD
Input Capacitor Selection
system resets through soft-start.
Voltage and RMS current rating of the input capacitors are
critical factors. Typically input capacitor is designed based
on input voltage ripple of 2%. Capacitor voltage rating must
be at least 1.25x greater than max input voltage . Maximum
RMS current supplied by the input capacitance occurs at
50% duty cycle and when Vin =2 x Vout.
Output Inductor Selection
The output inductor is selected to meet the output ripple
requirements. The inductor value determines the converter’s
ripple current DIL. Largest ripple current occurs at highest
Vin voltage.
ǒV
ǓǒVOUTǓ
IN * VOUT
SW @ L @ VIN
RMS current varies with load as shown below:
DIL +
(eq. 6)
F
DIL(pp)2
D @ ǒ1 * D )
Ǔ (eq. 12)
I
CIN(RMS) + IOUT @
Ǹ
Lower ripple current reduced core losses in the inductor
and output voltage ripple. Highest efficiency is obtained at
low frequency with small ripple current, however with a
disadvantage of using a large inductor. Inductor value can be
chosen based on the equation below in order to not exceed
a max ripple current (usually 30% to 70% of max inductor
current)
12
Ceramic capacitors are best known for low ESR and are
highly recommended.
Loop Compensation
Selecting External Compensation:
ǒV
F
Ǔ
IN * VOUT
The FAN65004B is a voltage mode buck regulator with an
error amplifier compensated by external components to
achieve accurate output voltage regulation and to respond to
fast transient events. The goal of the compensation network
is to provide a loop gain function with the highest cross−over
frequency at adequate phase and gain margins.
The output stage (LC) of the buck regulator is a double
pole system. The resonance frequency of this lowpass filter
is shown below:
L w
@ D
(eq. 7)
SW @ DIL
Output Capacitor Selection
In general, the output capacitors should be selected to
meet the dynamic regulation requirements including ripple
voltage and load transients.
1. For ripple voltage considerations; the output bulk
maintains the DC output voltage. The use of
ceramic capacitors is recommended to sustain a
low output voltage ripple. At switching frequency
the ceramic capacitors are capacitance dominante
1
ƒp0
+
(eq. 13)
2p @ Ǹ
LCOUT
The output filter has a zero that is calculated from the
output capacitance and output capacitor ESR:
use the following equation for calculating C
where the ripple output voltage is within 1% of
Vout.
out
1
ƒz0
+
(eq. 14)
2p @ ESR @ COUT
(
)
V
OUT @ 1 * D
DOUT
+
(eq. 8)
The bode plot of the power stage, error amplifier and the
desired loop gain are drawn in the figure below. The first
8 @ FSW2 @ L @ COUT
And the RMS current through it is
zero (f ) compensates the phase lag of the pole located at the
z1
origin followed by a second zero (f ) to compensate for one
DIL(pp)
z2
I
COUT(RMS) + IOUT @
(eq. 9)
of the poles of the LC filter in order to crossover (f ) at
c
Ǹ
12
−20 dB slope. The second pole (f ) is aimed to cancel the
p2
2. The maximum capacitor value required to provide
the full, rising step, transient load current during
the response time of the inductor is shown
ESR zero and finally the third pole (f ) is to provide
p3
attenuation for frequencies above f
.
sw/2
www.onsemi.com
21
FAN65005A
Layout Guidelines
1. Place RT resistor and SS capacitor close to RT and
SS pins.
2. Use a low impedance source such as a logic gate to
drive the SYNC pin and keep the PCB trace as
short as possible.
3. Components of digital signals like EN/UVLO,
PGOOD and SYNC can be placed far away from
device.
Figure 46. Power Stage, Loop Gain and Compensator
Bode Plots
4. Place BOOT capacitor right next to BOOT and PH
pins. If flexibility of high−side MOSFET driving
strength is desired, place a resistor in series with
this BOOT capacitor. For Vin > 40 V, use Rboot
= 2 ohm.
5. Place inductor on top layer. Restrict the SW trace
to only cover the inductor pin but keep its trace as
wide as possible for thermal relief.
6. Avoid all the compensation components from
passing through, above or underneath switching
trace.
7. Keep the switching nodes away from sensitive
small signal nodes (FB). Ideally the switch nodes
printed circuit traces should be routed away and
separated from the IC and especially the quiet side
of the IC. Separate the high dv/dt traces from
sensitive small−signal nodes with ground traces or
ground planes.
For ease of calculation, with C1 >> C3:
1
ƒz1
+
(
)
2p @ R10 ) R9 @ C9
1
ƒz2
ƒp2
ƒp3
ƒc +
+
+
+
2p @ R8 @ C7
1
2p @ R9 @ C9
1
2p @ R8 @ C8
VIN
2p @ VRamp @ R10 @ C7
Thermal Considerations
The temperature gradients on the FAN65004B are shown
below. While measuring the thermal performance, place the
thermocouple at the hottest spot of the IC (not at the center
of the part).
8. Place decoupling caps right next to PVCC, VCC ,
HVBIAS and EXTBIAS.
9. The output capacitors should be placed as close to
the load as possible. Use short wide copper regions
to connect output capacitors to load to avoid
inductance and resistances.
www.onsemi.com
22
FAN65005A
Table 8. ORDERING INFORMATION
Part Number
Current Rating (A)
Input Voltage Max. (V)
Frequency Max. (kHz)
Package
FAN65005A
8
65
1000
PQFN 6.0 × 6.0 mm
PowerTrench is a registered trademark of of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
www.onsemi.com
23
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN35 6X6, 0.5P
CASE 483BE
ISSUE A
DATE 06 JUL 2021
b (35X)
(z3)
D5
e1
(3X)
e
e4
D8
1
L (19X)
k2
2
E5
(2X)
e3
3
4
(k1)
0.000
E2
(2X)
e2
E6
E4
5
6
E3
L4
(k)
L5
(z1)
L1
11
0.10
0.05
C A B
C
(z2)
e
D7
D4
D3
D6
D2
SCALE 2:1
SEE DETAIL ”A”
0.10
0.08
C
A1
A
C
FRONT VIEW
C
(A3)
SEATING
PLANE
B
D
0.10
B
SCALE 2:1
2X
A
E
C.L.
35
27
26
1
PIN#1
INDICATOR
C.L.
17
16
6
7
0.10 A
2X
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13684G
PQFN35 6X6, 0.5P
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
PQFN35 6X6, 0.5P
CASE 483BE
ISSUE A
DATE 06 JUL 2021
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13684G
PQFN35 6X6, 0.5P
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
FAN6520AIMX_NL
Switching Controller, Voltage-mode, 1A, 340kHz Switching Freq-Max, PDSO8, LEAD FREE, MS-012AA, SOIC-8
FAIRCHILD
FAN6520AIM_NL
Switching Controller, Voltage-mode, 1A, 340kHz Switching Freq-Max, PDSO8, LEAD FREE, MS-012AA, SOIC-8
FAIRCHILD
FAN6520AMX_NL
Switching Controller, Voltage-mode, 1A, 340kHz Switching Freq-Max, PDSO8, LEAD FREE, MS-012AA, SOIC-8
FAIRCHILD
FAN6520AM_NL
Switching Controller, Voltage-mode, 1A, 340kHz Switching Freq-Max, PDSO8, LEAD FREE, MS-012AA, SOIC-8
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明