FAN6921BMRMY [ONSEMI]
mWSaver™ Combo Power Factor Correction + QR Flyback Controller, Brown Out Protection;
| 型号： | FAN6921BMRMY |
| 厂家： | 
ONSEMI |
| 描述： | mWSaver™ Combo Power Factor Correction + QR Flyback Controller, Brown Out Protection |
| 文件： | 总22页 (文件大小：1048K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Integrated Critical Mode PFC
and Quasi-Resonant Current
Mode PWM Controller
FAN6921BMR
Description
SOIC−16
CASE 751BG
The highly integrated FAN6921BMR combines Power Factor
Correction (PFC) controller and Quasi−Resonant PWM controller.
Integration provides cost effect design and allows for fewer external
components.
For PFC, FAN6921BMR uses a controlled on−time technique to
provide a regulated DC output voltage and to perform natural power
factor correction. With an innovative THD optimizer, FAN6921BMR
can reduce input current distortion at zero−crossing duration
to improve THD performance.
For PWM, FAN6921BMR provides several functions to enhance
the power system performance: valley detection, green−mode
operation, high / low line over power compensation. FAN6921BMR
provides many protection functions as well: secondary−side
open−loop and over−current with auto recovery protection, external
latch triggering, adjustable over−temperature protection by RT pin
MARKING DIAGRAM
$Y&Z&2&K
FAN6921BMR
MYD
$Y
&Z
&2
&K
= onsemi Logo
= Assembly Plant Code
= 2−Digit Date Code Format
= 2−Lot Run Traceability Code
FAN6921BMRMYD= Specific Device Code Data
and external NTC resistor, internal over−temperature shutdown, V
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
DD
pin OVP, and DET pin over−voltage for output OVP,
and brown−in / out for AC input voltage UVP.
The FAN6921BMR controller is available in a 16−pin small outline
package (SOP).
Features
• Integrated PFC and Flyback Controller
• Critical Mode PFC Controller
• Zero−Current Detection for PFC Stage
• Quasi−Resonant Operation for PWM Stage
• Internal Minimum t
8 ms for QR PWM Stage
OFF
• Internal 10 ms Soft−Start for PWM
• Brownout Protection
• High / Low Line Over−Power Compensation
• Auto−Recovery Over−Current Protection
• Auto−Recovery Open−Loop Protection
• Externally Latch Triggering (RT Pin)
• Adjustable Over−Temperature Latched (RT Pin)
• VDD Pin and Output Voltage OVP (Latched)
• Internal Over−Temperature Shutdown (140°C)
• This is a Pb−Free Device
Applications
• AC/DC NB Adapters
• Open−Frame SMPS
• Battery Charger
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
September, 2022 − Rev. 2
FAN6921BMR/D
FAN6921BMR
ORDERING INFORMATION
Part Number
OLP Mode
Operating Temperature Range
−40°C to 105°C
Package
Shipping
FAN6921BMRMY
Recovery
16−Pin Small Outline Package
2.500 /
Tape & Reel
(SOP)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
APPLICATION DIAGRAM
4
3
14
ZCD
6
1
16
INV
OPFC CSPFC
RANGE HV
15
8
13
9
NC
VIN
FAN6921B
OPWM
GND
5
CSPWM
VDD
COMP
2
RT
FB DET
12 11 10
7
Figure 1. Typical Application
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2
FAN6921BMR
INTERNAL BLOCK DIAGRAM
2
16
7
15
6
I
HV
27.5V
3
4
14
8
11
5
1
10
9
13
12
Figure 2. Internal Block Diagram
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3
FAN6921BMR
PIN CONFIGURATION
RANGE
COMP
INV
HV
1
2
3
4
5
16
15
NC
ZCD
VIN
RT
14
13
CSPFC
CSPWM
OPFC
VDD
12
11
10
FB
6
7
8
DET
GND
OPWM
9
Figure 3. Pin Configuration
PIN DEFINITIONS
Pin No.
Name
Description
1
RANGE
RANGE pin’s impedance changes according to VIN pin voltage level. When the input voltage detected by VIN
pin is lower than a threshold voltage, it sets to high impedance; whereas it sets to low impedance if input voltage
is high level.
2
COMP
Output pin of the error amplifier. It is a transconductance type error amplifier for PFC output voltage feedback.
Proprietary multi−vector current is built−in to this amplifier. Therefore the compensation for PFC voltage feed-
back loop allows a simple compensation circuit between this pin and GND.
3
4
INV
Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage divider and pro-
vides PFC output over− and under−voltage protections.
CSPFC
Input to the PFC over−current protection comparator that provides cycle−by−cycle current limiting protection.
When the sensed voltage across the PFC current sensing resistor reaches the internal threshold (0.82 V typical),
the PFC switch is turned off to activate cycle−by−cycle current limiting.
5
CSPWM Input to the comparator of the PWM over−current protection and performs PWM current−mode control with FB
pin voltage. A resistor is used to sense the switching current of PWM switch and the sensing voltage is applied
to the CSPWM pin for the cycle−by−cycle current limit, current mode control, and high / low line over−power
compensation according to DET pin source current during PWM t time.
ON
6
7
OPFC
VDD
Totem−pole driver output to drive the external power MOSFET. The clamped gate output voltage is 15.5 V.
Power supply. The threshold voltage for startup and turn−off is 18 V and 7.5 V, respectively. The startup current
is less than 30 mA and the operating current is lower than 10 mA.
8
OPWM
Totem−pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output
voltage is 17.5 V.
9
GND
DET
The power ground and signal ground.
10
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for the following
purposes:
• Producing an offset voltage to compensate the threshold voltage of PWM current limit for providing over−power
compensation. The offset is generated in accordance with the input voltage when PWM switch is on.
• Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley voltage switching
and minimize the switching loss on PWM switch.
• Providing output over−voltage protection. A voltage comparator is built−in to the DET pin. The DET pin detects
the flat voltage through a voltage divider paralleled with auxiliary winding. This flat voltage is reflected to
the secondary winding during PWM inductor discharge time. If output OVP and this flat voltage is higher than
2.5 V, the controller enters latch mode and stops all PFC and PWM switching operation.
11
12
FB
RT
Feedback voltage pin. This pin is used to receive output voltage level signal to determine PWM gate duty for
regulating output voltage. The FB pin voltage can also activate open−loop, over−load protection, and output−
short circuit protection if the FB pin voltage is higher than a threshold of around 4.2 V for more than 50 ms.
The input impedance of this pin is a 5 kW equivalent resistance. A 1/3 attenuator is connected between the FB
pin and the input of the CSPWM/FB comparator.
Adjustable over−temperature protection and external latch triggering. A constant current is flowed out of the RT
pin. When RT pin voltage is lower than 0.8 V (typical), latch mode protection is activated and stops all PFC and
PWM switching operation until the AC plug is removed.
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4
FAN6921BMR
PIN DEFINITIONS (continued)
Pin No.
Name
Description
13
VIN
Line−voltage detection for brown−in / out protections. This pin can receive the AC input voltage level through
a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pin’s status, but it can also
perform brown−in / out protection for AC input voltage UVP.
14
ZCD
Zero−current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to PFC inductor
winding to detect the ZCD voltage signal once the PFC inductor current discharges to zero. When the ZCD volt-
age signal is detected, the controller starts a new PFC switching cycle. When the ZCD pin voltage is pulled to
under 0.2 V (typical), it disables the PFC stage and the controller stops PFC switching. This can be realized with
an external circuit if disabling the PFC stage is desired.
15
16
NC
HV
No connection.
High−voltage startup. HV pin is connected to the AC line voltage through a resistor (100 kW typical) for providing
a high charging current to V capacitor.
DD
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−
Max
30
Unit
V
V
DD
V
HV
DC Supply Voltage
HV
−
500
V
V
OPFC, OPWM
−0.3
−0.3
−0.3
−
25.0
7.0
V
H
V
Others (INV, COMP, CSPFC, DET, FB, CSPWM, RT)
Input Voltage to ZCD Pin
V
L
V
ZCD
12.0
800
V
P
Power Dissipation
mW
°C/W
°C/W
°C
°C
°C
V
D
JA
JC
q
q
Thermal Resistance (Junction−to−Air)
−
104
Thermal Resistance (Junction−to−Case)
Operating Junction Temperature
−
41
T
−40
−55
−
+150
+150
+260
4500
1250
J
T
STG
Storage Temperature Range
T
Lead Temperature (Soldering 10 Seconds)
Human Body Model: JESD22−A114 (All Pins Except HV Pin) (Note 2)
Charged Device Model: JESD22−C101 (All Pins Except HV Pin) (Note 2)
L
ESD
−
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All voltage values, except differential voltages, are given with respect to GND pin.
2. All pins including HV pin: CDM = 750 V, HBM 1000 V.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Operating Ambient Temperature
Min
−40
−
Max
+105
25
Unit
°C
V
T
A
V
Continuously Operating Voltage
OP
HV−MIN
V
Minimum Startup Voltage on HV Pin
−
50
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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FAN6921BMR
ELECTRICAL CHARACTERISTICS (V = 15 V, T = −40°C ~ 105°C (T = T ), unless otherwise noted)
DD
A
A
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
DD
SECTION
V
Turn−On Threshold Voltage
16.5
18.0
19.5
DD−ON
DD−PWM−OFF
V
V
V
PWM Off Threshold Voltage
Turn−Off Threshold Voltage
Startup Current
9
6.5
−
10
7.5
20
11
8.5
30
V
V
DD−OFF
I
V
= V − 0.16 V,
DD−ON
mA
DD−ST
DD
Gate Open
I
Operating Current
V
= 15 V,
−
−
−
10
mA
mA
DD−OP
DD
OPFC, OPWM = 100 kHz,
, C = 2 nF
C
L−PFC
L−PWM
I
Green−Mode Operating Supply
Current (Average)
V
DD
= 15 V,
5.5
−
DD−GREEN
OPWM = 450 Hz,
C
= 2 nF
L−PWM
I
Operating Current at PWM−Off
Phase
V
DD
= V
− 0.5 V
70
120
170
mA
DD−PWM−OFF
DD−PWM−OFF
V
V
Over−Voltage Protection
26.5
27.5
28.5
V
DD−OVP
DD
(Latch−Off)
t
V
V
OVP Debounce Time
100
150
120
200
ms
VDD−OVP
DD
I
Over−Voltage Protection
Latch−Up Holding Current
V
DD
= 7 V
−
−
mA
DD−LATCH
DD
HV STARTUP CURRENT SOURCE SECTION
Supply Current Drawn from HV Pin
I
V
DD
= 90 V (V = 120 V),
1.3
−
−
−
mA
HV
AC
DC
V
= 0 V
HV = 500 V, V = V
+ 1 V
−
1
mA
DD
DD−OFF
VIN AND RANGE SECTION
V
Threshold Voltage for AC Input
0.95
1.00
1.05
V
V
VIN−UVP
Under−Voltage Protection
V
Under−Voltage Protection Reset
Voltage (for Startup)
V
V
V
VIN−UVP
+0.35 V
VIN−RE−UVP
VIN−UVP
+0.25 V
VIN−UVP
+0.30 V
t
Under−Voltage Protection
Debounce Time (No Need at
Startup and Hiccup Mode)
70
100
130
ms
VIN−UVP
V
High V
Threshold for RANGE
2.40
2.05
70
2.45
2.10
100
2.50
2.15
130
V
V
VIN−RANGE−H
VIN
Comparator
V
Low V
Threshold for RANGE
VIN−RANGE−L
VIN
Comparator
t
Range−Enable / Disable Debounce
Time
ms
RANGE
V
Output Low Voltage of RANGE Pin I =1 mA
−
−
−
−
0.5
50
V
RANGE−OL
O
I
Output High Leakage Current
of RANGE Pin (Note 3)
RANGE = 5 V
nA
RANGE−OH
t
PFC Maximum On Time
22
25
28
ms
ON−MAX−PFC
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FAN6921BMR
ELECTRICAL CHARACTERISTICS (V = 15 V, T = −40°C ~ 105°C (T = T ), unless otherwise noted) (continued)
DD
A
A
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
PFC STAGE
VOLTAGE ERROR AMPLIFIER SECTION
Gm Transconductance (Note 3)
100
125
150
mmho
V
REF
Feedback Comparator Reference
Voltage
2.465
2.500
2.535
V
V
Clamp High Feedback Voltage
RANGE = Open
RANGE = Ground
2.70
2.60
1.06
1.04
2.25
−
2.75
2.65
−
2.80
2.70
1.14
1.08
2.45
2.95
2.80
90
V
INV−H
V
RATIO
Clamp High Output Voltage Ratio
(Note 3)
V /V RANGE = Open
INVH REF,
V/V
V
/V
RANGE = Ground
−
INVH REF,
V
Clamp Low Feedback Voltage
2.35
2.90
2.75
70
V
V
INV−L
V
Over−Voltage Protection for INV
Input (Note 3)
RANGE = Open
INV−OVP
RANGE = Ground
−
t
Over−Voltage Protection
Debounce Time (Note 3)
50
ms
V
INV−OVP
V
Under−Voltage Protection for INV
Input
0.35
50
0.45
70
0.55
90
INV−UVP
t
Under−Voltage Protection
Debounce Time
ms
V
INV−UVP
V
PWM and PFC Off Threshold for
Brownout Protection
1.15
1.55
1.20
1.60
1.25
1.65
INV−BO
V
Limited Voltage on COMP Pin for
Brownout Protection
V
COMP−BO
V
Comparator Output High Voltage
4.8
−
6.0
V
V
COMP
V
Zero Duty Cycle Voltage
on COMP Pin
1.10
1.25
1.40
OZ
I
Comparator Output Source Current
V
V
= 2.3 V, V
= 1.5 V
COMP
15
0.50
20
30
0.75
30
45
1.00
40
mA
mA
mA
COMP
INV
= 1.5 V
INV
Comparator Output Sink Current
RANGE = Open,
= 2.75 V, V
V
INV
= 5 V
= 5 V
COMP
RANGE = Ground,
20
30
40
V
INV
= 2.65 V, V
COMP
PFC CURRENT SENSE SECTION
V
Threshold Voltage for Peak
Current Cycle−by−Cycle Limit
V
COMP
= 5 V
−
0.82
−
V
CSPFC
t
Propagation Delay
−
110
180
0.95
200
250
1.00
ns
ns
PD
t
Leading−Edge Blanking Time
110
0.90
BNK
A
CSPFC Compensation Ratio
for THD (Note 3)
V/V
V
PFC OUTPUT SECTION
V
Z
PFC Gate Output Clamping
Voltage
V
DD
= 25 V
14.0
15.5
17.0
V
V
PFC Gate Output Voltage Low
PFC Gate Output Voltage High
PFC Gate Output Rising Time
PFC Gate Output Falling Time
V
DD
V
DD
V
DD
V
DD
= 15 V, I = 100 mA
−
8
−
−
1.5
−
V
V
OL
O
V
OH
= 15 V, I = 100 mA
O
t
= 12 V, C = 3 nF, 20~80%
30
30
65
50
100
70
ns
ns
R
L
t
= 12 V, C = 3 nF, 80~20%
L
F
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FAN6921BMR
ELECTRICAL CHARACTERISTICS (V = 15 V, T = −40°C ~ 105°C (T = T ), unless otherwise noted) (continued)
DD
A
A
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
PFC ZERO CURRENT DETECTION SECTION
V
ZCD
Input Threshold Voltage Rising
Edge
V
ZCD
Increasing
1.9
2.1
2.3
V
V
Threshold Voltage Hysteresis
Upper Clamp Voltage
V
Decreasing
= 3 mA
0.25
8
0.35
10
0.45
−
V
V
V
V
ZCD−HYST
ZCD
V
I
ZCD
ZCD−HIGH
V
Lower Clamp Voltage
0.40
1.3
0.65
1.4
0.90
1.5
ZCD−LOW
V
Starting Source Current
Threshold Voltage
ZCD−SSC
t
Maximum Delay from ZCD
V
V
= 5 V, f = 60 kHz
100
−
200
ns
DELAY
COMP
S
to Output Turn−On
t
Restart Time
300
1.5
500
2.5
700
3.5
ms
ms
RESTART−PFC
t
Inhibit Time (Maximum Switching
Frequency Limit)
= 5 V
INHIB
COMP
V
PFC Enable/ Disable Function
Threshold Voltage
0.15
100
0.2
0.25
200
V
ZCD−DIS
ZCD−DIS
t
PFC Enable/ Disable Function
Debounce Time
V
ZCD
= 100 mV
150
ms
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FAN6921BMR
ELECTRICAL CHARACTERISTICS (V = 15 V, T = −40°C ~ 105°C (T = T ), unless otherwise noted) (continued)
DD
A
A
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
PWM STAGE
FEEDBACK INPUT SECTION
A
V
Input−Voltage to Current Sense
Attenuation (Note 3)
A
= DV
CSPWM
/ DV ,
FB
1⁄2.75
1⁄3.00
1⁄3.25
V/V
V
CSPWM
0 < V
< 0.9
Z
Input Impedance (Note 3)
Bias Current (Note 3)
FB > V
FB = V
3
5
7
kW
mA
V
FB
G
I
−
1.2
0.9
4.2
2.0
1.1
4.5
OZ
OZ
V
OZ
Zero Duty−cycle Input Voltage
0.7
3.9
V
Open−Loop Protection Threshold
Voltage
V
FB−OLP
t
The Debounce Time for Open
Loop Protection
40
50
60
ms
ms
FB−OLP
t
−
Internal Soft−Start Time (Note 3)
V
FB
= 0 V~3.6 V
8.5
9.5
10.5
FB SS
DET PIN OVP AND VALLEY DETECTION SECTION
V
Comparator Reference Voltage
Open−Loop Gain (Note 3)
Gain Bandwidth (Note 3)
2.45
−
2.50
60
2.55
−
V
dB
DET−OVP
A
V
BW
−
1
−
MHz
ms
t
Output OVP (Latched) Debounce
Time
100
150
200
DET−OVP
I
Maximum Source Current
Lower Clamp Voltage
V
= 0 V
−
−
1
mA
V
DET−SOURCE
DET
V
I
= 1 mA
0.5
150
0.7
200
0.9
250
DET−LOW
VALLEY−DELAY
DET
t
Delay Time from Valley Signal
Detected to Output Turn−on
ns
t
Leading−Edge Blanking Time
for DET−OVP (2.5 V) and Valley
Signal when PWM MOS Turns Off
(Note 3)
3
4
5
ms
ms
OFF−BNK
t
Time−Out after t
(Note 3)
8
9
10
TIME−OUT
OFF−MIN
PWM OSCILLATOR SECTION
t
Maximum On Time
Minimum On Time
38
7
45
8
52
9
ms
ms
ON−MAX−PWM
t
V
V
≥ V , T = 25°C
N A
OFF−MIN
FB
= V
32
37
42
FB
G
V
V
Beginning of Green−On Mode at
1.95
2.10
2.25
V
V
V
N
FB Voltage Level
Beginning of Green−Off Mode at
FB Voltage Level
1.00
1.15
0.1
1.30
G
DV
Hysteresis for Beginning
of Green−Off Mode at FB Voltage
Level (Note 3)
−
−
G
V
Threshold Voltage on FB Pin for
RANGE Pin Internally Open
RANGE Pin Internally Ground
RANGE Pin Internally Open
RANGE Pin Internally Ground
PFC Enable→Disable
1.70
1.60
1.85
1.70
400
2.0
1.75
1.65
1.90
1.75
500
2.5
1.80
1.70
1.95
1.80
600
3.0
V
V
CTL−PFC−OFF
PFC Enable→Disable
V
Threshold Voltage on FB Pin for
PFC Disable→Enable
CTL−PFC−ON
t
PFC Disable Debounce Time
PFC Enable Debounce Time
Start Timer (Time−Out Timer)
ms
ms
ms
ms
PFC−OFF
t
PFC Disable→Enable
PFC−ON
STARTER−PWM
t
V
< V
1.85
22
2.25
28
2.65
34
FB
FB
G
V
> V
FB−OLP
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FAN6921BMR
ELECTRICAL CHARACTERISTICS (V = 15 V, T = −40°C ~ 105°C (T = T ), unless otherwise noted) (continued)
DD
A
A
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
PWM OUTPUT SECTION
V
PWM Gate Output Clamping
Voltage
V
DD
= 25 V
16.0
17.5
19.0
V
CLAMP
V
PWM Gate Output Voltage Low
PWM Gate Output Voltage High
PWM Gate Output Rising Time
PWM Gate Output Falling Time
V
V
= 15 V, I = 100 mA
−
8
−
−
−
−
1.5
−
V
V
OL
DD
O
V
OH
= 15 V, I = 100 mA
O
DD
t
C = 3 nF, V = 12 V, 20~80%
80
40
110
70
ns
ns
R
L
DD
t
C = 3 nF, V = 12 V, 20~80%
F
L
DD
CURRENT SENSE SECTION
t
Delay to Output
−
150
0.84
0.72
0.58
0.40
0.30
0.10
300
−
200
0.87
0.75
0.61
0.46
0.35
0.15
−
ns
V
PD
V
The Limit Voltage on CSPWM
Pin for Over Power Compensation
0.81
0.69
0.55
0.34
0.25
0.05
−
I
I
I
I
t
t
< 75 mA, T = 25°C
LIMIT
DET
DET
DET
DET
A
= 185 mA, T = 25°C
A
= 350 mA, T = 25°C
A
= 550 mA, T = 25°C
A
V
Slope Compensation (Note 3)
V
= 45 ms, RANGE = Open
= 0 ms
SLOPE
ON
ON
t
Leading−Edge Blanking Time
ns
V
ON−BNK
V
CSPWM Pin Floating V
Clamped High Voltage
CSPWM Pin Floating
CSPWM Pin Floating
4.5
5.0
CS−FLOATING
CSPWM
t
The Delay Time once CSPWM
Pin Floating (Note 3)
−
150
−
ms
CS−H
RT PIN OVER−TEMPERATURE PROTECTION SECTION
T
Internal Threshold Temperature
for OTP (Note 3)
125
140
30
155
°C
°C
OTP
T
Hysteresis Temperature for
Internal OTP (Note 3)
−
−
OTP−HYST
I
Internal Source Current of RT Pin
90
100
110
mA
V
RT
V
Latch−Mode Triggering Voltage
0.75
0.80
0.85
RT−LATCH
V
Latch−Mode Release Voltage
(Note 3)
V
V
V
V
RT−LATH
+0.15
RT−LATH
+0.20
RT−LATH
+0.25
RT−RE−LATCH
V
Threshold Voltage for Two−level
Debounce Time
0.45
0.50
0.55
V
RT−OTP−LEVEL
t
Debounce Time for OTP
−
10
−
ms
RT−OTP−H
t
Debounce Time for Externally
Triggering
V
RT
< V
RT−OTP−LEVEL
70
110
150
ms
RT−OTP−L
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Guaranteed by design.
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10
FAN6921BMR
TYPICAL PERFORMANCE CHARACTERISTICS (THESE CHARACTERISTIC GRAPHS ARE NORMALIZED AT T = 25°C)
A
18.5
18.0
17.5
17.0
16.5
11.0
10.5
10.0
9.5
9.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 5. PWM Off Threshold Voltage
Figure 4. Turn−On Threshold Voltage
29.0
28.5
28.0
27.5
27.0
8.5
8.0
7.5
7.0
6.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 7. VDD Over−Voltage Protection Threshold
Figure 6. Turn−Off Threshold Voltage
8.0
7.0
16.0
14.0
12.0
10.0
8.0
6.0
5.0
4.0
6.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 9. Operating Current
Figure 8. Startup Current
2.60
2.55
2.50
2.45
2.40
17.0
16.5
16.0
15.5
15.0
14.5
14.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 10. PFC Output Feedback Reference Voltage
Figure 11. PFC Gate Output Clamping Voltage
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11
FAN6921BMR
TYPICAL PERFORMANCE CHARACTERISTICS (THESE CHARACTERISTIC GRAPHS ARE NORMALIZED AT T = 25°C)
A
(CONTINUED)
0.95
0.90
0.85
28.0
27.0
26.0
25.0
24.0
23.0
22.0
0.80
0.75
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 13. PFC Peak Current Limit Voltage
Figure 12. PFC Maximum On−Time
19.0
18.5
18.0
17.5
17.0
16.5
16.0
50.0
48.0
46.0
44.0
42.0
40.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 14. PWM Gate Output Clamping Voltage
Figure 15. PWM Maximum ON−Time
1.4
1.3
1.2
1.1
1.0
2.3
2.2
2.1
2.0
1.9
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 17. Beginning of Green−Off Mode at VFB
Figure 16. Beginning of Green −On Mode at VFB
9.0
8.5
8.0
7.5
7.0
42.0
40.0
38.0
36.0
34.0
32.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 19. PWM Minimum Off−Time for VFB = VG
Figure 18. PWM Minimum Off−Time for VFB > VN
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12
FAN6921BMR
TYPICAL PERFORMANCE CHARACTERISTICS (THESE CHARACTERISTIC GRAPHS ARE NORMALIZED AT T = 25°C)
A
(CONTINUED)
1.0
2.60
0.9
2.55
0.8
2.50
0.7
0.6
2.45
2.40
−40 −25 −10
0.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
110 125
5
20 35 50 65 80 95
Temperature (°C)
Temperature (°C)
Figure 21. Reference Voltage for Output
Over−Voltage Protection of DET Pin
Figure 20. Lower Clamp Voltage of DET Pin
110
0.90
0.85
0.80
0.75
0.70
105
100
95
90
110 125
−40 −25 −10
5
20 35 50 65
80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95
Temperature (°C)
Temperature (°C)
Figure 22. Internal Source Current of RT Pin
Figure 23. Over Temperature Protection Threshold
Voltage of RT Pin
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13
FAN6921BMR
FUNCTIONAL DESCRIPTION
PFC STAGE
Multi−Vector Error Amplifier and THD Optimizer
shows the difference between calculated fixed on−time
mechanism and fixed on−time with THD Optimizer during
a half AC cycle.
For better dynamic performance, faster transient
response, and precise clamping on PFC output,
FAN6921BMR uses a trans−conductance type amplifier
with proprietary innovative multi−vector error amplifier
The schematic diagram of this amplifier is shown in
Figure 24. The PFC output voltage is detected from the INV
Error
Amplifier
PFC V
O
V
COMP
PFC RS
MOS
2.5 V
R
1
pin by an external resistor divider circuit that consists of R
Filp−Flop
1
3
and R . When PFC output variation voltage reaches 6% over
2
INV
+
THD
S
4
or under the reference voltage 2.5 V, the multi−vector error
amplifier adjusts its output sink or source current to increase
the loop response to simplify the compensated circuit.
R
Optimizer
2
R
S
+
CSPFC
Sawtooth
Generator
FAN6921B
Figure 25. Multi−Vector Error Amplifier with THD
PFC V
O
2.65 V
2.35 V
Optimizer
R
1
C
O
I
(Fixed On−Time)
COMP
LAVG
2.5 V
I
(with THD Optimizer)
INV
LAVG
C
COMP
Error
Amplifier
R
2
FAN6921B
Figure 24. Multi−Vector Error Amplifier
Gate Signal
with
THD Optimizer
The feedback voltage signal on the INV pin is compared
V
COMP
Sawtooth
Gate Signal
with
with reference voltage 2.5 V, which makes the error
amplifier source or sink current to charge or discharge its
output capacitor CCOMP. The COMP voltage is compared
with the internally generated sawtooth waveform
to determine the on−time of PFC gate. Normally, with lower
feedback loop bandwidth, the variation of the PFC gate
on−time should be very small and almost constant within
one input AC cycle. However, the power factor correction
circuit operating at light load condition has a defect, zero
crossing distortion; which distorts input current and makes
the system’s Total Harmonic Distortion (THD) worse.
To improve the result of THD at light load condition,
especially at high input voltage, an innovative THD
Optimizer is inserted by sampling the voltage across
the current−sense resistor. This sampling voltage on
current−sense resistor is added into the sawtooth waveform
to modulate the on−time of PFC gate, so it is not constant
on−time within a half AC cycle. The method of operation
block between THD Optimizer and PWM are shown in
Figure 25. After THD Optimizer processes, around
the valley of AC input voltage, the compensated on−time
becomes wider than the original. The PFC ontime, which is
around the peak voltage, is narrowed by the THD Optimizer.
The timing sequences of the PFC MOS and the shape of
the inductor current are shown in Figure 26. Figure 27
Fixed On−Time
Figure 26. Operation Waveforms of Fixed On−Time
with and without THD Optimizer
Input Current
1.8
1.5
1.2
0.9
0.6
P : 90 W
O
Input Voltage: 90 VAC
PFC Inductor: 460 mH
CS Resistor: 0.15 W
0.3
0
0.0042 0.0056
0.0014 0.0028
0.0069 0.0083
0
Fixed On−time with THD Optimizer
Fixed On−time
Figure 27. Calculated Waveforms of Fixed
On−Time with and without THD Optimizer During
a Half AC Cycle
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14
FAN6921BMR
RANGE Pin
V
ZCD
A built−in low voltage MOSFET can be turned on or off
according to VVIN voltage level. The drain pin of this
internal MOSFET is connected to the RANGE pin.
Figure 28 shows the status curve of VVIN voltage level
and RANGE impedance (open or ground).
10 V
2.1 V
1.75 V
V
t
DS
RANGE = Ground
RANGE = Open
PFCVO
V
IN.MAX
V
VIN
V
V
VIN−RANGE−L
VIN−RANGE−H
Figure 28. Hysteresis Behavior between RANGE Pin
and VIN Pin Voltage
t
PFC
Gate
Inhibit
Time
Zero Current Detection (ZDC Pin)
Figure 29 shows the internal block of zero−current
detection. The detection function is performed by sensing
the information on an auxiliary winding of the PFC inductor.
Referring to Figure 30, when PFC MOS is off, the stored
energy of the PFC inductor starts to release to the output
load. Then the drain voltage of PFC MOS starts to decrease
since the PFC inductor resonates with parasitic capacitance.
Once the ZCD pin voltage is lower than the triggering
voltage (1.75 V typical), the PFC gate signal is sent again
to start a new switching cycle.
If PFC operation needs to be shut down due to abnormal
condition, it is suggested to pull the ZCD pin LOW, voltage
under 0.2 V (typical), to activate the PFC disable function
to stop PFC switching operation.
For preventing excessive high switching frequency
at light load, a built−in inhibit timer is used to limit
t
Figure 30. Operation Waveforms of PFC
Zero−Current Detection
PROTECTION FOR PFC STAGE
PFC Output Voltage UVP and OVP (INV Pin)
FAN6921BMR provides several kinds of protection for
PFC stage. PFC output over− and under−voltage are
essential for PFC stage. Both are detected and determined by
INV pin voltage, as shown in Figure 31. When INV pin
voltage is over 2.75 V or under 0.45 V, due to overshoot
or abnormal conditions and lasts for a de−bounce time
around 70 ms, the OVP or UVP circuit is activated to stop
PFC switching operation immediately.
The INV pin is not only used to receive and regulate PFC
output voltage, but can also perform PFC output OVP/ UVP
protection. For failure−mode test, this pin can shut down
PFC switching if pin floating occurs.
the minimum t
time. Even if the ZCD signal has been
OFF
detected, the PFC gate signal still would not be sent during
the inhibit time (2.5 ms typical).
PFC V
O
Debounce
Time
Driver
1.4 V
PFC Gate
Driver
V
(2.5 V)
REF
R
1
V
COMP
Q
R
COMP
C
0.2 V
INV
2
C
ZCD
O
V
Voltage
Detector
S
AC
1
Error
Amplifier
5
1.75 V
R
R
2
ZCD
L
b
COMP
OVP = (V
UVP = (V
≥ 2.75 V)
≤ 0.45 V)
INV
INV
2.1 V
S
Q R
10 V
1:n
PFC Gate On
FAN6921B
FAN6921B
Figure 31. Internal Block of PFC
Over− and Under−Voltage Protection
Figure 29. Internal Block of the Zero−Current
Detection
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15
FAN6921BMR
PFC Peak Current Limiting (CSPFC Pin)
During PFC stage switching operation, the PFC switch
current is detected by current−sense resistor on the CSPFC
pin and the detected voltage on this resistor is delivered
AC Input
to input terminal of
a comparator and compared
V
COMP−BO
with a threshold voltage 0.82 V (typical). Once the CSPFC
pin voltage is higher than the threshold voltage, PFC gate is
turned off immediately.
V
COMP
1.6 V
The PFC peak switching current is adjustable by
the current−sense resistor. Figure 32 shows the measured
waveform of PFC gate and CSPFC pin voltage.
V
VIN
V
V
INV−RE−UVP
0 V
2.5 V
INV−BO
PFC MOS Current Limit
0.82V
V
INV
1.2 V
CSPFC
OPFC
OPWM
OPFC
Brownout
Protection
Hiccup
Brownout
Protection
Debounce
Time 100 ms
Mode
Figure 33. Operation Waveforms of Brown−In/Out
Figure 32. Cycle−by−Cycle Current Limiting
Protection
Brown−In / Out Protection (VIN Pin)
With AC voltage detection, FAN6921BMR can perform
brown−in/ out protection (AC voltage UVP). Figure 33
shows the key operation waveforms of brown−in / out
protection. Both use the VIN pin to detect AC input voltage
level and the VIN pin is connected to AC input by a resistor
VDD
VDD Hiccup Mode
Brownout
AC Input
Brown−In
divider (refer to Figure 1); therefore, the V
voltage is
VIN
proportional to the AC input voltage. When the AC voltage
drops, and V voltage is lower than 1 V for 100 ms,
VIN
OPWM
OPFC
the UVP protection is activated and the COMP pin voltage
is clamped to around 1.6 V. Because PFC gate duty is
determined by comparing sawtooth waveform and COMP
pin voltage, lower COMP voltage results in narrow PFC
on−time, so that the energy converged is limited and the PFC
output voltage decreases. When INV pin is lower than 1.2 V,
FAN6921BMR stops all PFC and PWM switching operation
Figure 34. Measured Waveform of Brown−In/Out
Protection (Adapter Application)
immediately until V
voltage drops to turn−off voltage
DD
then raises to turn−on voltage again (UVLO).
When the brownout protection is activated, all switching
PWM STAGE
operation is turned off, V voltage enters hiccup mode up
DD
HV Startup and Operating Current (HV Pin)
and down continuously. Until VVIN voltage is higher than
The HV pin is connected to AC line through a resistor
(refer to Figure 1). With a built−in high−voltage startup
circuit, when AC voltage is applied to power system,
FAN6921BMR provides a high current to charge external
1.3 V (typical) and V
reaches turn−on voltage again,
DD
the PWM and PFC gate is sent out.
The measured waveforms of brown−in / out protection are
shown in Figure 34.
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16
FAN6921BMR
V
capacitor to speed up controller’s startup time and build
detected, FAN6921BMR outputs PWM gate signal to turn
on the switch and begin a new switching cycle.
With green mode operation and valley detection, at light
load condition; power system can perform extended valley
switching at DCM operation and can further reduce
switching loss for getting better conversion efficiency.
DD
up normal rated output voltage within three seconds. To save
power consumption, after V voltage exceeds turn−on
voltage and enters normal operation; this high voltage
startup circuit is shut down to avoid power loss from startup
resistor.
DD
Figure 35 shows the characteristic curve of V voltage
The FB pin voltage versus t
time characteristic
DD
OFF−MIN
and operating current I . When V voltage is lower than
curve is shown in Figure 37. As Figure 37 shows,
DD
DD
V
,
FAN6921BMR stops all switching
FAN6921BMR can narrow down to 2.25 ms t
time,
DD−PWM−OFF
OFF
operation and turns off some internal unnecessary circuit to
reduce operating current. By doing so, the period from
which is around 440 Hz switching frequency.
Referring to Figure 1 and Figure 2, FB pin voltage is not
only used to receive secondary feedback signal to determine
gate on−time, but also determines PFC stage on or off status.
At no−load or light−load conditions, if PFC stage is set to be
off; that can reduce power consumption from PFC stage
switching device and increase conversion efficiency. When
output loading is decreased, the FB pin voltage becomes
lower and, therefore, the FAN6921BMR can detect the
output loading level according to the FB pin voltage to
control the on / off status of the PFC part.
V
to V
can be extended and the hiccup
DD−PWM−OFF
DD−OFF
mode frequency can be decreased to reduce the input power
in case of output short circuit. Figure 36 shows the typical
waveforms of V voltage and gate signal at hiccup mode
DD
operation.
I
DD
I
DD−OP
t
OFF−MIN
I
2.25 ms
DD−PWM−OFF
I
DD−ST
PFC ON
V
DD
V
V
V
DD−OFF DD−PWM−OFF
DD−ON
PFC OFF
37 ms
8 ms
Figure 35. VDD vs. IDD−OP Characteristic Curve
V
CTL−PFC−ON
V
CTL−PFC−OFF
V
DD−ON
I
DD−OP
1.15 V (V
2.1 V (V
N)
G)
V
V
DD−PWM−OFF
Figure 37. VFB Voltage vs. tOFF−MIN Time
Characteristic Curve
DD−OFF
I
I
DD−PWM−OFF DD−ST
Valley Detection (DET Pin)
When FAN6921BMR operates in green mode, t
OFF−MIN
time is determined by the green mode circuit according to
FB pin voltage level. After t time, the internal valley
Figure 36. Typical Waveforms of VDD Voltage and
Gate Signal at Hiccup Mode Operation
OFF−MIN
detection circuit is activated. During the t
time of PWM
OFF
switch, when transformer inductor current discharges to
zero, the transformer inductor and parasitic capacitor of
PWM switch start to resonate concurrently. When the drain
voltage on the PWM switch falls, the voltage across on
Green−Mode Operation and PFC−ON / OFF Control
(FB Pin)
Green mode mechanism is used to further reduce power
loss in the system (e.g. switching loss). It uses an off−time
modulation technique to regulate switching frequency
according to FB pin voltage. When output loading is
decreased, FB voltage becomes lower due to secondary
auxiliary winding V
also decreases since auxiliary
AUX
winding is coupled to primary winding. Once the V
AUX
voltage resonates and falls to negative, V
voltage is
DET
clamped by the DET pin (refer to Figure 38)
and FAN6921BMR is forced to flow out a current I
feedback movement and the t
is extended. After
.
OFF−MIN
DET
t
(determined by FB voltage), the internal valley
FAN6921BMR reflects and compares this I
current. If
OFF−MIN
DET
detection circuit is activated to detect the valley on the drain
voltage of the PWM switch. When the valley signal is
this source current rises to a threshold current, PWM gate
signal is sent out after a fixed delay time (200 ns typical).
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17
FAN6921BMR
As the input voltage increases, the reflected voltage on
the auxiliary winding V becomes higher as well as
Auxiliary
Winding
AUX
the current I
and the controller regulates the V
DET
LIMIT
+
to a lower level.
The R resistor is connected from auxiliary winding
DET
R
R
DET
DET
V
10
AUX
+
0.3 V
to the DET pin. Engineers can adjust this R
resistor to
DET
V
DET
A
I
DET
get proper V
The characteristic curve of I
on CSPWM pin is shown in Figure 41.
voltage to fit power system needs.
LIMIT
−
current vs. V
voltage
DET
LIMIT
FAN6921B
−
I
DET + [VIN (NAńNP)]ńRDET
(eq. 1)
Figure 38. Valley Detection
where V is input voltage; N is turn number of auxiliary
IN
A
winding; and N is turn number of primary winding.
P
Figure 39. Measured Waveform of Valley Detection
Figure 40. Relationship between VAUX and VIN
High / Low Line Over−Power Compensation (DET Pin)
Generally, when the power switch turns off, there is
a delay time from gate signal falling edge to power switch
off. This delay is produced by an internal propagation delay
of the controller and the turn−off delay time of PWM switch
due to gate resistor and gate−source capacitor CISS of PWM
switch. At different AC input voltage, this delay time
produces different maximum output power under the same
PWM current limit level. Higher input voltage generates
higher maximum output power since applied voltage on
primary winding is higher and causes higher rising slope
inductor current. It results in higher peak inductor current at
the same delay time. Furthermore, under the same output
wattage, the peak switching current at high line is lower than
that at low line. Therefore, to make the maximum output
power close at different input voltages, the controller needs
900
800
700
600
500
400
300
0
100
200
I
300
(mA)
400
500
600
to regulate V
voltage of the CSPWM pin to control
DET
LIMIT
the PWM switch current.
Referring to Figure 40, during t
switch, the input voltage is applied to primary winding
and the voltage across on auxiliary winding V is
Figure 41. IDET Current vs. VLIMIT Voltage
Characteristic Curve
time of the PWM
ON
AUX
Leading−Edge Blanking (LEB)
proportional to primary winding voltage. So as the input
voltage increases, the reflected voltage on auxiliary winding
When the PFC or PWM switches are turned on, a voltage
spike is induced on the current sense resistor due to
the reciprocal effect by reverse recovery energy of
the output diode and COSS of power MOSFET. To prevent
this spike, a leading−edge blanking time is builtin to
FAN6921BMR and a small RC filter is also recommended
between the CSPWM pin and GND (e.g. 100 W, 470 pF).
V
AUX
becomes higher as well. FAN6921BMR also clamps
the DET pin voltage and flows out a current I . Since the
DET
current I
is in accordance with V
voltage,
DET
AUX
FAN6921BMR can depend on this current I
during t
DET
ON
time period to regulate the current limit level of PWM switch
to perform high / low line over−power compensation.
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18
FAN6921BMR
Output Over−Voltage Protection (DET Pin)
PROTECTION FOR PWM STAGE
Referring to Figure 43, during the discharge time of PWM
transformer inductor; the voltage across on auxiliary
winding is reflected from secondary winding and therefore
the flat voltage on the DET pin is proportional to the output
voltage. FAN6921BMR can sample this flat voltage level
VDD Pin Over−Voltage Protection (OVP)
V
DD
over−voltage protection is used to prevent device
damage once V voltage is higher than device stress rating
DD
voltage. In case of V
OVP, the controller stops all
DD
switching operation immediately and enters latch−off mode
until the AC plug is removed.
after a t
blanking time to perform output over−voltage
OFF
protection. This t
blanking time is used to ignore
OFF
the voltage ringing from leakage inductance of PWM
transformer. The sampling flat voltage level is compared
Adjustable Over−Temperature Protection and
Externally Latch Triggering (RT Pin)
Figure 42 is a typical application circuit with an internal
with internal threshold voltage 2.5
V and, once
the protection is activated, FAN6921BMR enters latch
mode.
The controller can protect rapidly by this kind of
cycle−by− cycle sampling method in the case of output over
voltage. The protection voltage level can be determined by
block of RT pin. As shown, a constant current I flows out
RT
from the RT pin, so the voltage V on RT pin can be
RT
obtained as I current multiplied by the resistor, which
RT
consists of NTC resistor and R resistor. If the RT pin
A
voltage is lower than 0.8 V and lasts for a de−bounce time,
latch mode is activated and stops all PFC and PWM
switching.
RT pin is usually used to achieve over−temperature
protection with a NTC resistor and provides external latch
triggering for additional protection. Engineers can use
an external triggering circuit (e.g. transistor) to pull low
the RT pin and activate controller latch mode.
Generally, the external latch triggering needs to activate
rapidly since it is usually used to protect power system from
abnormal conditions. Therefore, the protection debounce
time of the RT pin is set to around 110 ms once RT pin
voltage is lower than 0.5 V.
the ratio of external resistor divider R and R . The flat
A
DET
voltage on DET pin can be expressed by the following
equation:
RA
DET ) RA
V
DET + (NAńNS) VO
(eq. 2)
R
PWM
Gate
For over−temperature protection, because the
temperature would not change immediately; the RT pin
voltage is reduced slowly as well. The debounce time for
adjustable OTP should not need a fast reaction. To prevent
improper latch triggering on the RT pin due to exacting test
condition (e.g. lightning test), when the RT pin triggering
voltage is higher than 0.5 V, the protection debounce time is
set to around 10 ms. To avoid improper triggering on the RT
pin, it is recommended to add a small value capacitor (e.g.
t
NA
VO
@
V
AUX
NS
t
NA
NP
1000 pF) paralleled with NTC and R resistor.
A
PFC_VO
@
NA
RA
FAN6921B
VO
@
@
Sampling
here
Adjustable Over−
NS RDET ) RA
Temperature Protection &
External Latch Triggering
V
DET
I
RT
= 100 mA
t
off
12
RT
Blanking
Debounce
Time
0.8 V
0.5 V
Latched
NTC
R
110 ms
10 ms
RT
0.3 V
t
Figure 42. Adjustable Over−Temperature Protection
Figure 43. Operation Waveform of Output
Over−Voltage Detection
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19
FAN6921BMR
Open−Loop, Short−Circuit, and Overload Protection
(FB Pin)
on primary side is reduced. So the FB pin voltage is
increased by internal voltage bias. In the case of an open
loop, output short circuit, or overload conditions, this sink
current is further reduced and the FB pin voltage is pulled to
high level by internal bias voltage. When the FB pin voltage
is higher than 4.2 V for 50 ms, the FB pin protection is
activated.
V
O
FB
Under−Voltage Lockout (UVLO, VDD Pin)
Referring to Figure 35 and Figure 36, the turn−on
and turn−off V threshold voltages of FAN6921BMR are
fixed at 18 V and 10 V, respectively. During startup,
DD
Open−Loop
Short−Circuit/Overload
the holdup capacitor (V cap.) is charged by HV startup
DD
Figure 44. FB Pin Open−Loop, Short Circuit, and
current until V
voltage reaches the turn−on voltage.
DD
Overload Protection
Before the output voltage rises to rated voltage and delivers
energy to the V capacitor from auxiliary winding, this
DD
Referring to Figure 44, outside of FAN6921BMR, the FB
pin is connected to the collector of transistor of an
optocoupler. Inside of FAN6921BMR, the FB pin is
connected to an internal voltage bias through a resistor
around 5 kW.
hold−up capacitor has to sustain the V voltage energy for
DD
operation. When V
voltage reaches turn−on voltage,
DD
FAN6921BMR starts all switching operation if no
protection is triggered before V voltage drops to turnoff
DD
voltage V
.
DD−PWM−OFF
As the output loading is increased, the output voltage is
decreased and the sink current of transistor of optocoupler
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20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16, 150 mils
CASE 751BG−01
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
D
E
E1
e
9.80
5.80
3.80
9.90
6.00
10.00
6.20
4.00
E1
E
3.90
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
θ
PIN#1 IDENTIFICATION
TOP VIEW
D
h
q
A
c
e
b
L
A1
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34275E
SOIC−16, 150 MILS
PAGE 1 OF 1
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相关型号：
FAN6921MRMY
Switching Controller, Current-mode, 60kHz Switching Freq-Max, PDSO16, GREEN, MS-012AC, SOIC-16
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