FAN7388MX [ONSEMI]
625V，可兼容 3.3/5V 输入逻辑，0.65/0.35A 汲/源电流，3 相半桥门极驱动集成电路;
| 型号： | FAN7388MX |
| 厂家： | 
ONSEMI |
| 描述： | 625V，可兼容 3.3/5V 输入逻辑，0.65/0.35A 汲/源电流，3 相半桥门极驱动集成电路 PC 驱动 光电二极管 接口集成电路 |
| 文件： | 总15页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 2016
FAN7388
3 Half-Bridge Gate-Drive IC
Features
Description
Floating Channel for Bootstrap Operation to +600 V
The FAN7388 is a monolithic three half-bridge gate-drive
IC designed for high-voltage, high-speed driving MOS-
FETs and IGBTs operating up to +600 V.
Typically 350 mA / 650 mA Sourcing/Sinking Current
Driving Capability for All Channels
3 Half-Bridge Gate Driver
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side drivers under high-dv/dt noise circumstances.
Extended Allowable Negative VS Swing to -9.8 V for
Signal Propagation at VBS=15 V
Matched Propagation Delay Time Maximum: 50 ns
3.3 V and 5 V Input Logic Compatible
An advanced level-shift circuit allows high-side gate
driver operation up to VS=-9.8 V (typical) for VBS=15 V.
Built-in Shoot-Through Prevention Circuit for All
The UVLO circuits prevent malfunction when VDD and
VBS are lower than the specified threshold voltage.
Channels with 270 ns Typical Dead Time
Built-in Common Mode dv/dt Noise Canceling Circuit
Built-in UVLO Functions for All Channels
Output drivers typically source/sink 350 mA / 650 mA,
respectively, which is suitable for three-phase half-bridge
applications in motor drive systems.
Applications
3-Phase Motor Inverter Driver
Related Resources
AN-6076 - Design and Application Guide of Bootstrap
20-SOIC
Circuit for High-Voltage Gate-Drive IC
AN-9052 - Design Guide for Selection of Bootstrap
Components
AN-8102 - Recommendations to Avoid Short Pulse
Width Issues in HVIC Gate Driver Applications
Ordering Information
Operating
Part Number
Package
Temperature Range
Packing Method
FAN7388MX
20-SOIC
-40°C to +125°C
Tape & Reel
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev. 1.3
www.fairchildsemi.com
Typical Application Circuit
+15V
Up to 600V
1
2
VB1 20
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
LO3
VS3
19
18
HO1
VS1
VS1
3
4
5
6
3-Phase
BLDC Motor
Q1
Q3
Q5
Controller
LO1 17
VB2 16
Q1
Q3
IU
VS1
Q5
15
HO2
VS2
3-Phase Inverter
IV
7
8
9
14
13
VS2
Q4
Q6
Q2
VS2
LO2
VDD
IW
VS3
12
11
HO3
Q4
Q6
Q2
10 VB3
GND
VS3
FAN7388 Rev.00
Figure 1. 3-Phase BLDC Motor Drive Application
Internal Block Diagram
VB1
UVLO
HO1
VS1
R
R
S
UHIN
NOISE
CANCELLER
Q
HIN1
HIN2
VDD
VDD_UVLO
UVLO
SCHMITT
TRIGGER INPUT
ULIN
VDD
LO1
DELAY
HIN3
LIN1
LIN2
LIN3
GND
U Phase Driver
SHOOT-THOUGH
PREVENTION
VB2
HO2
VS2
VDD
VHIN
VLIN
V Phase Driver
W Phase Driver
LO2
CONTROL LOGIC
VB3
HO3
VS3
VDD
WHIN
WLIN
LO3
FAN7388 Rev.01
Figure 2. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
2
Pin Configuration
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
LO3
VS3
1
2
20 VB1
19
HO1
3
18 VS1
4
17 LO1
VB2
5
16
15
14
13
12
11
HO2
VS2
6
7
LO2
VDD
8
HO3
VB3
9
GND
10
FAN7388 Rev.00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
1
Name
Description
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
LO3
VS3
Logic input 1 for high-side gate 1 driver
Logic input 1 for low-side gate 1 driver
Logic input 2 for high-side gate 2 driver
Logic input 2 for low-side gate 2 driver
Logic input 3 for high-side gate 3 driver
Logic input 3 for low-side gate 3 driver
Low-side gate driver 3 output
2
3
4
5
6
7
8
High-side driver 3 floating supply offset voltage
High-side driver 3 gate driver output
High-side driver 3 floating supply voltage
Ground
9
HO3
VB3
10
11
12
13
14
15
16
17
18
19
20
GND
VDD
LO2
VS2
Logic and all low-side gate drivers power supply voltage
Low-side gate driver 2 output
High-side driver 2 floating supply offset voltage
High-side driver 2 gate driver output
High-side driver 2 floating supply voltage
Low-side gate driver 1 output
HO2
VB2
LO1
VS1
High-side driver 1 floating supply offset voltage
High-side driver 1 gate driver output
High-side driver 1 floating supply voltage
HO1
VB1
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
VB
Parameter
High-Side Floating Supply Voltage of VB1,2,3
High-Side Floating Supply Offset Voltage of VS1,2,3
High-Side Floating Output Voltage
Low-Side and Logic-fixed Supply Voltage
Low-Side Output Voltage
Min.
-0.3
Max.
625.0
Unit
V
VS
VB1,2,3-25
VS1,2,3-0.3
-0.3
VB1,2,3+0.3
VB1,2,3+0.3
25.0
V
VHO1,2,3
VDD
VLO1,2,3
VIN
V
V
-0.3
VDD+0.3
VDD+0.3
50
V
Logic Input Voltage (HIN1,2,3 and LIN1,2,3)
Allowable Offset Voltage Slew Rate
Power Dissipation(1)(2)(3)
-0.3
V
dVS/dt
PD
V/ns
W
1.47
JA
Thermal Resistance, Junction-to-ambient
Junction Temperature
85
C/W
C
C
TJ
+150
TSTG
Storage Temperature
-55
+150
Notes:
1. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material).
2. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.
3. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VB1,2,3
VS1,2,3
VDD
Parameter
High-Side Floating Supply Voltage
High-Side Floating Supply Offset Voltage
Supply Voltage
Min.
VS1,2,3+10
6-VDD
10
Max.
VS1,2,3+20
600
Unit
V
V
20
V
VHO1,2,3
VLO1,2,3
VIN
High-Side Output Voltage
VS1,2,3
GND
VB1,2,3
VDD
V
Low-Side Output Voltage
V
Logic Input Voltage (HIN1,2,3 and LIN1,2,3)
Ambient Temperature
GND
VDD
V
TA
-40
+125
°C
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
4
Electrical Characteristics
VBIAS (VDD, VBS1,2,3)=15.0 V, TA=25C, unless otherwise specified. The VIN and IIN parameters are referenced to
GND. The VO and IO parameters are referenced to GND and VS1,2,3 and are applicable to the respective outputs
LO1,2,3 and HO1,2,3.
Symbol
Characteristics
Condition
Min. Typ. Max. Unit
LOW-SIDE POWER SUPPLY SECTION
IQDD
Quiescent VDD Supply Current
VLIN1,2,3=0 V or 5 V
160 350
500 900
µA
µA
Operating VDD Supply Current for each
Channel
IPDD1,2,3
fLIN1,2,3=20 kHz, rms Value
VDD Supply Under-Voltage Positive-Going
Threshold
VDDUV+
VDDUV-
VDDHYS
VDD=Sweep, VBS=15 V
VDD=Sweep, VBS=15 V
VDD=Sweep, VBS=15 V
7.2
6.8
8.2
7.8
0.4
9.0
8.5
V
V
V
VDD Supply Under-Voltage Negative-Going
Threshold
VDD Supply Under-Voltage Lockout
Hysteresis
BOOTSTRAPPED POWER SUPPLY SECTION
Quiescent VBS Supply Current for each
IQBS1,2,3
Channel
VHIN1,2,3=0 V or 5 V
50
120
µA
µA
V
Operating VBS Supply Current for each
IPBS1,2,3
Channel
fHIN1,2,3=20 kHz, rms Value
VDD=15 V, VBS=Sweep
VDD=15 V, VBS=Sweep
400 800
VBS Supply Under-Voltage Positive-going
Threshold
VBSUV+
7.2
6.8
8.2
7.8
0.4
9.0
8.5
VBS Supply Under-Voltage Negative-going
Threshold
VBSUV-
V
VBS Supply Under-Voltage Lockout
Hysteresis
VBSHYS
VDD=15 V, VBS=Sweep
VB1,2,3=VS1,2,3=600 V
V
ILK
Offset Supply Leakage Current
10
µA
GATE DRIVER OUTPUT SECTION
VOH
VOL
High-Level Output Voltage, VBIAS-VO
IO=20 mA
IO=20 mA
1.0
0.6
V
V
Low-Level Output Voltage, VO
Output HIGH Short-Circuit Pulsed
Current(4)
VO=0 V, VIN=5 V with PW
<10 µs
IO+
IO-
VS
250 350
500 650
mA
mA
VO=15 V, VIN=0 V with PW
<10 µs
Output LOW Short-Circuit Pulsed Current(4)
Allowable Negative VS Pin Voltage for IN
Signal Propagation to HO
-9.8 -7.0
V
LOGIC INPUT SECTION (HIN, LIN)
VIH
VIL
IIN+
IIN-
RIN
Logic "1" Input Voltage
2.5
V
V
Logic "0" Input Voltage
1.0
Logic "1" Input Bias Current
Logic "0" Input Bias Current(4)
Input Pull-Down Resistance
VIN=5 V
VIN=0 V
25
50
µA
µA
K
2.0
100 200 300
Note:
4. This parameter is guaranteed by design.
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
5
Dynamic Electrical Characteristics
TA=25C, VBIAS (VDD, VBS1,2,3)=15.0 V, VS1,2,3=GND, CLoad=1000 pF unless otherwise specified.
Symbol
tON
Parameter
Turn-on Propagation Delay
Turn-off Propagation Delay
Turn-on Rise Time
Conditions
VS1,2,3=0 V
VS1,2,3=0 V
Min. Typ. Max. Unit
130
150
50
220
240
120
80
ns
ns
ns
ns
ns
ns
ns
ns
tOFF
tR
tF
Turn-off Fall Time
30
MT1
MT2
DT
Turn-on Delay Matching I tON(H) -tOFF(L)
Turn-off Delay Matching I tOFF(H) -tON(L)
Dead Time
I
I
50
50
100
270
440
60
MDT
Dead-time Matching I tDT1 -tDT2 I
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
6
Typical Characteristics
300
250
200
150
100
50
250
200
150
100
50
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 4. Turn-on Propagation Delay vs. Temp.
Figure 5. Turn-off Propagation Delay vs. Temp.
120
100
80
60
40
20
0
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 6. Turn-on Rise Time vs. Temp.
Figure 7. Turn-off Fall Time vs. Temp.
50
50
40
30
20
10
0
40
30
20
10
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 8. Turn-on Delay Matching vs. Temp.
Figure 9. Turn-off Delay Matching vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
7
Typical Characteristics (Continued)
500
400
300
200
100
60
50
40
30
20
10
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 10. Dead Time vs. Temp.
Figure 11. Dead-Time Matching vs. Temp.
350
120
100
80
60
40
20
0
300
250
200
150
100
50
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 12. Quiescent VDD Supply Current
vs. Temp.
Figure 13. Quiescent VBS Supply Current
vs. Temp.
1000
800
600
400
200
0
1000
800
600
400
200
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 14. Operating VDD Supply Current vs. Temp.
Figure 15. Operating VBS Supply Current vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev. 1.3
www.fairchildsemi.com
8
Typical Characteristics (Continued)
9.0
8.5
8.0
7.5
7.0
9.0
8.5
8.0
7.5
7.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 16. VDD UVLO+ vs. Temp.
Figure 17. VDD UVLO- vs. Temp.
9.0
9.0
8.5
8.0
7.5
7.0
8.5
8.0
7.5
7.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 18. VBS UVLO+ vs. Temp.
Figure 19. VBS UVLO- vs. Temp.
1.0
0.8
0.6
0.4
0.2
0.0
0.60
0.45
0.30
0.15
0.00
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 20. High-Level Output Voltage vs. Temp.
Figure 21. Low-Level Output Voltage vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev. 1.3
www.fairchildsemi.com
9
Typical Characteristics (Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 22. Logic High Input Voltage vs. Temp.
Figure 23. Logic Low Input Voltage vs. Temp.
50
40
30
20
10
0
-7
-8
-9
-10
-11
-12
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 24. Logic Input High Bias Current vs. Temp.
Figure 25. Allowable Negative VS Voltage vs. Temp.
500
400
300
200
100
0
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 26. Input Pull-down Resistance vs. Temp.
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev. 1.3
www.fairchildsemi.com
10
Application Information
1. Protection Function
2. Operational Notes
The FAN7388 is a three half-bridge gate driver with
internal, typical 270 ns dead-time for the three-phase
brushless DC (BLDC) motor drive system, as shown in
Figure 1.
1.1 Under-Voltage Lockout (UVLO)
The high- and low-side drivers include under-voltage
lockout (UVLO) protection circuitry for each channel that
monitors the supply voltage (VDD) and bootstrap capaci-
tor voltage (VBS1,2,3) independently. It can be designed
prevent malfunction when VDD and VBS1,2,3 are lower
than the specified threshold voltage. The UVLO hystere-
sis prevents chattering during power supply transitions.
Figure 29 shows a switching sequence of 120 electrical
commutation for a three-phase BLDC motor drive system.
The waveforms are idealized: they assumed that the
generated back EMF waveforms are trapezoidal with flat
tops of sufficient width to produce constant torque when
the line currents are perfectly rectangular, 120 electrical
1.2 Shoot-Through Prevention Function
degrees, with the switching sequence as shown in Figure
29. The operating waveforms of the wye-connection
reveal that repeat every 60 electrical degrees, with each
The FAN7388 has shoot-through prevention circuitry
monitoring the high- and low-side control inputs. It can
be designed to prevent outputs of high and low side from
turning on at same time, as shown Figure 27 and 28.
60 segment being “commutated” to another phase, as
shown in Figure 29.
HIN1,2,3/LIN1,2,3
LIN1,2,3/HIN1,2,3
Shoot-Through Prevent
HO1,2,3/LO1,2,3
After DT
LO1,2,3/HO1,2,3
After DT
FAN7388 Rev.00
Figure 27. Waveforms for Shoot-Through Prevention
HIN1,2,3/LIN1,2,3
LIN1,2,3/HIN1,2,3
Shoot-Through Prevent
HO1,2,3/LO1,2,3
After DT
LO1,2,3/HO1,2,3
FAN7388 Rev.00
Figure 28. Waveforms for Shoot-Through Prevention
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
11
Application Information (Continued)
Elec o
-30
0
30
60
90
120
150
180
210
240
270
300
330
Input / Output
HIN / HO1,2,3
Q5 (HIN3)
Q1 (HIN1)
Q3 (HIN2)
Q5 (HIN3)
Q6 (LIN2)
Q2 (LIN3)
Q4 (LIN1)
LIN / LO1,2,3
Phase Current
IU
IV
IW
Phase Voltage
VS1
Phase Back EMF
VS2
VS3
Current Flow
Direction
U
V
W
U
V
W
U
V
W
U
V
W
U
V
W
U
V
W
Figure 29. 120 Commutation Operation Waveforms for 3-Phase BLDC Motor Application
Switching Time Diagram
50%
HIN1,2,3
/LIN1,2,3
50%
tON(H)
tOFF(H)
90%
tR
tF
90%
HO1,2,3
10%
MT1
10%
MT2
90%
90%
tOFF(L)
tON(L)
LO1,2,3
10%
10%
Figure 30. Switching Time Definition
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev. 1.3
www.fairchildsemi.com
12
ꢃꢂꢁꢄꢀꢀꢁꢂꢀ
A
11.930
11.430
11.430
20
11
B
ꢅꢁꢆꢀꢀꢁꢃꢀ
10.922
8.422
10.325
1
10
PIN ONE
INDICATOR
1.27
C B A
0.50 TYP
0.51
0.35
1.25 TYP
1.27 TYP
M
0.25
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
ꢀꢁꢂꢀꢀꢁꢃꢀ
SEATING PLANE
PIN#1 IDENTIFICATION OPTIONS
20
0.75
0.25
;ꢇꢈꢆ
20
20
(R0.10)
GAGE PLANE
(R0.10)
0.25
ꢄ
ꢀ
SEATING PLANE
0.40~1.27
(1.40)
PIN #1
INDICATOR
DETAIL A
SCALE: 2:1
PIN #1
INDICATOR
PIN #1
INDICATOR
NOTES: UNLESS OTHERWISE SPECIFIED
1
1
1
A) THIS PACKAGE CONFORMS TO JEDEC MS-013.
OPTION 2
OPTION 1
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
OPTION 3
HALF MOON & PIN 1
HALF MOON ONLY
PIN 1 ONLY
D) LANDPATTERN RECOMMENDATION IS FSC DESIGN
E) FILENAME AND REVISION: M20Brev4
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