FAN73901MX [ONSEMI]
625V，可兼容 3.3/5V 输入逻辑，2.5/2.5A 汲/源电流，半桥门极驱动;
| 型号： | FAN73901MX |
| 厂家： | 
ONSEMI |
| 描述： | 625V，可兼容 3.3/5V 输入逻辑，2.5/2.5A 汲/源电流，半桥门极驱动 驱动 光电二极管 接口集成电路 |
| 文件： | 总14页 (文件大小：710K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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2013 年 11 月
FAN73901
高侧和低侧栅极驱动 IC
特性
说明
浮动通道可实现高达 +600V 的自举运行
2.5A/2.5A 的典型源电流 / 灌电流
FAN73901 是单片高侧和低侧栅极驱动 IC，可以驱动工作
电压最高达 +600V 的高速 MOSFET IGBT。它具有缓
冲输出级，且所有 NMOS 晶体管设计为具有高脉冲电流
和
驱动能力
驱动能力和最低交叠导通。
共模 dv/dt 噪声消除电路
两个通道均内置欠压闭锁功能
适用于两个通道的匹配传播延迟
兼容 3.3V 和 5V 逻辑输入电平
输出与输入同相
飞兆的高压工艺和共模噪声消除技术 s 可使高侧驱动器在
高 dv/dt 噪声环境下稳定运行。先进的电平转换电路，能
使高侧栅极驱动器的工作电压在 VBS=15V 时 VS 达到
-9.8V （典型值）。
UVLO （欠压保护）电路在 VDD 和 VBS 低于额定阙值电
压时启动保护防止故障发生。
应用
半桥驱动器
HID 灯镇流器
SMPS
大电流和低输出压降的特性，使得 FAN73901 适合开关
电源、电机驱动器和大功率 DC-DC 转换器应用。
电动机驱动
8-SOP
订购信息
器件编号
FAN73901M
FAN73901MX
封装
工作温度范围
包装方法
塑料管
8-SOP
-40°C ~ 125°C
卷带和卷盘
© 2008 飞兆半导体公司
FAN73901 • Rev. 1.0.1
www.fairchildsemi.com
典型应用电路
15V
RBOOT
FAN73901
Up to 600V
DBOOT
1
2
3
4
HIN
8
7
6
5
HIN
LIN
VB
HO
VS
Controller
Q1
R1
LIN
COM
LO
CBOOT
R2
OUTPUT
VDD
Load
C1
R3
Q2
R4
FAN73901 Rev.01
图 1. 半桥应用电路
内部框图
8
7
VB
FAN73901
UVLO
R
HO
R
1
NOISE
HIN
CANCELLER
S
Q
200K
6
5
VS
VDD
UVLO
DELAY
4
LO
2
LIN
200K
3
COM
FAN73901 Rev.01
图 2. 功能框图
© 2008 飞兆半导体公司
FAN73901 • Rev. 1.0.1
www.fairchildsemi.com
2
引脚布局
HIN
LIN
1
2
3
4
8
7
6
5
VB
HO
VS
FAN73901
COM
LO
VDD
FAN73901 Rev.01
图 3. 引脚分配 （顶视图 / 俯视图）
引脚定义
引脚号
名称
HIN
LIN
COM
LO
说明
1
2
3
4
5
6
7
8
高侧栅极驱动器输出的逻辑输入
低侧栅极驱动器输出的逻辑输入
低侧驱动返回
低侧驱动输出
VDD
VS
低侧和逻辑电路的电源电压
高侧浮动电源电压返回
高侧驱动输出
HO
VB
高侧浮动电源
© 2008 飞兆半导体公司
FAN73901 • Rev. 1.0.1
www.fairchildsemi.com
3
绝对最大额定值
应力超过绝对最大额定值，可能会损坏器件。在超出推荐的工作条件的情况下，该器件可能无法正常工作，所以不建议
让器件在这些条件下长期工作。此外，长期在超出推荐的工作条件下工作，会影响器件的可靠性。绝对最大额定值仅是
应力规格值。除非另有说明， TA=25°C。
符号
VS
特性
最小值
VB-25
-0.3
最大值
VB+0.3
625.0
VB+0.3
25.0
单位
V
高侧浮动电源偏置电压
高侧浮动电源电压
VB
V
VHO
VDD
VLO
VIN
VS-0.3
-0.3
V
高侧浮动输出电压 HO
V
低侧和固定逻辑电源电压
低侧输出电压 LO
逻辑输入电压 (HIN, LIN)
允许的偏置电压变化速率
功耗 (1)(2)(3)
-0.3
VDD+0.3
VDD+0.3
50
V
-0.3
V
dVS/dt
PD
V/ns
W
0.625
200
JA
C/W
C
C
结至环境热阻
TJ
+150
结温
TSTG
+150
存储温度
注意：
1. 安装在 76.2 x 114.3 x 1.6 mm PCB 板 （FR-4 环氧玻璃材料）。
2. 参考以下标准：
JESD51-2: 集成电路热测试方法环境条件 - 自然对流。
JESD51-3: 含铅表面贴装封装的低有效导热系数测试板。
3. 在任何情况下，都不要超过 PD。
推荐工作条件
推荐的操作条件表明确了器件的真实工作条件。指定推荐的工作条件，以确保器件的最佳性能达到数据表中的规格。
飞兆不建议超出额定或依照绝对最大额定值进行设计。
符号
VB
参数
最小值
VS+10
6-VDD
VS
最大值
VS+20
600
单位
V
高侧浮动电源电压
高侧浮动电源偏置电压
高侧输出电压
VS
V
VHO
VDD
VLO
VIN
TA
VB
V
10
20
V
低侧和逻辑电源电压
低侧输出电压
COM
COM
-40
VDD
V
VDD
V
逻辑输入电压 （HIN 和 LIN）
+125
C
工作环境温度
© 2008 飞兆半导体公司
FAN73901 • Rev. 1.0.1
www.fairchildsemi.com
4
电气特性
除非另有规定，否则 VBIAS (VDD，VBS)=15.0 V，VS=COM，TA=25°C。VIL、VIH 和 IIN 参数指的是以 COM 为参考点的
值，同时适用于输入信号 HIN 和 LIN。VO 和 IO 参数指的是以 COM 为参考点的值，VS 同时适用于输出信号 HO 和 LO。
符号
特性
测试条件
最小值 典型值 最大值 单位
电源部分 （VDD 和 VBS
）
VDDUV+
VBSUV+
VDDUV-
VBSUV-
VDDUVH
VDD 和 VBS 电源欠压正向 （电压从高到
低）阈值
8.0
7.4
8.8
8.3
0.5
9.8
9.0
V
V
V
VDD 和 VBS 电源欠压负向 （电压从低到
高）阈值
VDD 和 VBS 电源欠压闭锁滞回电压回差
VBSUVH
ILK
VB=VS=600 V
50
80
µA
µA
µA
µA
µA
偏置漏电流
IQBS
IQDD
IPBS
IPDD
45
75
静态 VBS 电源电流
静态 VDD 电源电流
工作 VBS 电源电流
工作 VDD 电源电流
VIN=0V 或 5 V
110
640
640
VIN=0V 或 5 V
530
530
fIN=20 kHz， rms 值
fIN=20 kHz， rms 值
逻辑输入部分 (HIN, LIN)
VIH
VIL
IIN+
IIN-
RIN
2.5
V
V
逻辑 "1" 输入电压
逻辑 "0" 输入电压
逻辑 "1" 输入偏置电流
逻辑 "0" 输入偏置电流
输入下拉电阻
1.2
50
VIN=5 V
VIN=0 V
25
1.0
200
µA
µA
K
2.0
100
栅极驱动器输出部分 （HO, LO）
VOH
VOL
IO+
1.0
35
V
mV
A
高电平输出电压， VBIAS-VO
无负载
无负载
低电平输出电压， VO
输出高电平、短路脉冲电流 (4)
输出低电平、短路脉冲电流 (4)
V =0 V
，
V =5 V
及
PW<10 µs
， V =0 V 及 PW<10 µs
IN
1.8
1.8
2.5
2.5
O
IN
IO-
A
V =15 V
O
IN 信号传播到 HO 时允许的 VS 引脚负
电压
VS
-9.8
-7.0
V
注：
4. 参数由设计者提供。
动态电气特性
除非另有规定，否则 VBIAS (VDD， VBS)=15.0 V， VS=COM=0 V， CL=1000 pF 和 TA=25°C。
符号
ton
toff
MT
tr
特性
测试条件
最小值 典型值 最大值 单位
VS=0 V
VS=0 V
140
140
0
200
200
50
ns
ns
ns
ns
ns
导通传播延时
关断传播延时
延时匹配， HS 与 LS 导通 / 关断
导通上升时间
25
20
50
tf
45
关断下降时间
© 2008 飞兆半导体公司
FAN73901 • Rev. 1.0.1
www.fairchildsemi.com
5
典型特性
240
220
200
180
160
140
120
100
80
240
220
200
180
160
140
120
100
80
60
-40
60
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 4. 导通传播延迟
图 5. 关断传播延迟
与温度的关系
与温度的关系
40
30
20
10
0
40
30
20
10
0
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 6. 导通上升时间与温度的关系
图 7. 导通下降时间与温度的关系
50
40
30
20
10
50
40
30
20
10
0
0
-40
-10
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 8. 导通延时匹配与 温度的关系
图 9. 关断延时匹配与温度的关系
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73901 • Rev. 1.0.1
6
典型特性 （续）
140
120
100
80
120
100
80
60
40
20
0
60
40
20
0
-40
-20
0
20
40
60
80
100
120
-40
-20
-20
-20
0
20
40
60
80
100
100
100
120
120
120
Temperature [°C]
Temperature [°C]
图 10. 静态 VDD 电源电流
图 11. 静态 VBS 电源电流
与温度的关系
与温度的关系
1000
800
600
400
200
1000
800
600
400
200
-40
-20
0
20
40
60
80
100
120
-40
0
20
40
60
80
Temperature [°C]
Temperature [°C]
图 12. 工作 VDD 电源电流
图 13. 工作 VBS 电源电流
与温度的关系
与温度的关系
9.0
8.5
8.0
7.5
7.0
9.5
9.0
8.5
8.0
7.5
-40
0
20
40
60
80
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 14.VDD UVLO+ 与温度的关系
图 15.VDD UVLO- 与温度的关系
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73901 • Rev. 1.0.1
7
典型特性 （续）
9.5
9.0
8.5
8.0
7.5
9.0
8.5
8.0
7.5
7.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 16.VBS UVLO+ 与温度的关系
图 17.VBS UVLO- 与温度的关系
1500
1200
900
600
300
0
20
10
0
-10
-20
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 18. 高电平输出电压
图 19. 低电平输出电压
与温度的关系
与温度的关系
3.0
2.5
2.0
1.5
1.0
0.5
3.0
2.5
2.0
1.5
1.0
0.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 20. 逻辑高输入电压与 温度的关系
图 21. 逻辑低输入电压与 温度的关系
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73901 • Rev. 1.0.1
8
典型特性 （续）
-7
-8
60
50
40
30
20
10
0
-9
-10
-11
-12
-10
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 22. 逻辑输入高偏置电流
图 23. 容许负 VS 电压
与温度的关系
与温度的关系
.
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73901 • Rev. 1.0.1
9
开关时间定义
15V
VB
HO
VS
8
7
6
5
HIN
LIN
1
2
3
4
HIN
LIN
COM
LO
10µF 100nF
1nF
15V
VDD
1nF
10µF 100nF
FAN73901 Rev.01
图 24. 开关时间测试电路
HIN
LIN
HO
LO
FAN73901 Rev.01
图 25. 输入 / 输出时序图
HIN
50%
50%
LIN
ton tr
toff tf
90%
90%
HO
LO
10%
10%
FAN73901 Rev.01
图 26. 开关时间波形定义
50%
50%
HIN
LIN
MT
LO
HO
10%
10%
90%
90%
LO
HO
MT
FAN73901 Rev.01
图 27. 开关匹配波形定义
© 2008 飞兆半导体公司
FAN73901 • Rev. 1.0.1
www.fairchildsemi.com
10
机械尺寸
.
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.40
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08Arev14
F) FAIRCHILD SEMICONDUCTOR.
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
图 28. 8- 引脚小尺寸封装 (SOP)
封装图纸是作为一项服务而提供给考虑选用飞兆半导体产品的客户。具体参数可能会有变化，且不会做出相应通知。请注意图纸上的版
本和 / 或日期，并联系飞兆半导体代表核实或获得最新版本。封装规格并不超出飞兆公司全球范围内的条款与条件，尤其指保修，保修
涵盖飞兆半导体的全部产品。
随时访问飞兆半导体在线封装网页，可以获取最新的封装图纸：
http://www.fairchildsemi.com/dwg/M0/M08B.pdf.
© 2008 飞兆半导体公司
FAN73901 • Rev. 1.0.1
www.fairchildsemi.com
11
© 2008 飞兆半导体公司
www.fairchildsemi.com
FAN73901 • Rev. 1.0.1
12
ON Semiconductor and
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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
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