FAN73912AMX [ONSEMI]
1200V High-Current, High & Low-Side, Gate-Driver IC (HVIC);
| 型号： | FAN73912AMX |
| 厂家： | 
ONSEMI |
| 描述： | 1200V High-Current, High & Low-Side, Gate-Driver IC (HVIC) 栅 |
| 文件： | 总18页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High-Current, High & Low-Side,
Gate-Driver IC
FAN73912A
Description
The FAN73912A is a monolithic high and low−side gate−drive IC
designed for high−voltage and high−speed driving for MOSFETs
and IGBTs that operate up to +1200 V.
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The advanced input filter of HIN provides protection against
short−pulsed input signals caused by noise.
An advanced level−shift circuit offers high−side gate driver
operation up to VS = −9.8 V (typical) for VBS = 15 V. The UVLO
circuit prevents malfunction when VCC and VBS are lower than
the specified threshold voltage.
SOIC−16
CASE 751BH
Output drivers typically source and sink 2 A and 3 A, respectively.
Features
• Floating Channel for Bootstrap Operation to +1200 V
MARKING DIAGRAM
• Typically 2 A/ 3 A Sourcing/Sinking Current Driving Capability for
Both Channels
• Gate Driver Supply (VCC) Range from 12 V to 20 V
FAN73912A
• Separate Logic Supply (VDD) Range from 3 V to 20 V
• Extended Allowable Negative VS Swing to −9.8 V for Signal
Propagation at VCC = VBS = 15 V
ON LOT No.
• Built−in Cycle−by−Cycle Edge−Triggered Shutdown Logic
• Common−Mode dv/dt Noise Canceling Circuit
• UVLO Functions for Both Channels
• Built−in Advanced Input Filter
ORDERING INFORMATION
• Matched Propagation Delay Below 60 ns
• Outputs in−Phase with Input Signal
†
Device
FAN73912AMX
Package
Shipping
1,000/
Tape & Reel
Wide−16
• Logic and Power Ground 10 V Offset
(Note 1)
SOIC
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1. This device passed wave−soldering test by
JESD22A−111
Typical Application
• Electrical Contactor
• Industrial Motor Driver
• UPS
• Solar Inverter
• Ballast
• General−Purpose Half−Bridge Topology
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
February, 2021 − Rev. 1
FAN73912A/D
FAN73912A
Up to 1200 V
Q1
R1
Typically
3.3~15 V
9
8
7
6
5
4
3
2
1
NC
NC
HO
V
B
10
11
12
13
14
15
16
C
BOOT
V
S
V
DD
Load
HIN
SD
NC
NC
HIN
SD
D
R
BOOT
BOOT
Controller
V
LIN
LIN
15 V
R2
CC
COM
LO
C1
V
SS
Q2
NC
Figure 1. Application Schematic − Adjustable Option
V
7
8
B
UVLO
HS(ON/OFF)
HO
11
12
R
V
DD
R
S
NOISE
CANCELLER
Q
HIN
LIN
SD
6
3
V
S
CYCLE−By−
CYCLE EDGE
TRIGGERED
SHUTDOWN
SCHMITT
VSS/COM
LEVEL
SHIFT
UVLO
TRIGGER
INPUT
14
13
15
V
CC
DELAY
LO
1
2
LS(ON/OFF)
Pin 4,5,9,10 and 16 are no connection
V
SS
COM
Figure 2. Simplified Block Diagram
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2
FAN73912A
1
2
3
4
5
6
7
16
15
14
13
12
11
10
9
LO
NC
COM
V
SS
FAN73912A
LIN
SD
V
CC
NC
NC
HIN
V
V
S
V
DD
NC
NC
B
HO
8
Figure 3. Pin Connections − Wide 16−SOIC
(Top View)
Table 1. PIN FUNCTION DESCRIPTION (Note 2)
Pin No.
Symbol
LO
Description
1
2
Low−Side Driver Output
Low−Side Driver Return
Low−Side Supply Voltage
No Connection
COM
VCC
NC
3
4
5
NC
No Connection
6
V
V
High−Voltage Floating Supply Return
High−Side Floating Supply
High−Side Driver Output
No Connection
S
B
7
8
HO
NC
NC
9
10
11
12
13
14
15
16
No Connection
V
DD
Logic Supply Voltage
HIN
Logic Input for High−Side Gate Driver Output
Logic Input for Shutdown
SD
LIN
Logic Input for Low−Side Gate Driver Output
Logic Ground
V
SS
NC
No Connection
2. Do not connect NC pins to ground or any other nodes in the circuitry to ensure floating status.
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3
FAN73912A
Table 2. MAXIMUM RATINGS (T = 25°C, unless otherwise specified. All voltage parameters are referenced to COM unless
J
otherwise stated in the table.)
Symbol
Parameter
High−Side Floating Supply Voltage
High−Side Floating Offset Voltage
Min
Max
Unit
V
V
B
S
−0.3
1225.0
V
V
T = 150°C
V
V
V
− 25
− 25
− 23
V
V
V
+ 0.3
+ 0.3
+ 0.3
J
B
B
B
B
B
B
T = 25°C
J
T =−40°C
J
V
V
High−Side Floating Output Voltage
Low−Side Supply Voltage
V
− 0.3
V
+ 0.3
25
V
V
V
V
HO
S
B
−0.3
CC
V
LO
DD
Low−Side Floating Output Voltage
Logic Supply Voltage
−0.3
−0.3
V
CC
+ 0.3
V
25
+ 25
V
SS
− 0.3
V
SS
V
Logic GND
V
− 25
V
+ 0.3
V
V
SS
DD
DD
V
Logic Input Voltage (HIN, LIN and SD)
−0.3
DD
25
+ 0.3
IN
V
SS
+ V − 25.3
V
DD
dV /dt
Allowable Offset Voltage Slew Rate
Power Dissipation
−
−
50
V/ns
W
S
P
D
1.3
(Note 3, 4, 5)
q
Thermal Resistance
Junction Temperature
Storage Temperature
−
−
95
°C/W
°C
JA
T
150
150
J
T
STG
−55
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR−4 glass epoxy material).
4. Refer to the following standards:
JESD51−2: Integral circuit’s thermal test method environmental conditions, natural convection;
JESD51−3: Low effective thermal conductivity test board for leaded surface−mount packages.
5. Do not exceed maximum power dissipation (P ) under any circumstances.
D
Table 3. RECOMMENDED OPERATING CONDITIONS (All voltage parameters are referenced to COM unless otherwise stated in
the table.)
Symbol
Parameter
High−Side Floating Supply Voltage
Min
V + 12
Max
+ 20
Unit
V
V
B
V
S
V
S
S
High−Side Floating Supply Offset Voltage (Note 6)
High−Side (HO) Output Voltage
Low−Side Supply Voltage
8 − V
1200
V
CC
V
HO
V
CC
V
S
V
B
V
12
0
20
V
V
Low−Side (LO) Output Voltage
Logic Supply Voltage
V
CC
V
LO
DD
V
V
SS
+ 3
V
+ 20
V
SS
V
SS
Logic Ground (Note 7)
−10
10
V
V
IN
Logic Input Voltage (HIN, LIN, SD)
0
DD
20
V
DD
V
V
SS
+ V − 20
T
J
Junction Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Referenced to T = 25°C.
J
7. When V < 10 V, the minimum V offset is limited to −V .
DD
DD
SS
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FAN73912A
Table 4. STATIC ELECTRICAL CHARACTERISTICS (V
(V , V , V ) = 15.0 V, T = −40°C to 125°C, unless otherwise
CC BS DD J
BIAS
specified. The V , V and I parameters are referenced to V and are applicable to respective input leads: HIN, LIN and SD. The V
IH
IL
IN
SS
O
and I parameters are referenced to V and COM and are applicable to the respective output leads: HO and LO. The V
parameters
O
S
DDUV
are referenced to COM. The V
parameters are referenced to V
)
BSUV
S1, 2, 3
Symbol
Parameter
Conditions
Min
Typ
Max
Units
mA
LOW−SIDE POWER SUPPLY SECTION
I
I
Quiescent V Supply Current
V
V
= 0 V or V
= 0 V or V
T = 25°C
J
−
−
170
170
−
300
350
10
QCC
CC
IN
DD
T = −40°C to 125°C
J
Quiescent V Supply Current
T = 25°C
J
−
mA
QDD
DD
IN
DD
T = −40°C to 125°C
J
−
−
20
I
Operating V Supply Current
f
f
= 20 kHz, rms V = 15 V
−
650
2
950
−
mA
PCC
CC
IN
IN
PP
Operating V Supply Current
= 20 kHz, rms V = 15 V
−
IPDD
DD
IN
IN
PP
I
Shutdown Supply Current
S
V
= V
DD
−
30
50
mA
SD
D
V
V
V
Supply Under−Voltage
= Sweep
= Sweep
= Sweep
9.7
11.0
12
V
CCUV+
CCUV−
CCUVH
CC
CC
Positive−Going Threshold Voltage
V
Supply Under−Voltage
V
V
9.2
10.5
0.5
11.4
V
V
CC
CC
Negative−Going Threshold Voltage
V
V
CC
Supply Under−Voltage Lockout
−
−
CC
Hysteresis Voltage
BOOTSTRAPPED SUPPLY SECTION
Quiescent V Supply Current
I
V
= 0 V or V
DD
−
−
50
100
850
12.0
mA
mA
V
QBS
BS
IN
I
Operating V Supply Current
f = 20 kHz, rms value
IN
550
11.0
PBS
BS
V
V
V
Supply Under−Voltage
V
BS
V
BS
V
BS
= Sweep
= Sweep
= Sweep
9.7
BSUV+
BSUV−
BSUVH
BS
Positive−Going Threshold Voltage
V
BS
Supply Under−Voltage
9.2
10.5
0.5
11.4
V
V
Negative−Going Threshold Voltage
V
V
BS
Supply Under−Voltage Lockout
−
−
Hysteresis Voltage
I
LK
Offset Supply Leakage Current
V = V = 1200 V (T = 25°C)
−
−
−
−
−
−
100
100
100
mA
B
S
J
V = V = 1200 V (T = 125°C) (Note 8)
B
S
J
V = V = 1000 V (T = −40°C) (Note 8)
B
S
J
INPUT LOGIC SECTION (HIN.LIN AND AD)
V
Logic “1” Input Voltage
V
V
= 3 V
2.4
9.5
10.5
−
−
−
−
−
V
V
IH
DD
= 15 V
T = 25°C
J
DD
T = −40°C to 125°C
J
−
−
V
Logic “0” Input Voltage
V
V
= 3 V
−
0.8
6.0
9.5
50
1
IL
DD
= 15 V
T = 25°C
J
−
−
DD
T = −40°C to 125°C
J
−
−
I
I
Logic “1” Input bias Current
Logic “0” Input bias Current
Logic Input Pull−down Resistance
V
V
= 15 V
= 0 V
−
30
−
mA
mA
kW
IN+
IN
−
IN−
IN
R
−
500
−
IN
GATE DRIVER OUTPUT SECTION
High−Level Output Voltage,
V
OH
I
I
= 0 A
= 0 A
T = 25°C
−
−
−
−
−
−
1.2
1.4
0.1
V
O
J
V
−V
BIAS
O
T = −40°C to 125°C
J
V
OL
Low−Level Output Voltage, V
O
V
O
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. These parameters are guaranteed by design.
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FAN73912A
Table 4. STATIC ELECTRICAL CHARACTERISTICS (V
(V , V , V ) = 15.0 V, T = −40°C to 125°C, unless otherwise
CC BS DD J
BIAS
specified. The V , V and I parameters are referenced to V and are applicable to respective input leads: HIN, LIN and SD. The V
IH
IL
IN
SS
O
and I parameters are referenced to V and COM and are applicable to the respective output leads: HO and LO. The V
parameters
O
S
DDUV
are referenced to COM. The V
parameters are referenced to V
) (continued)
BSUV
S1, 2, 3
Symbol
Parameter
Conditions
Min
Typ
Max
Units
GATE DRIVER OUTPUT SECTION
I
I
Output HIGH Short−Circuit Pulse
V
V
= 0 V, V = 5 V with PW ≤ 10 ms
−
−
−
2.0
3.0
−
−
A
A
V
O+
O
IN
Current
Output LOW Short−Circuit Pulsed
Current
= 15 V, V = 0 V with PW ≤ 10 ms
IN
O−
O
V
Allowable Negative V Pin Voltage
−9.8
−7.0
S
S
for HIN Signal Propagation to HO
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. These parameters are guaranteed by design.
Table 5. DYNAMIC ELECTRICAL CHARACTERISTICS (V
J
(V , V
V
) = 15.0 V, V = V = COM, C = 1000 pF and
BIAS CC
BS, DD S SS L
T = −40°C to 125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LOW−SIDE POWER SUPPLY SECTION
t
Turn−On Propagation Delay
Turn−Off Propagation Delay
V
V
= 0 V
= 0 V
−
−
500
550
150
150
30
−
−
ns
ns
ns
ON
S
t
OFF
S
t
Input Filtering Time (HIN, LIN)
(Note 9)
T = 25°C
J
80
80
−
220
300
−
FLTIN
T = −40°C to 125°C
J
t
Input Filtering Time (SD)
ns
ns
FLTSD
t
Shutdown Propagation Delay Time
T = 25°C
J
260
200
−
330
330
25
400
550
−
SD
T = −40°C to 125°C
J
t
R
Turn−On Rise Time
Turn−Off Fall Time
ns
ns
ns
t
F
−
15
−
MT
PM
Delay Matching ,
HO & LO Turn−On/OFF (Note 10)
T = 25°C
J
−
−
50
60
100
140
T = −40°C to 125°C
J
−
−
Output Pulse−Width Matching
(Note 11)
PW > 1 ms
T = 25°C
−
50
IN
J
T = −40°C to 125°C
J
−
50
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. The minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded.
10.MT is defined as an absolute value of matching delay time between High−side and Low−Side.
11. PM is defined as an absolute value of matching pulse−width between Input and Output.
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FAN73912A
TYPICAL CHARACTERISTICS
580
560
660
640
620
600
580
560
540
520
500
480
540
520
500
480
460
440
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 5. Turn−Off Propagation Delay
Figure 4. Turn−On Propagation Delay
vs. Temperature
vs. Temperature
30
25
20
15
10
5
30
25
20
15
10
5
0
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 6. Turn−On Rise Time vs Temperature
Figure 7. Turn−Off Fall Time vs. Temperature
50
50
40
30
20
10
0
40
30
20
10
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 9. Turn−Off Delay Matching
Figure 8. Turn−On Delay Matching
vs. Temperature
vs. Temperature
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FAN73912A
TYPICAL CHARACTERISTICS (continued)
40
440
420
400
380
360
340
320
300
280
260
30
20
10
0
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 11. Logic Input High Bias Current
vs. Temperature
Figure 10. Shutdown Propagation Delay
vs. Temperature
220
210
200
190
180
170
160
150
140
130
120
110
100
90
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
V
= V
= V , V
= 0 V, V
= 0 V
LIN
HIN
LIN
V
V
= V
= V , V
= 0 V, V
= 0 V
LIN
HIN
LIN
= 0 V
HIN
DD
= 0 V
HIN
DD
(or V
= V
)
HIN
LIN
DD
(or V
= V
)
HIN
LIN
DD
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 13. Quiescent VDD Supply Current
vs. Temperature
Figure 12. Quiescent VCC Supply Current
80
70
60
50
40
30
20
10
0
800
700
600
500
400
300
200
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 15. Operating VCC Supply Current
Figure 14. Quiescent VBS Supply Current
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FAN73912A
TYPICAL CHARACTERISTICS (continued)
5.0
4.5
1000
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
800
600
400
200
0
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 17. Operating VBS Supply Current
vs. Temperature
Figure 16. Operating VDD Supply Current
11.0
10.8
10.6
10.4
10.2
10.0
9.8
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
9.6
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 19. VCC UVLO− vs. Temperature
Figure 18. VCC UVLO+ vs Temperature
11.0
10.8
10.6
10.4
10.2
10.0
9.8
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
9.6
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 21. VBS UVLO− vs. Temperature
Figure 20. VBS UVLO+ vs. Temperature
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FAN73912A
TYPICAL CHARACTERISTICS (continued)
0.010
0.008
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.006
0.004
0.002
0.000
−0.002
−0.004
−0.006
−0.008
−0.010
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 23. Low−Level Output Voltage
Figure 22. High−Level Output Voltage
vs. Temperature
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
VDD=15 V
VDD =3 V
V
= 15 V
= 3 V
DD
DD
V
−40 −20
0
20
40
60
80 100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 25. Logic Low Input Voltage
vs. Temperature
Figure 24. Logic High Input Voltage
−7
−8
12
10
8
−9
6
−10
−11
−12
4
V
V
IH
IL
2
0
−40 −20
0
20
40
60
80 100 120
0
2
4
6
8
10 12 14 16 18 20
V
DD
Logic Supply Voltage [V]
Temperature [°C]
Figure 27. Input Logic (HIN&LIN) Threshold
vs. VDD Supply Voltage
Figure 26. Allowable Negative VS
vs. Temperature
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FAN73912A
TYPICAL CHARACTERISTICS (continued)
600
580
−4
−6
High Side
Low Side
V
V
A
= V
SS
COM
T = 25°C
CC
560
540
520
500
480
460
440
420
400
= 0 V
−8
−10
−12
−14
−16
10 11 12 13 14 15 16 17 18 19 20
3
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
V
DD
Supply Voltage [V]
V
CC
Supply Voltage [V]
Figure 29. Turn−On Propagation Delay
Figure 28. Allowable Negative VS Voltage
for HIN Signal Propagation to High Side
vs. VCC Supply Voltage
vs. VDD Supply Voltage
350
300
250
200
150
100
50
600
580
560
540
520
500
480
460
440
420
400
Positive
High Side
Low Side
Negative
0
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
V
DD
V
DD
Supply Voltage [V]
Figure 31. Logic Input Filtering Time
vs. VDD Supply Voltage
Figure 30. Turn−Off Propagation Delay
vs. VDD Supply Voltage
160
140
120
100
80
440
420
400
380
360
340
320
300
280
260
Positive
High Side
Low Side
Negative
60
40
20
0
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
V
DD
Supply Voltage [V]
V
DD
Supply Voltage [V]
Figure 33. Shutdown Propagation Delay
vs. VDD Supply Voltage
Figure 32. Shutdown Input Filtering
Time vs. VDD Supply Voltage
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11
FAN73912A
TYPICAL CHARACTERISTICS (continued)
100
HighSide
LowSide
80
60
40
20
0
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
V
DD
Supply Voltage [V]
Figure 34. Output Pulse−Width Matching vs. VDD Supply Voltage
SWITCHING TIME DEFINITIONS
9 NC
NC
HO 8
HO
15 V
7
V
B
10
100 nF
1 nF
15 V
(0 to 1200 V)
6
5
4
V
V
S
11
12
DD
HIN
SD
NC
NC
HIN
SD
13
14
15 V
3
2
1
V
LIN
LIN
CC
100 nF
COM
15 V
SS
NC
LO
LO
16
1 nF
Figure 35. Switching Time Test Circuit
HIN
LIN
SD
HO
LO
Skip
Shutdown
Shutdown
Figure 36. Input/Output Timing Diagram
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12
FAN73912A
HIN
LIN
50%
50%
t
R
t
t
F
t
OFF
ON
90%
90%
HO
10%
10%
Figure 37. Switching Time Definition
50%
SD
t
SD
90%
HO
(LO)
Figure 38. Shutdown Waveform Definition
50%
LO
50%
HIN
LIN
MT
HO
10%
10%
90%
90%
LO
HO
MT
Figure 39. Delay Matching Waveform Definitions
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13
FAN73912A
APPLICATIONS INFORMATION
Shutdown Input
Short−Pulsed Input Noise Rejection Method
The input filter circuitry provides protection against
short−pulsed input signals (HIN, LIN, and SD) on the input
signal lines by applied noise signal.
When the SD pin is in LOW state, the gate driver operates
normally. When a condition occurs that should shut down
the gate driver, the SD pin should be HIGH. The Shutdown
circuitry has an input filter; the minimum input duration is
If the input signal duration is less than input filter time
specified by t
(typically 250 ns).
(t
), the output does not change states.
FLTIN
FLTIN
Example A and B of the Figure 42 show the input
and output waveforms with short−pulsed noise spikes
with a duration less than input filter time; the output does not
change states.
50%
SD
t
SD
IN
90%
t
t
t
FLTIN
FLTIN
FLTIN
HO
(LO)
OUT
(LOW)
Figure 40. Output Shutdown Timing Waveform
t
t
t
FLTIN
FLTIN
FLTIN
Noise Filter
OUT
(HIGH)
Input Noise Filter
Figure 41 shows the input noise filter method, which has
Figure 42. Noise Rejecting Input Filter Definition
symmetry duration between the input signal (t
)
INPUT
and the output signal (t ) and helps to reject noise
OUTPUT
spikes and short pulses. This input filter is applied to
the HIN, LIN, and EN inputs. The upper pair of waveforms
Negative VS Transient
The bootstrap circuit has the advantage of being simple
and low cost, but has some limitations. The biggest difficulty
with this circuit is the negative voltage present at the emitter
of the high−side switching device when high−side switch is
turned−off in half−bridge application. If the high−side
switch, Q1, turns−off while the load current is flowing to
an inductive load, a current commutation occurs from
high−side switch, Q1, to the diode, D2, in parallel with
the low−side switch of the same inverter leg. Then
the negative voltage present at the emitter of the high−side
switching device, just before the freewheeling diode, D2,
starts clamping, causes load current to suddenly flow to
the low−side freewheeling diode, D2, as shown in Figure 43.
(Example A) shows an input signal duration (t ) much
INPUT
longer than input filter time (t
); it is approximately
FLTIN
the same duration between the input signal time (t
)
INPUT
and the output signal time (t ). The lower pair
OUTPUT
of waveforms (Example B) shows an input signal time
(t ) slightly longer than input filter time (t ); it is
INPUT
FLTIN
approximately the same duration between input signal time
(t
) and the output signal time (tO
).
INPUT
UTPUT
t
IN
FLTIN
t
INPUT
t
DC+ Bus
Q1
OUTPUT
OUT
IN
D1
i
LOAD
i
freewheeling
t
FLTIN
Load
t
INPUT
Q2
t
OUTPUT
Output duration is
same as input duration
D2
OUT
Figure 43. Half−Bridge Application Circuits
Figure 41. Input Noise Filter Definition
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14
FAN73912A
DC+ Bus
L
This negative voltage can be trouble for the gate driver’s
output stage, there is the possibility to develop
an over−voltage condition of the bootstrap capacitor, input
signal missing and latch−up problems because it directly
affects the source VS pin of the gate driver, shown
in Figure 44. This undershoot voltage is called “negative VS
transient”.
L
C1
C2
Q2
Q1
D1
D2
i
LOAD
i
freewheeling
L
E2
L
E1
S1
C3
V
L
Load
V
S2
−
V
+
+
V
LC3
D3
L
C4
Q4
LC4
−
Q3
Q1
D4
−
+
L
E3
V
V
L
E4
LE3
LE4
+
−
Figure 46. Q1 Turn−Off and D3 Conducting
V
S
GND
The FAN73912A has a typical negative V transient
S
Freewheeling
characteristics, as shown in Figure 47.
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
−200
−220
Figure 44. VS Waveforms During Q1 Turn−Off
Figure 45 and Figure 46 show the commutation of the load
current between high−side switch, Q1, and low−side
freewheeling diode, D3, in same inverter leg. The parasitic
inductances in the inverter circuit from the die wire bonding
to the PCB tracks are jumped together in LC and LE for each
IGBT. When the high−side switch, Q1, and low−side switch,
Q4, are turned on, the VS1 node is below DC+ voltage by
the voltage drops associated with the power switch
and the parasitic inductances of the circuit due to load
current is flows from Q1 and Q4, as shown in Figure 45.
When thehigh−side switch, Q1, is turned off and Q4,
remained turned on, the load current to flows the low−side
freewheeling diode, D3, due to the inductive load connected
to VS1 as shown in Figure 46. Q1 Turn−Off and D3
Conducting. The current flows from ground (which is
connected to the COM pin of the gate driver) to the load
and the negative voltage present at the emitter
of the high−side switching device. In this case, the COM pin
50
100
150
200
250
300
Pulse Width [ns]
Figure 47. Negative VS Transient Characteristic
Even though the FAN73912A has been shown able to
handle these negative V transient conditions, it is strongly
recommended that the circuit designer limit the negative V
transient as much as possible by careful PCB layout to
minimize the value of parasitic elements and component
use. The amplitude of negative V voltage is proportional to
the parasitic inductances and the turn−off speed, di/dt, of the
switching device.
S
S
of the gate driver is at a higher potential than the V pin due
S
S
to the voltage drops associated with freewheeling diode, D3,
and parasitic elements, L and L
.
C3
E3
General Guidelines
DC+ Bus
+
Printed Circuit Board Layout
The layout recommended for minimized parasitic
elements is as follows:
• Direct tracks between switches with no loops or
deviation.
• Avoid interconnect links. These can add significant
inductance.
• Reduce the effect of lead−inductance by lowering
package height above the PCB.
• Consider co−locating both power switches to reduce
track length.
L
Q2
C2
L
C1
V
LC1
−
Q1
D1
D2
i
LOAD
+
i
freewheeling
L
L
V
E1
E2
LE1
−
V
L
Load
V
L
S1
S2
+
V
C4
C3
LC4
−
Q3
Q4
D4
D3
+
V
L
E3
L
LE4
E4
−
Figure 45. Q1 and Q4 Turn−On
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15
FAN73912A
use is typically 5 ~ 10 W that increase the V time
constant. If the voltage drop of bootstrap resistor
and diode is too high or the circuit topology does not
allow a sufficient charging time, a fast recovery or
ultra−fast recovery diode can be used.
• To minimize noise coupling, the ground plane should
not be placed under or near the high−voltage floating
side.
• To reduce the EM coupling and improve the power
switch turn−on/off performance, the gate drive loops
must be reduced as much as possible.
BS
• The bootstrap capacitor, C
, uses a low−ESR
BOOT
capacitor, such as ceramic capacitor. It is strongly
recommended that the placement of components is as
follows:
Placement of Components
The recommended placement and selection of component
as follows:
• Place components tied to the floating voltage pins (V
B
• Place a bypass capacitor between the V and V
CC
SS
and V ) near the respective high−voltage portions of
S
pins. A ceramic 1 mF capacitor is suitable for most
applications. This component should be placed as close
as possible to the pins to reduce parasitic elements.
the device and the FAN73912A. Not Connected (NC)
pins in this package maximize the distance between
the high−voltage and low−voltage pins (see Figure 3).
• Place and route for bypass capacitors and gate resistors
as close as possible to gate drive IC.
• The bypass capacitor from V to V supports both
CC
SS
the low−side driver and bootstrap capacitor recharge.
A value at least ten times higher than the bootstrap
capacitor is recommended.
• Locate the bootstrap diode, D
, as close as possible
BOOT
to bootstrap capacitor, C
.
BOOT
• The bootstrap resistor, R
, must be considered in
sizing the bootstrap resistance and the current
BOOT
• The bootstrap diode must use a lower forward voltage
drop and minimal switching time as soon as possible
for fast recovery or ultra−fast diode.
developed during initial bootstrap charge. If the resistor
is needed in series with the bootstrap diode, verify that
V does not fall below COM (ground). Recommended
B
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16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16, 300 mils
CASE 751BH−01
ISSUE A
DATE 18 MAR 2009
D
SYMBOL
MIN
NOM
MAX
2.36
2.49
2.64
A
A1
b
0.10
0.33
0.30
0.51
0.41
0.23
c
0.18
0.28
D
E
E1
e
10.08
10.01
7.39
10.31
10.31
7.49
10.49
10.64
7.59
E1 E
1.27 BSC
h
0.25
0.38
0º
0.75
1.27
8º
0.81
L
θ
PIN #1 IDENTIFICATION
TOP VIEW
h
c
q
A
b
e
L
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34279E
SOIC−16, 300 MILS
PAGE 1 OF 1
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