FAN7930CMX [ONSEMI]
功率因数控制器 (PFC)，CrCM，PFC 就绪信号;
| 型号： | FAN7930CMX |
| 厂家： | 
ONSEMI |
| 描述： | 功率因数控制器 (PFC)，CrCM，PFC 就绪信号 控制器 功率因数校正 光电二极管 |
| 文件： | 总22页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Critical Conduction Mode
PFC Controller
SOIC8
CASE 751EB
FAN7930C
Description
MARKING DIAGRAM
The FAN7930C is an active power factor correction (PFC)
controller for boost PFC applications that operate in critical
conduction mode (CRM). It uses a voltage−mode PWM that compares
an internal ramp signal with the error amplifier output to generate a
MOSFET turn−off signal. Because the voltage−mode CRM PFC
controller does not need rectified AC line voltage information, it saves
the power loss of an input voltage−sensing network necessary for a
current−mode CRM PFC controller.
7930C
ALYW
FAN7930C provides over−voltage protection (OVP),
open−feedback protection, over−current protection (OCP),
input−voltage−absent detection, and under−voltage lockout protection
(UVLO). The PFC−ready pin can be used to trigger other power stages
when PFC output voltage reaches the proper level with hysteresis.
The FAN7930C can be disabled if the INV pin voltage is lower than
0.45 V and the operating current decreases to a very low level. Using a
new variable on−time control method, total harmonic distortion
(THD) is lower than in conventional CRM boost PFC ICs.
7930C = Device Code
A
= Assembly Site
L
YW
= Wafer Lot Number
= Assembly Start Week
ORDERING INFORMATION
See detailed ordering and shipping information on page X of
this data sheet.
Features
• PFC−Ready Signal
• V −Absent Detection
IN
• Maximum Switching Frequency Limitation
• Internal Soft−Start and Startup without Overshoot
• Internal Total Harmonic Distortion (THD) Optimizer
• Precise Adjustable Output Over−Voltage Protection
• Open−Feedback Protection and Disable Function
• Zero−Current Detector (ZCD)
• 150 ms Internal Startup Timer
• MOSFET Over−Current Protection (OCP)
• Under−Voltage Lockout with 3.5 V Hysteresis
• Low Startup and Operating Current
• Totem−Pole Output with High State Clamp
• +500/−800 mA Peak Gate Drive Current
• 8−Pin, Small Outline Package (SOP)
Applications
• Adapter
• Ballast
• LCD TV, CRT TV
• SMPS
Related Resources
• AN−8035/D − Design Consideration for Boundary Conduction Mode
PFC Using FAN7930
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
November, 2021 − Rev. 4
FAN7930C/D
FAN7930C
ORDERING INFORMATION
†
Part Number
Operating Temperature Range
−40 to +125°C
Top Mark
7930C
Package
Shipping
FAN7930CMX−G
8−Lead, Small Outline Package (SOP)
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
APPLICATION DIAGRAM
DC OUTPUT
Vcc
FAN7930C
8
VCC
7
Out
+
5
line filter
ZCD
+
4
1
CS
3
2
COMP
RDY
INV
AC INPUT
GND
PFC
ready
6
Figure 1. Typical Boost PFC Application
INTERNAL BLOCK DIAGRAM
VCC
H:open
VREF
VBIAS
2.5 VREF
8
VCC
VCC
−
VZ
Internal
Bias
reset
+
VTH(S/S)
8.5 12
ZCD
5
−
VCC
+
Restart
Timer
Gate
VTH(ZCD)
7
OUT
Driver
fMAX
limit
VO(MAX)
THD
S
R
Q
Q
Optimized
Sawtooth
Generator
Control Range
Compensation
+
−
40 kW
Startup without
Overshoot
+
4
6
CS
8 pF
−
INV
1
−
VCS_LIM
VREF
Stair
Step
VREF
GND
+
Clamp
Circuit
reset
VIN Absent
COMP
RDY
3
2
disable
disable
Thermal
Shutdown
−
0.45
0.35
2.5 2.675
+
INV_open
VBIAS
OVP
UVLO
2.051 2.240
Figure 2. Functional Block Diagram
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2
FAN7930C
PIN CONFIGURATION
VCC
OUT
GND
ZCD
FAN7930C
8−SOP
INV
RDY COMP
CS
Figure 3. Pin Configuration (Top View)
PIN DEFINITIONS
Pin No.
Name
Description
1
INV
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter should be
resistively divided to 2.5 V.
2
3
4
5
6
7
8
RDY
COMP
CS
This pin is used to detect PFC output voltage reaching a pre−determined value. When output voltage reaches
89% of rated output voltage, this pin is pulled HIGH, which is an (open−drain) output type.
This pin is the output of the transconductance error amplifier. Components for the output voltage compensation
should be connected between this pin and GND.
This pin is the input of the over−current protection comparator. The MOSFET current is sensed using a sensing
resistor and the resulting voltage is applied to this pin. An internal RC filter is included to filter switching noise.
ZCD
GND
OUT
This pin is the input of the zero−current detection (ZCD) block. If the voltage of this pin goes higher than 1.5 V,
then goes lower than 1.4 V, the MOSFET is turned on.
This pin is used for the ground potential of all the pins. For proper operation, the signal ground and the power
ground should be separated.
This pin is the gate drive output. The peak sourcing and sinking current levels are +500 mA and −800 mA,
respectively. For proper operation, the stray inductance in the gate driving path must be minimized.
V
CC
This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.
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3
FAN7930C
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−
Max
Unit
V
V
CC
Supply Voltage
V
Z
I
, I
Peak Drive Output Current
−800
−10
−10
−
+500
+10
mA
mA
mA
OH OL
I
Driver Output Clamping Diodes V > V or V < −0.3 V
O CC O
CLAMP
I
Detector Clamping Diodes
RDY Pin (Note 1)
+10
DET
V
IN
V
Z
V
Error Amplifier Input, Output and ZCD (Note 1)
CS Input Voltage (Note 2)
−0.3
−10.0
−
8.0
6.0
T
J
Operating Junction Temperature
Operating Temperature Range
Storage Temperature Range
+150
+125
+150
2.5
°C
°C
°C
kV
T
A
−40
−65
−
T
STG
ESD
Electrostatic Discharge Capability
Human Body Model, JESD22−A114
Charged Device Model, JESD22−C101
−
2.0
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50 mA.
2. In case of DC input, the acceptable input range is −0.3 V~6 V: within 100 ns −10 V~6 V is acceptable, but electrical specifications are not
guaranteed during such a short time.
THERMAL IMPEDANCE
Symbol
Parameter
Min
Max
Unit
Q
JA
Thermal Resistance, Junction−to−Ambient (Note 3)
150
−
°C/W
3. Regarding the test environment and PCB type, please refer to JESD51−2 and JESD51−10.
ELECTRICAL CHARACTERISTICS (V = 14 V and T = −40°C~+125°C, unless otherwise noted)
CC
A
Symbol
SECTION
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
V
Start Threshold Voltage
V
Increasing
11
7.5
3.0
20
12
8.5
3.5
22
−
13
9.5
4.0
24
V
V
V
V
V
START
CC
V
Stop Threshold Voltage
UVLO Hysteresis
Zener Voltage
V
CC
Decreasing
STOP
HY
UVLO
V
Z
I
= 20 mA
CC
V
OP
Recommended Operating Range
13
20
SUPPLY CURRENT SECTION
I
I
Startup Supply Current
V
= V − 0.2 V
START
−
−
120
1.5
190
3.0
mA
mA
mA
mA
START
CC
I
Operating Supply Current
Dynamic Operating Supply Current
Operating Current at Disable
Output Not Switching
50 kHz, C = 1 nF
OP
I
−
2.5
4.0
DOP
OPDIS
I
V
INV
= 0 V
90
160
230
ERROR AMPLIFIER SECTION
V
Voltage Feedback Input Threshold1
Line Regulation
T = 25°C
2.465
−
2.500
0.1
20
2.535
10.0
−
V
mV
mV
mA
REF1
A
V
CC
= 14 V~20 V
DVREF1
DVREF2
Temperature Stability of V
Input Bias Current
(Note 4)
−
REF1
I
V
INV
V
INV
V
INV
V
INV
= 1 V~4 V
−0.5
−
−
0.5
−
EA,BS
I
Output Source Current
Output Sink Current
= V
− 0.1 V
−12
12
mA
EAS,SR
REF
REF
I
= V
+ 0.1 V
−
−
mA
EAS,SK
V
Output Upper Clamp Voltage
Zero−Duty Cycle Output Voltage
Transconductance (Note 4)
= 1 V, V = 0 V
6.0
0.9
90
6.5
1.0
115
7.0
1.1
140
V
EAH
CS
V
V
EAZ
g
m
mmho
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4
FAN7930C
ELECTRICAL CHARACTERISTICS (V = 14 V and T = −40°C~+125°C, unless otherwise noted) (continued)
CC
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MAXIMUM ON−TIME SECTION
t
t
Maximum On−Time Programming 1
Maximum On−Time Programming 2
T = 25°C, V = 1 V
ZCD
35.5
11.2
41.5
13.0
47.5
14.8
ms
ms
ON,MAX1
A
T = 25°C, I
= 0.469 mA
ON,MAX2
A
ZCD
CURRENT−SENSE SECTION
V
Current−Sense Input Threshold Voltage Limit
Input Bias Current
0.7
−1.0
−
0.8
−0.1
350
0.9
1.0
V
CS
I
V
= 0 V~1 V
mA
ns
CS,BS
CS
t
Current−Sense Delay to Output (Note 4)
dV/dt = 1 V/100 ns, from 0 V to 5 V
500
CS,D
ZERO−CURRENT DETECT SECTION
V
Input Voltage Threshold (Note 4)
Detect Hysteresis (Note 4)
Input High Clamp Voltage
Input Low Clamp Voltage
1.35
0.05
5.5
0
1.50
0.10
6.2
0.65
−0.1
−
1.65
0.15
7.5
V
V
ZCD
HY
ZCD
CLAMPH
V
I
I
= 3 mA
V
DET
V
= −3 mA
1.00
1.0
V
CLAMPL
ZCD,BS
ZCD,SR
DET
I
Input Bias Current
V
= 1 V~5 V
−1.0
−
mA
mA
mA
ns
ZCD
I
Source Current Capability (Note 4)
Sink Current Capability (Note 4)
T = 25°C
−4
A
I
T = 25°C
−
−
10
ZCD,SK
A
t
Maximum Delay From ZCD to Output
Turn−On (Note 4)
dV/dt = −1 V/100 ns, from 5 V to 0 V
100
−
200
ZCD,D
OUTPUT SECTION
V
Output Voltage High
I
I
= −100 mA, T = 25°C
9.2
−
11.0
1.0
50
12.8
2.5
V
V
OH
O
A
V
Output Voltage Low
= 200 mA, T = 25°C
A
OL
O
t
Rising Time (Note 4)
C
= 1 nF
= 1 nF
−
100
100
14.5
1
ns
ns
V
RISE
FALL
IN
t
Falling Time (Note 4)
C
−
50
IN
V
Maximum Output Voltage
Output Voltage with UVLO Activated
V
V
= 20 V, I = 100 mA
11.5
−
13.0
−
O,MAX
CC
CC
O
V
= 5 V, I = 100 mA
V
O,UVLO
O
RESTART / MAXIMUM SWITCHING FREQUENCY LIMIT SECTION
t
Restart Timer Delay
50
150
300
300
350
ms
RST
MAX
f
Maximum Switching Frequency (Note 4)
250
kHz
RDY PIN
I
Output Sink Current
1
−
−
2
320
−
4
500
1
mA
mV
mA
RDY,SK
V
Output Saturation Voltage
Output Leakage Current
I
= 2 mA
RDY,SAT
RDY,SK
I
Output High Impedance
RDY,LK
SOFT−START TIMER SECTION
Internal Soft−Soft (Note 4)
UVLO SECTION
t
SS
3
5
7
ms
V
Output Ready Voltage
2.166
2.240
0.189
2.314
V
V
RDY
HY
Output Ready Hysteresis
−
−
RDY
PROTECTIONS
V
OVP Threshold Voltage
T = 25°C
2.620
0.120
0.40
0.05
125
2.675
0.175
0.45
0.10
140
2.730
0.230
0.50
0.15
155
V
V
OVP
A
HY
OVP Hysteresis
T = 25°C
A
OVP
V
Enable Threshold Voltage
Enable Hysteresis
V
EN
HY
V
EN
T
Thermal Shutdown Temperature (Note 4)
Hysteresis Temperature of TSD (Note 4)
°C
°C
SD
T
HYS
60
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. These parameters, although guaranteed by design, are not production tested.
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FAN7930C
COMPARISON OF FAN7530 AND FAN7930C
Function
FAN7530
FAN7930C
FAN7930C Advantages
PFC Ready Pin
None
Integrated
• No External Circuit for PFC Output UVLO
• Reduce Power Loss and BOM Cost Caused by PFC Out UVLO Circuit
• Versatile Open−Drain Pin
Frequency Limit
None
None
None
None
Integrated
Integrated
Integrated
Integrated
Internal
• Abnormal CCM Operation Prohibited
• Abnormal Inductor Current Accumulation Can Be Prohibited
VIN−Absent
Detection
• Increase System Reliability by Testing for Input Supply Voltage
• Guarantee Stable Operation at Short Electric Power Failure
Soft−Start and
Startup without
Overshoot
• Reduce Voltage and Current Stress at Startup
• Eliminate Audible Noise due to Unwanted OVP Triggering
Control Range
Compensation
• Can Avoid Burst Operation at Light Load and High Input Voltage
• Reduce Probability of Audible Noise Due to Burst Operation
THD Optimizer
TSD
External
None
• No External Resistor Needed
140°C with 60°C
• Stable and Reliable TSD Operation
• Converter Temperature Range Limited Range
Hysteresis
COMPARISON OF FAN7530C AND FAN7930B
Function
RDY Pin
RDY Pin
FAN7530C
Integrated
None
FAN7930B
None
Remark
• User Choice for the Use of Number #2 Pin
Integrated
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6
FAN7930C
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Voltage Feedback Input Threshold 1 (VREF1
)
Figure 5. Start Threshold Voltage (VSTART) vs. TA
vs. TA
Figure 6. Stop Threshold Voltage (VSTOP) vs. TA
Figure 7. Startup Supply Current (ISTART) vs. TA
Figure 8. Operating Supply Current (IOP) vs. TA
Figure 9. Output Upper Clamp Voltage (VEAH) vs. TA
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FAN7930C
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Figure 10. Zero Duty Cycle Output Voltage (VEAZ
vs. TA
)
Figure 11. Maximum On−Time Program 1 (tON,MAX1
vs. TA
)
Figure 12. Maximum On−Time Program 2 (tON,MAX2
)
Figure 13. Current−Sense Input Threshold Voltage
vs. TA
Limit (VCS) vs. TA
Figure 14. Input High Clamp Voltage (VCLAMPH) vs. TA Figure 15. Input Low Clamp Voltage (VCLAMPL) vs. TA
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FAN7930C
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Figure 16. Output Voltage High (VOH) vs. TA
Figure 17. Output Voltage Low (VOL) vs. TA
Figure 18. Restart Timer Delay (tRST) vs. TA
Figure 19. Output Ready Voltage (VRDY) vs. TA
Figure 20. Output Saturation Voltage (VRDY,SAT) vs.
TA
Figure 21. OVP Threshold Voltage (VOVP) vs. TA
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FAN7930C
APPLICATIONS INFORMATION
PFC
VOUT
Startup
+
Normally, supply voltage (V ) of a PFC block is fed from
the additional power supply, which can be called standby
power. Without this standby power, auxiliary winding for
zero current detection can be used as a supply source. Once
the supply voltage of the PFC block exceeds 12 V, internal
operation is enabled until he voltage drops to 8.5 V. If VCC
CC
2.240 V/2.051 V
2.675 V/2.5 V
UVLO
OVP
−
−
2.5 2.675
+
disable
−
INV open
0.45
0.35
+
+
0.45 V/0.35 V
2.5 V
exceeds V , 20 mA current is sinking from V
.
Z
CC
INV
high
PFC Inductor
−
PFC
PFC
1
VIN
VOUT
disable
2.051 2.240
2
3
Aux. Winding
RDY
COMP
VCC
’
External VCC circuit
when no standby power exists
Figure 23. Circuit Around INV Pin
PFC
VOUT
413 V
390 V
390 Vdc
349 V
VCC
320 V
H:open
VCC
’
2.5 VREF
8
VREF
VBIAS
−
VZ
Internal
Bias
70 V
reset
55 V
+
VTH(S/S)
20 mA
VINV
2.65 V
2.50 V
0.45 V
2.50 V
2.051 V
8.5 12
2.24 V
0.35 V
Figure 22. Startup Circuit
VCC
INV Block
2.0 V
Scaled−down voltage from the output is the input for the
INV pin. Many functions are embedded based on the INV
pin: transconductance amplifier, output OVP comparator,
disable comparator, and output UVLO comparator.
COMP
IOUT
Current sourcing
Current sourcing
Disable
I sinking
For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
VRDY
OVP
amplifier.
The
transconductance
amplifier
Voltage is decided by pull−up voltage.
(voltage−controlled current source) aids the implementation
of the OV P and disable functions. The output current of the
amplifier changes according to the voltage difference of the
inverting and non−inverting input of the amplifier. To cancel
down the line input voltage effect on power factor correction,
the effective control response of the PFC block should be
slower than the line frequency and this conflicts with the
transient response of controller. Two−pole one−zero type
compensation can meet both requirements.
Vcc < 2 V, internal logic is not alive.
− RDY pin is floating, so pull up voltage is shown.
− Internal signals are unknown.
t
Figure 24. Timing Chart for INV Block
RDY Output
When the INV voltage is higher than 2.24 V, RDY output
is triggered HIGH and lasts until the INV voltage is lower
than 2.051 V. When input AC voltage is quite high, for
The OVP comparator shuts down the output drive block
when the voltage of the INV pin is higher than 2.675 V and
there is 0. 175 V hysteresis. The disable comparator disables
operation when the voltage of the inverting input is lower than
0.35 V and there is 100 mV hysteresis. An external
small−signal MOSFET can be used to disable the IC, as show
n in Figure 23. The IC operating current decreases to reduce
pow er consumption if the IC is disabled. Figure 24 is the
timing chart of the internal circuit near the INV pin when
example 240 V , PFC output voltage is always higher than
RDY threshold, regardless of boost converter operation. In
this case, the INV voltage is already higher than 2.24 V before
AC
PFC V touches V
; however, RDY output is not
START
CC
triggered to HIGH until V touches V
. After boost
START
CC
converter operation stops, RDY is not pulled LOW because
the INV voltage is higher than the RDY threshold. When V
CC
of the PFC drops below 5 V, RDY is pulled LOW even though
PFC output voltage is higher than threshold. The RDY pin
output is open drain, so needs an external pull−up resistor to
supply the proper power source. The RDY pin output remains
rated PFC output voltage is 390 V and V supply voltage
DC
CC
is 15 V.
floating until V is higher than 2 V.
CC
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10
FAN7930C
VCC
VSTART
Control Range Compensation
On time is controlled by the output voltage compensator
with FAN7930C. Due to this when input voltage is high and
load is light, control range becomes narrow compared to
when input voltage is low. That control range decrease is
inversely proportional to the double square of the input
1
VSTOP
PFC operation
5 V
VINV (= VPFCOUT
2.500 V
2.240 V
2.051 V
)
voltage (control range a
). Thus at high line,
input voltage2
unwanted burst operation easily happens at light load and
audible noise may be generated from the boost inductor or
inductor at input filter. Different from the other converters,
burst operation in PFC block is not needed because the PFC
block itself is normally disabled during standby mode. To
reduce unwanted burst operation at light load, an internal
control range compensation function is implemented and
shows no burst operation until 5% load at high line
VRDY
t
VCC
VSTART
VSTOP
PFC operation
Zero−Current Detection
5 V
Zero−current detection (ZCD) generates the turn−on signal
of the MOSFET when the boost inductor current reaches zero
using an auxiliary winding coupled with the inductor. When
the power switch turns on, negative voltage is induced at the
auxiliary winding due to the opposite winding direction (see
Equation 2). Positive voltage is induced (see Equation 3)
when the power switch turns off.
VINV (= VPFCOUT
)
2.500 V
2.240 V
2.051 V
V
RDY
1
control range a
input voltage2
(eq. 1)
t
TAUX
Figure 25. Two Cases of RDY Triggered HIGH
VAUX + *
@ VAC
(eq. 2)
(eq. 3)
TIND
VCC
TAUX
TIND
VAUX
+
@ (VPFCOUT * VAC
)
VSTART
VSTOP
PFC operation
5 V
where:
V
is the auxiliary winding voltage;
is boost inductor turns;
auxiliary winding turns;
AUX
VINV (= VPFCOUT
)
T
T
IND
2.500 V
2.240 V
2.051 V
IND
V
AC
is input voltage for PFC converter; and
V
is output voltage from the PFC converter.
OUT_PFC
VRDY
PFC Inductor
PFC
PFC
VIN
VOUT
Aux Winding
t
VCC
VCC
RZCD
VSTART
VSTOP
Negative Clamp
Circuit
PFC operation
5 V
ZCD
5
−
+
CZCD
VINV (= VPFCOUT
)
Restart
Timer
VTH(ZCD)
Positive Clamp
2.500 V
2.240 V
2.051 V
Circuit
optional
gate
driver
fMAX
limit
S
R
Q
Q
THD optimized
Sawtooth
Generator
VRDY
Figure 27. Circuit Near ZCD
t
Figure 26. Two Cases of RDY Triggered LOW
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11
FAN7930C
V
DS
Because auxiliary winding voltage can swing from
negative to positive voltage, the internal block in ZCD pin has
both positive and negative voltage clamping circuits. When
the auxiliary voltage is negative, an internal circuit clamps the
negative voltage at the ZCD pin around 0.65 V by sourcing
current to the serial resistor between the ZCD pin and the
auxiliary winding. When the auxiliary voltage is higher than
6.5 V current is sinked through a resistor from the auxiliary
winding to the ZCD pin.
VOUT PFC − VIN
VOUT PFC − VIN
VIN
IINDUCTOR
IDIODE
IMOSFET
ISW
V
ZCD
IDIODE
VACIN
IMOSFET
1.5 V
1.4 V
VAUX & VZCD
VAUX
MOSFET gate
ON
150 ns Delay
VZCD
ON
6.2 V
0.65 V
t
t
Figure 29. Auxiliary Voltage Threshold
Figure 28. Auxiliary Voltage Depends on MOSFET
Switching
When no ZCD signal is available, the PFC controller
cannot turn on the MOSFET, so the controller checks every
switching off time and forces MOSFET turn on when the off
time is longer than 150 ms. This restart timer triggers
MOSFET turn−on at startup and may be used at the input
voltage zero−cross period.
The auxiliary winding voltage is used to check the boost
inductor current zero instance. When boost inductor current
becomes zero, there is a resonance between boost inductor
and all capacitors at the MOSFET drain pin: including C
OSS
of the MOSFET; an external capacitor at the D−S pin to
reduce the voltage rising and falling slope of the MOSFET;
a parasitic capacitor at inductor; and so on to improve
performance. Resonated voltage is reflected to the auxiliary
winding and can be used for detecting zero current of boost
inductor and valley position of MOSFET voltage stress. For
valley detection, a minor delay by the resistor and capacitor
is needed. A capacitor increases the noise immunity at the
ZCD pin. If ZCD voltage is higher than 1.5 V, an internal ZCD
comparator output becomes HIGH and LOW when the ZCD
goes below 1.4 V. At the falling edge of comparator output,
internal logic turns on the MOSFET.
VOUT
VIN
VCC
t RESTART
150 m s
MOSFET gate
ZCDafter COMPARATOR
t
Figure 30. Restart Timer at Startup
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12
FAN7930C
Because the MOSFET turn−on depends on the ZCD input,
signal. The “ON” instant is determined by the external signal
switching frequency may increase to higher than several
megahertz due to the mis−triggering or noise on the nearby
ZCD pin. If the switching frequency is higher than needed for
critical conduction mode (CRM), operation mode shifts to
continuous conduction mode (CCM). In CCM, unlike CRM
where the boost inductor current is reset to zero at the next
switch on; inductor current builds up at every switching cycle
and can be raised to very high current that exceeds the current
rating of the power switch or diode. This can seriously
damage the power switch. To avoid this, maximum switching
frequency limitation is embedded. If ZCD signal is applied
again within 3.3 ms after the previous rising edge of gate
signal, this signal is ignored internally and FAN7930C waits
for another ZCD signal. This slightly degrades the power
factor performance at light load and high input voltage.
and the turn−on time lasts until the error amplifier output
(V ) and saw tooth waveform meet. When load is heavy,
COMP
output voltage decreases, scaled output decreases, COMP
voltage increases to compensate low output, turn−on time
lengthens to give more inductor turn−on time, and increased
inductor current raises the output voltage. This is how a PFC
negative feedback controller regulates output.
The maximum of V
is limited to 6.5 V, which dictates
COMP
the maximum turn−on time. Switching stops when V
is
COMP
lower than 1.0 V.
ZCD after COMPARATOR
VCOMP & Sawtooth
ZCDafter COMPARATOR
Ignores ZCD noise
0.155 V / m s
MOSFET gate
MOSFET Gate
Max. fSW Limit
Error occurs!
t
Figure 33. Turn−On Time Determination
The roles of PFC controller are regulating output voltage
and input current shaping to increase power factor. Duty
control based on the output voltage should be fast enough to
compensate output voltage dip or overshoot. For the power
factor, however, the control loop must not react to the
fluctuating AC input voltage. These two requirements
conflict; therefore, when designing a feedback loop, the
feedback loop should be least ten times slower than AC line
frequency. That slow response is made by C1 at the
compensator. R1 makes gain boost around operation region
and C2 attenuates gain at higher frequency. Boost gain by R1
helps raise the response time and improves phase margin.
t
Inhibit Region
Figure 31. Maximum Switching Frequency Limit
Operation
Control
The scaled output is compared with the internal reference
voltage and sinking or sourcing current is generated from the
COMP pin by the transconductance amplifier. The error
amplifier output is compared with the internal saw tooth
waveform to give proper turn−on time based on the controller.
PFC
VOUT
Gain
Integrator
C 1
6.2 V
Proportional
gain
THD−Optimized
Sawtooth
Generator
1 V
+
MOSFET Off
Sawtooth
R1
−
INV
Freq.
1
3
−
VREF
Stair
Step
+
C 2
Clamp
Circuit
High−Frequency
Noise Filter
COMP
R1
C1
C2
Figure 34. Compensators Gain Curve
For the transconductance error amplifier side, gain changes
based on differential input. When the error is large, gain is
large to suppress the output dip or peak quickly. When the
error is small, low gain is used to improve power factor
performance.
Figure 32. Control Circuit
Unlike a conventional voltage−mode PWM controller,
FAN7930C turns on the MOSFET at the falling edge of ZCD
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13
FAN7930C
ICOMP
Operation on and off by OV P at startup may cause audible
noise and can increase voltage stress at startup, which is
normally higher than in normal operation. This operation is
improved when soft−start time is very long. However, too
much startup time enlarges the output voltage building time
at light load. FA N7930C has overshoot protection at startup.
During startup, the feedback loop is controlled by an internal
proportional gain controller and, when the output voltage
reaches the rated value, it switches to an external compensator
after a transition time of 30 ms. This internal proportional
gain controller eliminates overshoot at startup and an external
conventional compensator takes over successfully afterward.
Powering
250 mmho
115
mmho
Braking
VOUT
Figure 35. Gain Characteristic
Conventional Controller
Startup Overshoot
Soft−Start
When V reaches VSTART, the internal reference voltage
CC
Startup Overshoot Control
is increased like a stair step for 5 ms. As a result, V
is
COMP
also raised gradually and MOSFET turn−on time increases
smoothly. This reduces voltage and current stress on the
power switch during startup.
Control Transition
VCOMP
VCC
Depends on Load
VSTART = 12 V
Internal Controller
SS
VREFEND = 2.5 V
VREF
5 ms
t
Figure 37. Startup without Overshoot
VINV = 0.4 V
gM
THD Optimization
Total Harmonic Distortion (THD) is the factor that dictates
how closely input current shape matches sinusoidal form. The
turn−on time of the PFC controller is almost constant over one
AC line period due to the extremely low feedback control
response. The turn−off time is determined by the current
decrease slope of the boost inductor made by the input voltage
and output voltage. Once inductor current becomes zero,
COMP
COMP
(VREFSS− VINV
)
gM = ISOURCE
ISOURCE
resonance between C
and the boost inductor makes
OSS
COMP
oscillating waveforms at the drain pin and auxiliary winding.
By checking the auxiliary winding voltage through the ZCD
pin, the controller can check the zero current of boost
inductor. At the same time, a minor delay is inserted to deter
mine the valley position of drain voltage. The input and
output voltage difference is at its maximum at the zero cross
point of AC input voltage. The current decrease slope is steep
near the zero cross region and more negative inductor current
flows during a drain voltage valley detection time. Such a
negative inductor current cancels down the positive current
flows and input current becomes zero, called “zero−cross
distortion” in PFC.
VCOMP
ISOURCE
RCOMP = VCOMP
t
Figure 36. Soft−Start Sequence
Startup without Overshoot
Feedback control speed of PFC is quite slow. Due to the
slow response, there is a gap between output voltage and
feedback control. That is why over−voltage protection (OVP)
is critical at the PFC controller and voltage dip caused by fast
load changes from light to heavy is diminished by a bulk
capacitor. OV P is triggered during startup phase.
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14
FAN7930C
IIN
VAUX
RZCD
Vcc
IINDUCTOR
THD Optimizer
N
IDIODE
IMOSFET
1
VZCD
INEGATIVE
ZCD
5
1.5 V
1.4 V
Zero−Current
Detect
150 ns
MOSFET gate
VREF
ON
ON
IMOT
t
CMOT
reset
Figure 38. Input and Output Current Near Input
Voltage Peak
Sawtooth Generator
IIN
Figure 40. Circuit of THD Optimizer
tON is typically constant over 1 AC line frequency,
but tON is changed by ZCD voltage.
IINDUCTOR
VZCD
tON
VZCD
INEGATIVE
1.5 V
t
tON not shorter
tON get shorter
1.4 V
VZCD at FET on
150 ns
MOSFET gate
ON
ON
ON
ON
Figure 41. Effect of THD Optimizer
t
By THD optimizer, turn−on time over one AC line period
is proportionally changed, depending on input voltage. Near
zero cross, lengthened turn−on time improves THD
performance.
Figure 39. Input and Output Current Near Input
Voltage Peak Zero Cross
To improve this, lengthened turn−on time near the zero
cross region is a well−known technique, though the method
may vary and may be proprietary. FA N7930C optimizes this
by sourcing current through the ZCD pin. Auxiliary winding
voltage becomes negative when the MOSFET turns on and is
proportional to input voltage. The negative clamping circuit
of ZCD outputs the current to maintain the ZCD voltage at a
fixed value. The sourcing current from the ZCD is directly
proportional to the input voltage. Some portion of this current
is applied to the internal saw tooth generator, together with a
fixed−current source. Theoretically, the fixed−current source
and the capacitor at saw tooth generator determine the
maximum turn−on time when no current is sourcing at ZCD
clamp circuit and available turn−on time gets shorter
proportional to the ZCD sourcing current.
VIN−Absent Detection
To save power loss caused by input voltage sensing
resistors and to optimize THD, the FA N7930C omits AC
input voltage detection. Therefore, no information about AC
input is available from the internal controller. In many cases,
the V of PFC controller is supplied by an independent
CC
power source, like standby power. In this scheme, some
mismatch may exist. For example, when the electric power is
suddenly interrupted during two or three AC line periods;
V
CC
is still live during that time, but output voltage drops
because there is no input power source. Consequently, the
control loop tries to compensate for the output voltage drop
and V
reaches its maximum. This lasts until AC input
COMP
voltage is live again. When AC input voltage is live again,
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15
FAN7930C
VOUT
VIN
high V
allows high switching current and more stress is
COMP
put on the MOSFET and diode. To protect against this,
FAN7930C checks if the input AC voltage exists. If input
does not exist, soft−start is reset and waits until AC input is
live again. Soft−start manages the turn−on time for smooth
operation when it detects AC input is applied again and
applies less voltage and current stress on startup.
Though V is
IN
eliminated, operation of
controller is normal due
to the large bypass
capacitor.
VAUX
VOUT
VIN
Though V is
IN
DMAX
f MIN
eliminated, operation of
controller is normal due
to the large bypass
capacitor.
DMIN
MOSFET gate
NewV COMP
f MIN
VIN Absence Detected
VAUX
IDS
Smooth
Soft−Start
DMAX
MOSFET gate
VCOMP
fMIN
t
Figure 43. With VIN−Absent Circuit
Current Sense
IDS
High drain
current!
The MOSFET current is sensed using an external sensing
resistor for over−current protection. If the CS pin voltage is
higher than 0.8 V, the over−current protection comparator
generates a protection signal. An internal RC filter of 40 kW
and 8 pF is included to filter switching noise.
t
Figure 42. Without VIN−Absent Circuit
Gate Driver Output
FAN7930C contains a single totem−pole output stage
designed for a direct drive of the power MOSFET. The drive
output is capable of up to +500 / −800 mA peak current with
a typical rise and fall time of 50 ns with 1 nF load. The output
voltage is clamped to 13 V to protect the MOSFET gate even
if the V voltage is higher than 13 V.
CC
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16
FAN7930C
PCB LAYOUT GUIDE
PFC block normally handles high switching current and
5. A stabilizing capacitor for VCC is recommended as
close as possible to the VCC and ground pins. If it is
difficult, place the SMD capacitor as close to the
corresponding pins as possible.
the voltage low energy signal path can be affected by the
high energy path. Cautious PCB layout is mandatory for
stable operation.
1. The gate drive path should be as short as possible.
The closed−loop that starts from the gate driver,
MOSFET gate, and MOSFET source to ground of
PFC controller should be as close as possible. This
is also crossing point between power ground and
signal ground. Power ground path from the bridge
diode to the output bulk capacitor should be short
and wide. The sharing position between power
ground and signal ground should be only at one
position to avoid ground loop noise. Signal path of
the PFC controller should be short and wide for
external components to contact.
2. The PFC output voltage sensing resistor is normally
high to reduce current consumption. This path can be
affected by external noise. To reduce noise potential
at the INV pin, a shorter path for output sensing is
recommended. If a shorter path is not possible, place
some dividing resistors between PFC output and the
INV pin — closer to the INV pin is better. Relative
high voltage close to the INV pin can be helpful.
3. The ZCD path is recommended close to auxiliary
winding from boost inductor and to the ZCD pin. If
that is difficult, place a small capacitor (below
50 pF) to reduce noise.
Figure 44. Recommended PCB Layout
4. The switching current sense path should not share
with another path to avoid interference. Some
additional components may be needed to reduce the
noise level applied to the CS pin.
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17
FAN7930C
TYPICAL APPLICATION CIRCUIT
TYPICAL APPLICATION CIRCUIT
Output Voltage
(Maximum Current)
Application
Device
FAN7930C
Input Voltage Range
90 − 265 V
Rated Output Power
195 W
LCD TV Power Supply
390 V (0.5 A)
AC
Features
• Because the input bias current of INV pin is almost zero,
output voltage sensing resistors (R112~R115) should be
as high as possible. However, too−high resistance makes
the node susceptible to noise. Resistor values need to
strike a balance between power consumption and noise
immunity.
• Quick charge diode (D106) can be eliminated if output
diode inrush current capability is sufficient. Even without
D106, system operation is normal due to the controller’s
highly reliable protection features.
• Average efficiency of 25%, 50%, 75%, and 100% load
conditions is higher than 95% at universal input.
• Power factor at rated load is higher than 0.98 at universal
input.
• Total Harmonic Distortion (THD) at rated load is lower
than 15% at universal input.
Key Design Notes
• When auxiliary V supply is not available, V power
CC
CC
can be supplied through Zero Current Detect (ZCD)
winding. The power consumption of R103 is quite high,
so its power rating needs checking.
Schematic
Optional
D106
600V 3A
D105
600V 8A
194mH, 39:5
DC OUTPUT
LP101,EER3019N
BD101,
600V,15A
VAUX
R103,
10k,1W
C104,
12nF
R109
47
Q101
FCPF
20N60
D102,
UF4004
D103,1N4148
R108
4.7
8
7
VCC
Out
C102,
680nF
5
ZCD
4
CS
3
Comp
1
2
INV
RDY
GND
6
C114, C115,
2.2nF 2.2nF
C101,
220nF
R101,1M−J
VCC for another power stage
ZNR101,
10D471
Circuit for VCC. If external VCC is used, this circuit is not needed.
Circuit for VCC for another power stage thus components structure and values may vary.
Figure 45. Demonstration Circuit
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18
FAN7930C
Transformer
EER3019N
1,2
Naux
9,10
1,2
9,10
6,7
NP
Naux
Np
6,7
3,4
3,4
Figure 46. Transformer Schematic Diagram
Winding Specification
WINDING SPECIFICATION
Position
No
Np
Pin (S " F)
3, 4 → 1, 2
Wire
Turns
Winding Method
Bottom
39
Solenoid Winding
0.1φ x 50
Insulation: Polyester Tape t = 0.05 mm, 3 Layers
9, 10 → 6, 7
Top
NAUX
5
Solenoid Winding
0.3φ
Insulation: Polyester Tape t = 0.05 mm, 4 Layers
Electrical Characteristics
ELECTRICAL CHARACTERISTICS
Pin
3, 4 → 1, 2
Specification
Remark
Inductance
194 mH 5%
100 kHz, 1 V
Core & Bobbin
Core: EER3019, Samhwa (PL−7) (Ae = 137.0 mm )
2
Bobbin: EER3019
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19
FAN7930C
BILL OF MATERIALS
BILL OF MATERIALS
Part #
Value
Note
Part #
Value
Note
Resistor
Switch
Diode
®
R101
R102
R103
R104
1 MW
330 kW
10 kW
30 kW
1 W
1/2 W
1 W
Q101
FCPF20N60
20 A, 600 V, SUPERFET
D101
D102
1N4746
UF4004
1 W, 18 V, Zener Diode
1/4 W
1 A, 400 V Glass Passivated
High−Efficiency Rectifier
R107
R108
R109
10 kW
4.7 kW
47 kW
1/4 W
1/4 W
1/4 W
D103
D104
D105
1N4148
1N4148
1 A, 100 V Small−Signal Diode
1 A, 100 V Small−Signal Diode
8 A, 600 V, General−Purpose
Rectifier
R110
R111
10 kW
1/4 W
D106
3 A, 600 V, General−Purpose
Rectifier
0.80 kW
3.9 kW
5 W
R112, 113,
114
1/4 W
IC101
FAN7930C
CRM PFC Controller
R115
75 kW
1/4 W
Capacitor
Fuse
C101
C102
C103
C104
C105
C107
C108
C109
C110
C112
C111
C114
C115
220 nF / 275 V
Box Capacitor
Box Capacitor
FS101
TH101
BD101
LF101
T1
5 A / 250 V
AC
AC
680 nF / 275 V
NTC
0.68 mF / 630 V
12 nF / 50 V
100 nF / 50 V
33 mF / 50 V
220 nF / 50 V
47 nF / 50 V
1 nF / 50 V
Box Capacitor
5D−15
Ceramic Capacitor
SMD (1206)
Bridge Diode
Line Filter
Transformer
ZNR
15 A, 600 V
Electrolytic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Electrolytic Capacitor
Box Capacitor
23 mH
EER3019
10D471
2
Ae = 137.0 mm
47 nF / 50 V
220 mF / 450 V
2.2 nF / 450 V
2.2 nF / 450 V
ZNR101
Box Capacitor
SUPERFET is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in
the United States and/or other countries.
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20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
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DOCUMENT NUMBER:
DESCRIPTION:
98AON13735G
SOIC8
PAGE 1 OF 1
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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