FAN8060EMPX [ONSEMI]
1.2MHz，1A 同步步降 DC-DC 转换器;
| 型号： | FAN8060EMPX |
| 厂家： | 
ONSEMI |
| 描述： | 1.2MHz，1A 同步步降 DC-DC 转换器 开关 光电二极管 转换器 |
| 文件： | 总14页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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November 2013
FAN8060
1.2 MHz, 1 A Synchronous Step-Down DC/DC
Regulator
Features
Description
The FAN8060 is a highly efficient, monolithic, current-
mode, step-down synchronous regulator. It can provide
1 A continuous current from 2.5 V to 5.5 V input
voltage. The output voltage can be adjusted from 1.2 V
up to the input voltage with an external voltage divider.
.
.
.
.
.
.
.
.
.
.
Current Mode Control
Over 96% Efficient
Selectable Continuous Output Current: 500 mA/1 A
2.5 V to 5.5 V Input Voltage Range
Output Voltage as Low as 1.2 V
1.2 MHz Operating Frequency
External compensation and soft-start allow for design
optimization and flexibility. High-frequency operation
allows for all-ceramic solutions and small footprints. In
Less than 1 µA Shutdown Current
External Synchronization from 500 kHz to 2 MHz
100% Duty Cycle
addition,
a
user-selectable current limit provides
protection against output overload and short circuit.
FAN8060 features pulse skipping to achieve higher
efficiency during light load operation. 100% duty cycle
capability enables power solutions to extend the drop
out voltage.
Synchronous Switching FET; no Schottky Diode
Required
.
.
.
.
.
.
.
.
Stable with Ceramic Capacitors
Light Load Mode with Pulse Skipping
External Compensation
Provision for external synchronization allows users to
minimize input capacitors and manage EMI in solutions.
External Soft-Start
FAN8060 is available in a green, low profile, 10-Lead
3x3 mm MLP package.
Overload / Short-Circuit Protection
Under-Voltage Lockout
Thermal Shutdown
HI
10-Lead 3x3 mm Green MLP Package
INPUT
2.5 to 5.5V
EN
PVIN
AVIN
LO
SYNC
Applications
OUTPUT
1.2V to 5.5V
FAN8060
SS
SW
LOUT
.
.
.
.
.
.
.
.
.
.
.
PDAs
COMP
CIN
R2
R3
COUT
GPS Devices
MP3 Players
Mini PCI
FB
RC
PGND
AGND
CSS
CA
CC
Digital Cameras
Peripheral Ports
DSP Core
Figure 1. Typical Application Circuit
USB Devices
PCMCIA
Cable Modem
Data Cards
Ordering Information
Operating
Temperature Range
Part Number
Package
Packing Method
10-Pin, 3x3 mm Molded Leadless
Package (MLP)
FAN8060EMPX
-40 to +85°C
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
Pin Configuration
1
2
3
4
5
10
9
EN
AVIN
PVIN
AGND
FB
8
COMP
SS
7
SW
6
SYNC
PGND
Figure 2. Pin Configuration (Top View)
Note:
1. Connect exposed PAD to AGND
Pin Definitions
Pin
1
Name
EN
Function
Enable. Enables operation when pulled to logic HIGH.
Analog Input Voltage. All internal control circuits are connected to this supply.
Power Input Voltage. Power stage supply voltage.
2
AVIN
PVIN
SW
3
4
Switching Node. The drains of both PMOS and NMOS.
Power Ground. Power return and source of the power NMOS
5
PGND
Synchronization. Use this pin to synchronize the part to an external clock. This pin also
controls current limit threshold. Tie to ground for 1.0 A or tie to VIN for 0.5 A continuous load
current. When an external clock is applied, the default current setting is 1 A. This pin has a
pull-down resistor of 450 KΩ.
6
SYNC
7
8
SS
Soft-Start. A capacitor connected between this pin and AGND can set soft-start time.
Compensation. Error amplifier output. Connect the external compensation network between
this pin and AGND.
COMP
9
FB
Output Voltage Feedback. Connect through a resistor divider to set the output voltage.
Analog Ground. Ground return for all internal control circuits.
10
AGND
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are
given with respect to the network ground terminal. Stress beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device.
Symbols
Parameter
Min.
Max.
Unit
VPVIN
VAVIN
VSW
PVIN (AGND=PGND)
AVIN (AGND=PGND)
-0.3
-0.3
-0.3
-0.3
-65
6.0
6.0
V
V
Switch Voltage, SW to GND
All other pins except COMP
Storage Temperature
VIN + 0.3 or 6.0
6.0
V
V
TSTG
TJ
+150
°C
°C
Junction Temperature
-40
+125
Human Body Model,
JESD22-A114
2.0
2.5
ESD
Electrostatic Discharge Protection
kV
Charged Device Model,
JESD22-C101
Note:
2. COMP pin has an internal clamp to 1.5 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VIN
Parameter
Min.
2.5
Max.
5.5
Unit
V
Supply Voltage
Ambient Operating Temperature
TA
-40
+85
°C
Thermal Information
Symbol
Parameter
Min.
-65
Typ.
Max.
+150
+300
Units
TSTG
TL
Storage Temperature
°C
°C
Lead Soldering Temperature, 30 Seconds
Thermal Resistance: Junction-to-Ambient
Thermal Resistance: Junction-to-Case(3)
Total Power Dissipation in the package, TA=25°C(3)
49
8
°C/W
°C/W
W
θJA
θJc
PD
1.3
Note:
3. Typical thermal resistance when mounted on a four-layer PCB. Actual results are dependent upon mounting
method and surface related to the design.
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
3
Electrical Characteristics
VIN=5.0 V, VOUT=2.5 V, COUT=10 µF, CIN=10 µF, over operating range, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Basic Operation
VIN
IQ
VIN Operating Voltage
Quiescent Current
AVIN=PVIN
2.5
5.5
500
0.60
2.25
V
µA
µA
V
VEN=5 V, VSS=0 V
VEN=0 V
250
371
0.34
2.19
70
ISD
Shutdown Current
VUVLO
VIN Under-Voltage Lockout
Rising VIN
2.10
0.80
VUVLOHYS VIN Under-Voltage Lockout Hysteresis
mV
V
VENH
VENL
Enable High Input Voltage
Enable Low Input Voltage
1.70
1.22
200
300
200
300
1.2
2.00
V
VIN=5 V
RONPMOS PMOS On Resistance(4)
RONNMOS NMOS On Resistance(4)
mΩ
mΩ
A
VIN=3.3 V
VIN=5 V
VIN=3.3 V
VSYNC=0 V
P-Channel Current Limit
ILIM
VFB=0.7 V, VIN=5 V, 100% Duty Cycle
VSYNC=VIN
0.6
fOSC
VSYNC
fSYNC
tSYNC
Oscillator Frequency
TA=25°C
1.105
500
1.210
VIN/2
1.350
2000
MHz
V
SYNC Threshold
Rising Edge
VSYNC=Square Wave
VSYNC On Time
Sink/Source Current
Synchronization Frequency
Minimum SYNC Pulse Width
KHz
ns
100
45
30
60
µA
(4)
IAMP
Error Amplifier
GEA
700
1000
550
3
1400
µA/V
V/V
A/V
(4)
AVEA
GCS
Current Sense Gain(4)
Reference Voltage for Temperature
Co-efficient, see Figure 12
Measured at FB Pin
TA=25°C
VREF
1.181
1.205
1.229
V
IFB
ISS
FB Bias Current
TA=25°C
-0.10
-5.5
-0.06
-4.5
0
µA
µA
Soft-Start Current
-3.5
Protections
TOTP
Over-Temperature Threshold(4)
Over-Temperature Hysteresis
+165
+20
°C
°C
THYS
Note:
4. Guaranteed by design and characterization; not production tested.
© 2013 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN8060 • Rev. 1.0.1
4
Functional Block Diagram
AVIN
To Internal Supply
PVIN
SYNC
+
Current
Sense
-
450k
+
+
Oscillator
Slope
Compensation
EN
Enable
& Reference
Logic
&
Driver
SW
OTP
4uA
PWM
Vref
+
-
+
Pulse
Skip
SS
FB
+
GM
+
-
-
1.4V
PGND
Low Current
Detect
Short
Circuit
Protection
COMP
AGND
Figure 3. Functional Block Diagram
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
5
Operation Description
The FAN8060 is a step-down converter operating in
current-mode PWM architecture with a typical switching
frequency of 1.2 MHz. At the beginning of each clock
cycle, the P-channel transistor is turned on. The current
in the inductor ramps up and is sensed via an internal
circuit. The P-channel switch is turned off when the
sensed current causes the PWM comparator to trip,
which is when the output voltage is in regulation or
when the inductor current reaches the current limit (set
internally to 1.2 A, typically). After a minimum dead time
to prevent shoot-through current, the N-channel
transistor is turned on and the current ramps down. As
the clock cycle is completed, the N-channel switch is
turned off and the next clock cycle starts.
Soft Start
When the input voltage on AVIN exceeds the UVLO
threshold and EN is high, the circuit releases SS and
enables the PWM regulator. A capacitor connected to
the SS pin and AGND is charged by a 4 μA internal
current source, causing the voltage on the capacitor to
rise. When this voltage reaches 1.2 V, the output is in
regulation. The SS voltage continues to rise to AVIN.
The time for the output to reach regulation is given by
the following equation:
CSS (nF)
t(ms) =
(1)
(
4µA/1.2V
)
Output overload and short-circuit protection is active
during soft-start. When the part is disabled, SS pin is
pulled low internally.
Light Load Operation
As the output load reduces, the current in the inductor
during off time is sensed across the low side MOSFET.
When the current reverses direction, the low-side
MOSFET is turned off and the high-side MOSFET is not
turned on until the output is out of regulation.
Overload & Short-Circuit Protection
FAN8060 employs cycle-by-cycle current limiting, which
limits current by reducing duty cycle during overload. As
the load increases beyond the limit, the output voltage
starts to reduce, thereby reducing the FB voltage. When
the FB node is half the reference voltage and the
COMP node has reached maximum value, short-circuit
protection is detected. At that time, both the SS pin and
the COMP pin are pulled to ground until the inductor
current crosses zero. At that point, both SS and COMP
are released for the current to ramp up again. This
continues until the short-circuit condition is released.
100% Duty Cycle Operation
As the input voltage approaches the output voltage, the
controller starts to increase the duty cycle to maintain
output regulation until duty cycle reaches 85%. The
controller then transitions to a 100% duty cycle mode
over several cycles to support the load. When the
dropout condition is met, the converter turns the P-
channel high side continuously on. In this mode, the
output voltage is equal to the input voltage, minus the
voltage drop across the P-channel MOSFET.
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
6
Typical Performance Characteristics
VIN=5 V, VOUT=2.4 V, L=3.3 µH, CIN=10 µF, COUT=10 µF, fS=1.2 MHz, TA=25°C, unless otherwise noted.
EN(2V/div.)
VSW(2V/div.)
EN(2V/div.)
VSW(2V/div.)
VOUT(2V/div.)
VOUT(2V/div.)
IL((1A/div.)
IL((1A/div.)
[1ms/div.]
[1ms/div.]
Figure 4. EN Startup with 1 A Load
Figure 5. EN Turn off with 1 A Load
VSW(2V/div.)
VSW(2V/div.)
VOUT(2V/div.)
VOUT(2V/div.)
IL((1A/div.)
IL((1A/div.)
[500ns/div.]
[200ns/div.]
Figure 6. PWM Operation with 1 A Load
Figure 7. 2 MHz Sync Operation with 1 A Load
VOUT(10mV/div. AC coupled)
VSW(2V/div.)
VOUT(50mV/div. AC coupled)
IOUT(500mA/div.)
Slew rate : 2.5A/us
IL((1A/div.)
[500ns/div.]
[200µs/div.]
Figure 8. Load Transient Response(Step-up/down)
Figure 9. Output Voltage Ripple with 1 A Load
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
VIN=5 V, VOUT=2.4 V, L=3.3 µH, CIN=10 µF, COUT=10 µF, fS=1.2 MHz, TA=25°C, unless otherwise noted.
0.10
0.05
98
95
92
89
86
83
80
3.3VIN/2.4VO
3.3VIN/2.4VO
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
5VIN/2.4VO
5VIN/2.4VO
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
Load Current [A]
Load Current [A]
Figure 10. Normalized VOUT vs. Load Current
Figure 11. Efficiency vs. Load Current
4.00
2.00
0.00
-2.00
-4.00
-50
-25
0
25
50
75
100
Temperature [℃]
Temperature [℃]
Figure 12. Normalized VREF vs. Temperature
Figure 13. Normalized Oscillation Frequency
vs. Temperature
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
8
Applications Information
Refer to Figure 1 for reference designators.
Input Capacitor Selection
The input capacitor reduces the RMS current drawn
from the input and switching noise from the device. The
combined RMS current rating for the input capacitor
should be greater than the value calculated by the
following equation:
Output Voltage Setting
The output voltage of the FAN8060 can be set from
1.2 V to VIN by an external resistor divider, given by the
following equation:
IRMS = IOUTMAX ⋅( D − D2 )
R2
(5)
VOUT = 1.2(1+
)
(2)
R3
where:
where, VOUT equals the output voltage.
IRMS
= RMS current of the input capacitor; and
Inductor Selection
IOUTMAX = Maximum output current.
Typically, the inductor value is chosen based on ripple
current (∆IL), which is chosen between 10% and 35% of
the maximum DC load. Regulator designs that require
fast transient response use a higher ripple-current
setting, while regulator designs that require higher
efficiency keep ripple current on the low side and
operate at a lower switching frequency.
Small, high value, inexpensive, lower-ESR ceramic
capacitors are recommended; 10 µF ceramic
capacitors with X7R or X5R should be adequate for
1 A applications.
Loop Compensation
The loop is compensated using a feedback network
connected between COMP and AGND. Figure 14
For a given output voltage ripple requirement, L can be
calculated by the following equation:
shows
a Type-2 compensation network used to
stabilize the FAN8060.
VOUT ⋅(1− D)
L ≥
(3)
∆IL ⋅ fS
Vout
where;
R2
R3
D
=
=
=
Duty ratio (VO/VIN);
Switching frequency; and
Inductor ripple value, typically set to 10% -
VFB
-
fS
Ve
G
m
∆IL
R
C
C
+
35% of the maximum steady-state load current.
C
A
C
The inductor should have a low DCR to minimize the
conduction losses and maximize efficiency. Some
recommended inductors are suggested in Table 1:
Vref
Figure 14. Compensation Network
Table 1. Recommended Inductors (3.3 µH)
The goal of the compensation design is to shape the
frequency response of the converter to achieve high
DC gain and fast transient, while maintaining loop
stability. FAN8060 employs peak-current-mode control
for easy use and fast transient response. Current mode
control helps simplify the loop to a one-pole and one
zero system.
Size[mm2]
7x7x3
DCR
23 mΩ
60 mΩ
78 mΩ
130 mΩ
Part Number
SLF7032T-3R3
LTF5022T-3R3
VLCF4020T-3R3
VLF3012AT-3R3
Vendor
TDK
5x5x2
TDK
4x4x2
TDK
2.6x2.8x1.2
TDK
The DC gain of the voltage feedback loop is given by:
Output Capacitor Selection
VFB
AVDC = RL ⋅GCS ⋅ AVEA
⋅
(6)
The output capacitor is selected based on the needs of
the final application and its output ripple requirements.
A larger output capacitor value reduces the output
ripple voltage. The formula of output ripple ΔVOUT is:
VOUT
where:
AVDC = DC gain of the feedback loop;
RL = Load resistor value (VOUT/IOUT);
1
∆VOUT ≅ ∆I ESR +
(4)
L
8 ⋅COUT ⋅ fS
GCS = Current sense gain (3 A/V);
where COUT is the output capacitor.
AVEA = Error amplifier voltage gain (550 V/V); and
VFB = Feedback threshold voltage (1.2 V).
ESR is the equivalent series resistance of the output
capacitor.
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
9
The system pole is calculated by the equation:
1
If required, add the second compensation capacitor
(CA) to set the pole fP3 at the location of the ESR zero.
Determine (CA) value by the equation:
fP1
=
(7)
2π ⋅COUT ⋅ RL
COUT ⋅ ESR
CA
=
(14)
The system zero is due to the output capacitor and its
ESR. System zero is calculated by the equation:
RC
1
fz1
=
(8)
2π ⋅COUT ⋅ ESR
Design Example
Table 2 provides component values for delivering
various output voltages with loads up to 1 A with VIN at
5 V (±10% tolerance).
The output characteristics of the error (Gm) amplifier
are controlled by a series capacitor and resistor
network connected at the COMP pin to GND.
The pole is calculated by the following equation:
Table 2. Recommended Feedback and
Compensation Values (VIN=5 V)
GEA
fp2
=
(9)
2π ⋅CC ⋅ AVEA
VO
C4
L1
R2
R3
R1
C5
C2
where:
Short
Open
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
GEA = Error Amplifier Transconductance (1000 µA/V);
and
2.55 kΩ 10.2 kΩ
5.9 kΩ 11.8 kΩ
16.2 kΩ 15 kΩ
18.7 kΩ 10.7 kΩ
10 µF 3.3 µH
4.7 kΩ 1.5 nF 150 pF
CC = compensation capacitor.
Zero is due to the compensation capacitor (CC) and
resistor (RC) calculated by the following equation:
1
HI
INPUT
2.5 to 5.5V
fz2
=
EN
LO
PVIN
AVIN
(10)
2π ⋅CC ⋅ RC
SYNC
SS
OUTPUT
2.5V/1A
FAN8060
SW
where RC is compensation resistor.
L1
3.3µH
R2
16.2k
COMP
R1
4.7k
The system crossover frequency (fC), where the control
loop has unity gain, is recommended to be set at 1/10th
of switching frequency. Generally, higher fC means
faster response to load transients, but can result in
instability if not properly compensated.
FB
C3
10µF
C4
10µF
AGND
PGND
C1
C2
R3
15k
10nF 150pF
C5
1.5nF
Figure 15. Recommended Schematic (5 VIN to
2.5 VO)
The first step in compensation design is choosing the
compensation resistor (RC) to set the crossover
frequency by the following equation:
2π ⋅COUT ⋅ fC ⋅VOUT
GCS ⋅GEA ⋅VFB
RC
=
(11)
where VFB is reference voltage.
The next step is choosing the compensation capacitor
(CC) to achieve the desired phase margin. For
applications with typical inductor values, setting the
compensation zero, fZ2, to below one fourth of the
crossover frequency provides sufficient phase margin.
Determine the (CC) value by the following equation:
2
CC
=
(12)
π ⋅RC ⋅fC
Then determine if the second compensation capacitor
(CA) is required. It is required if the ESR zero of the
output capacitor is located at less than half of the
switching frequency.
fS
1
<
(13)
2π ⋅COUT ⋅ ESR
2
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
10
PCB Layout Recommendations
The switching power supply PCB layout needs careful
attention and is critical to achieving low losses and
clean and stable operation. Although each design is
different, below are some general recommendations for
a good PCB layout.
.
.
.
Keep the high-current traces and load connectors
as short and wide as possible. These traces
consist of VIN, GND, VOUT, and SW.
Place the input capacitor, the inductor, and the
output capacitor as close as possible to the IC
terminals.
Keep the loop area between SW node, inductor,
and output capacitors as small as possible;
minimizing ground loops to reduce EMI issues.
Figure 16. Recommended PCB Layout
.
.
Route high-dV/dt signals, such as SW node, away
from the error amplifier input/output pins.
Keep components connected to the FB and COMP
pins close to the pins.
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
www.fairchildsemi.com
11
10
6
A
2.25
2.20
2.00
0.55
0.78
3.0
B
0.10 C
2X
2.33
3.0
2X
1.55 2.00 3.10
0.23
0.02
0.50
0.10 C
0.20
0.25
TOP VIEW
0.80 MAX
0.10 C
1
5
D
LAND PATTERN RECOMMENDATION
0.08 C
SEATING PLANE
SIDE VIEW
C
0.05
0.00
NOTES:
0.30
0.20
A. CONFORMS TO JEDEC REGISTRATION
MO-229, VARIATION WEED-5
0.5
0.38
1
5
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009
PIN #1
IDENT
D. LAND PATTERN DIMENSIONS ARE
NOMINAL REFERENCE VALUES ONLY
E. DRAWING FILENAME: MKT-MLP10Brev2
1.60
1.50
3.10
2.90
10
6
0.45
0.35
2.0
2.30
2.20
M
M
0.10
0.05
C A B
C
3.10
2.90
BOTTOM VIEW
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