FAN8811 [ONSEMI]
High-Frequency, High Side and Low Side Gate Driver IC;
| 型号： | FAN8811 |
| 厂家： | 
ONSEMI |
| 描述： | High-Frequency, High Side and Low Side Gate Driver IC 栅 |
| 文件： | 总14页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAN8811
High-Frequency, High Side
and Low Side Gate Driver IC
The FAN8811 is high side and low side gate−drive IC designed for
high−voltage, high−speed, driving MOSFETs operating up to 80 V.
The FAN8811 integrates a driver IC and a bootstrap diode. The
driver IC features low delay time and matched PWM input
propagation delays, which further enhance the performance of the
part.
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The high speed dual gate drivers are designed to drive both the
high−side and low−side of N−Channel MOSFETs in a half bridge or
synchronous buck configuration. The floating high−side driver is
capable of operating with supply voltages of up to 80 V. In the dual
gate driver, the high side and low side each have independent inputs to
allow maximum flexibility of input control signals in the application.
WDFN10 4x4, 0.8P
CASE 511DU
The PWM input signal (high level) can be 3.3 V, 5 V or up to V
DD
logic input to cover all possible applications. The bootstrap diode for
the high−side driver bias supply is integrated in the chip. The
high−side driver is referenced to the switch node (HS) which is
typically the source pin of the high−side MOSFET and drain pin of the
MARKING DIAGRAM
low−side MOSFET. The low−side driver is referenced to V which is
SS
ZXYTT
typically ground. The functions contained are the input stages, UVLO
protection, level shift, bootstrap diode, and output driver stages.
FAN8811T
MPX
Features
• Drives two N−Channel MOSFETs in High & Low Side
• Integrated Bootstrap Diode for High Side Gate Drive
• Bootstrap Supply Voltage Range up to 100 V
• 3 A Source, 6 A Sink Output Current Capability
• Drives 1 nF Load with Typical Rise/Fall Times of 6 ns/4 ns
• TTL Compatible Input Thresholds
• Wide Supply Voltage Range 7.5 V to 16 V
(Absolute Maximum 18 V)
FAN8811T= Specific Device Code
Z
= Plant Code
X
Y
TT
MP
X
= 1−Digit Year Code
= 1−Digit Week Code
= 2−Digit Die Run Code
= Package Type
= Reel Package
• Fast Propagation Delay Times (Typ. 30 ns)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
• 2 ns Delay Matching (Typical)
• Under−Voltage Lockout (UVLO) Protection for Drive Voltage
• Operating Junction Temperature Range of −40°C to 125°C
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Power Supplies for Telecom and Datacom
• Half−Bridge and Full−Bridge Converters
• Synchronous−Buck Converters
• Two−Switch Forward Converters
• Class−D Audio Amplifiers
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
April, 2019 − Rev. 3
FAN8811/D
FAN8811
TYPICAL APPLICATIONS
L
VDC
Supply Voltage
VDD
L
O
A
D
COUT
RLGATE
LO
C
IN
HB
VSS
CHB
HO
LI
FAN8811
PWM
FEEDBACK
Controller
HS
NC
HI
NC
Figure 1. Application Schematic − Synchronous Buck Converter
VDC
SECONDARY
SIDE
CIRCUIT
RHGATE
NC
HI
NC
HS
FAN8811
PWM
Controller
HO
LI
CHB
ISOLATION
AND
FEEDBACK
VSS
LO
HB
RLGATE
VDD
C
IN
Figure 2. Application Schematic − Half Bridge Converter
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2
FAN8811
BLOCK DIAGRAM
1
7
VDD
2
3
HB
HO
UVLO
HI
LEVEL
SHIFT
4
HS
LO
8
LI
UVLO
10
9
5
VSS
NC
6
NC
Figure 3. Simplified Block Diagram
PIN CONNECTIONS
VDD
HB
LO
VSS
HO
FAN8811
LI
HS
NC
HI
NC
Figure 4. Pin Assignments − 10 Lead MLP (Top View)
Table 1. PIN DESCRIPTION
Pin No.
Pin Name
Description
Logic and low−side gate driver power supply voltage
High−side floating supply
1
2
V
DD
HB
3
HO
HS
NC
NC
HI
High−side driver output
4
High−voltage floating supply return
No Connection
5
6
No Connection
7
Logic input for High−side gate driver output
Logic input for Low−side gate driver output
Logic Ground
8
LI
9
V
SS
10
LO
Low−side driver output
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3
FAN8811
Table 2. MAXIMUM RATINGS
All voltage parameters are referenced to V , unless otherwise noted.
SS
Symbol
Parameter
Min.
Max.
Units
Low−Side and Logic Fixed Supply Voltage
−0.3
18
V
V
DD
HS
High−Side Floating Supply Offset Voltage(Note 1)
Repetitive Pulse (< 100 ns)(Note 2)
Low−Side Output Voltage, LO Pin
Repetitive Pulse (< 100 ns)(Note 2)
High−Side Floating Output Voltage, HO Pin
Repetitive Pulse (< 100 ns)(Note 2)
Logic Input Voltage
−1
−(24 – V
−0.3
100
100
V
V
V
V
V
V
V
V
)
DD
V
V
V
V
V
+ 0.3
DD
DD
HB
HB
DD
V
LO
−2
+ 0.3
+ 0.3
+ 0.3
+ 0.3
V
– 0.3
HS
V
HO
V
– 2
HS
−0.3
−0.3
−0.3
−55
V , V
LI
HI
High−Side Floating Supply Voltage
100
V
V
V
HB
V
HS
to V Supply Voltage
18
HB
V
– V
HS
HB
Operating Junction Temperature
150
°C
T ,
J
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The V negative voltage capability can be calculated using (V –V )−18 V base on V , due to its dependence on V voltage level.
HS
HB
HS
HB
DD
2. Verified at bench characterization.
Table 3. ESD AND MSL
Symbol
Parameters
Value
2000
1000
Unit.s
ESD
Electrostatic Discharge Capability
Human Body Model,per AEC Q100−002
Charged Device Model, AEC Q100−011
V
HBM
CDM
ESD
Table 4. THERMAL INFORMATION
Symbol
Parameters
Value
0.6
Unit.s
P
D
Power Dissipation (Note 3)
1S0P with thermal vias (Note 4)
1S2P with thermal vias (Note 5)
1S0P with thermal vias (Note 4)
1S2P with thermal vias (Note 5)
W
2.4
q
Thermal Resistance Junction−Air
163
41
°C/W
JA
3. JEDEC standard: JESD51−2, JESD51−3. Mounted on 76.2 x 114.3 x1.6 mm PCB (FR−4 glass epoxy material)
4. 1S0P with thermal via: one signal layer with zero power plane and thermal via
5. 1S2P with thermal via: one signal layer with two power planes and thermal via
Table 5. RECOMMENDED OPERATING RANGES
All voltage parameters are referenced to V
SS
Symbol
Parameters
Supply Voltage
Test Condition
Min.
7.5
Max.
16
Units
V
V
DD
V
HS
DC
High Side Floating Return
DC
Repetitive Pulse (< 100 ns)
DC
−1
80
V
−(24 – V
)
100
V
DD
V
HB
Voltage on HB
V
+ 7.5
V + 16
HS
V
HS
dV /dt
Voltage Slew Rate on SW
Operating Temperature
50
125
V/ns
°C
SW
T
J
−40
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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FAN8811
Table 6. ELECTRICAL CHARACTERISTICS
V
DD
= V = 12 V, V = V = 0 V, T = T = −40°C to 125°C, no load on HO or LO, unless otherwise noted.
HB HS SS A J
Symbol
Power Supply Section
Parameters
Test Condition
Min.
Typ.
Max.
Units
I
V
Quiescent Current
Operating Current
V
= 0 V; V = 0 V
0.17
1.5
0.1
1.9
0
0.3
3.0
0.2
3.0
10
mA
mA
mA
mA
mA
mA
V
DD
DD
DD
HI
LI
I
I
V
f
= 500 kHz
DDO
SW
I
HB Quiescent Current
HB Operating Current
V
HI
= 0 V; V = 0 V
HB
LI
f
= 500 kHz
HBO
SW
I
HB to V Quiescent Current
V
HS
= V = 80 V
HBS
SS
HB
I
HB to V Operating Current
f
= 500 kHz
V Rising
DD
0.3
6.8
0.6
6.3
0.4
1.0
7.4
HBSO
SS
SW
V
V
UVLO Threshold
UVLO Hysteresis
6.2
5.5
DDR
DDH
HBR
HBH
DD
DD
V
V
V
V
V
HB UVLO Threshold
HB UVLO Hysteresis
HB Rising
7.2
V
V
Input Logic Section
V
High Level Input Voltage Threshold
Low Level Input Voltage Threshold
Input Logic Voltage Hysteresis
Input Pull−down Resistance
1.80
1.3
2.2
1.7
0.5
100
2.50
2.0
V
V
IH
V
IL
V
IHYS
V
R
kW
IN
Bootstrap Diode
V
Forward Voltage @ Low Current
Forward Voltage @ High Current
Dynamic Resistance
I
I
I
−
= 100 mA
= 100 mA
= 100 mA
0.55
0.8
0.7
20
0.8
1.0
1.5
V
V
FL
VDD HB
V
FH
−
VDD HB
R
−
VDD HB
W
ns
D
t
BS
(Note 6)
Diode Turn−off Time
I = 20 mA, I
F
= 0.5 A
REV
Low Side Driver
V
Low Level Output Voltage
High Level Output Voltage
Peak Pull−up Current
Peak Pull−down Current
LO Rise Time
I
I
= 100 mA
0.06
0.16
3
0.15
0.28
V
V
OLL
OHL
LO
V
= −100 mA, V
= V − V
LO
OHL DD LO
I
(Note 6)
(Note 6)
V
V
= 0 V
A
OHL
LO
LO
I
= 12 V
6
A
OLL
t
10% to 90%, C
= 1 nF
= 1 nF
6
ns
ns
ns
ns
ns
ns
R_LO
LOAD
LOAD
t
LO Fall Time
90% to 10%, C
4
F_LO
t
LO Rise Time
3 V to 9 V, C
9 V to 3 V, C
= 100 nF
= 100 nF
300
140
28
30
500
300
43
R_LO1
LOAD
t
LO Fall Time
F_LO1
LOAD
t
t
LI = Low Propagation Delay
LI = High Propagation Delay
V
V
Falling to V Falling, C
= 0
LPHL
LPLH
LI
LI
LO
LOAD
Rising to V Rising, C
= 0
45
LO
LOAD
High Side Driver
V
Low Level Output Voltage
High Level Output Voltage
Peak Pull−up Current
Peak Pull−down Current
HO Rise Time
I
I
= 100 mA
0.06
0.16
3
0.15
0.28
V
V
OLH
OHH
HO
V
= −100 mA, V
= V − V
HO
OHH HB HO
I
(Note 6)
(Note 6)
V
V
= 0 V
A
OHH
HO
HO
I
= 12 V
6
A
OLH
t
10% to 90%, C
90% to 10%, C
= 1 nF
6
ns
ns
ns
ns
ns
ns
R_HO
F_HO
LOAD
t
HO Fall Time
= 1 nF
4
LOAD
t
HO Rise Time
3 V to 9 V, C
= 100 nF
= 100 nF
300
140
28
30
500
300
43
R_HO1
LOAD
LOAD
t
HO Fall Time
9 V to 3 V, C
F_HO1
t
t
HI = Low Propagation Delay
HI = High Propagation Delay
V
V
Falling to V Falling, C
= 0
HPHL
HI
HO
LOAD
Rising to V Rising, C
= 0
45
HPLH
HI
HO
LOAD
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FAN8811
Table 6. ELECTRICAL CHARACTERISTICS
V
DD
= V = 12 V, V = V = 0 V, T = T = −40°C to 125°C, no load on HO or LO, unless otherwise noted.
HB HS SS A J
Symbol
Delay Matching
Parameters
Test Condition
Min.
Typ.
Max.
Units
t
HI Turn−OFF to LI Turn−ON
LI Turn−OFF to HI Turn−ON
2
2
10
10
ns
ns
MON
t
MOFF
Minimum Pulse Width
t
Minimum Pulse Width for HI and LI
(Note 6)
50
ns
PW
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. These parameters are guaranteed by design.
TYPICAL CHARACTERISTICS
Typical characteristics are provided at 25°C and V
HB
DD,
V
= 12 V unless otherwise noted.
0.25
0.25
0.2
0.2
0.15
0.1
0.15
0.1
IDD
IHB
0.05
0
0.05
0
IDD
IHB
7
8
9
10
11
12
13
14
15
16
17
18
-50℃
0℃
50℃
100℃
150℃
VDD (VHB) VOLTAGE [V]
TEMPERATURE [ ℃]
Figure 6. Quiescent Current vs. VDD (VHB
)
Figure 5. Quiescent Current vs. Temperature
2.5
2
100
10
1.5
1
1
0pF
0.5
0
IDDO
IHBO
1000pF
2200pF
3300pF
0.1
-50℃
0℃
50℃
100℃
150℃
10
100
1000
TEMPERATURE [℃]
FREQUENCY [kHz]
Figure 7. Operating Current vs. Temperature
Figure 8. IDD Operating Current vs. Frequency
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FAN8811
100
10
1
3
2.5
2
1.5
1
0pF
VIH
VIL
1000pF
2200pF
3300pF
0.5
0.1
-50℃
0℃
50℃
100℃
150℃
10
100
1000
TEMPERATURE [ ℃]
FREQUENCY [kHz]
Figure 10. Input Threshold vs. Temperature
Figure 9. IHB Operating Current vs. Frequency
3
7
6.8
6.6
6.4
6.2
6
2.5
2
1.5
1
5.8
5.6
5.4
5.2
5
VIH
VIL
VDDR
VDDF
0.5
7
8
9
10
11
12
13
14
15
16
17
18
-50℃
0℃
50℃
100℃
150℃
VDD VOLTAGE [V]
TEMPERATURE [ ℃]
Figure 12. VDD UVLO Threshold vs. Temperature
Figure 11. Input Threshold vs. VDD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
0.2
VFL
VHBR
VHBF
0.1
VFH
0
-50℃
0℃
50℃
100℃
150℃
-50℃
0℃
50℃
100℃
150℃
TEMPERATURE [ ℃]
TEMPERATURE [ ℃]
Figure 14. Bootstrap Diode VF vs. Temperature
Figure 13. VHB UVLO Threshold vs. Temperature
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FAN8811
0.25
0.2
0.25
VOL
VOH
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
VOL
VOH
-50℃
0℃
50℃
100℃
150℃
7
8
9
10
11
12
13
14
15
16
17
18
TEMPERAUTRE [ ℃]
VDD VOLTAGE [V]
Figure 15. VOH, VOL Voltage vs. Temperature
Figure 16. VOH, VOL Voltage vs. VDD (VHB
)
40
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
High Prop delay
Low Prop delay
High Prop Delay
Low Prop Delay
0
0
-50℃
0℃
50℃
100℃
150℃
-50℃
0℃
50℃
100℃
150℃
TEMPERATURE [℃]
TEMPERATURE [ ℃]
Figure 18. High Side Propagation Delay vs.
Temperature
Figure 17. Low Side Propagation Delay vs.
Temperature
50
50
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
High Prop Delay
Low Prop Delay
High Prop Delay
Low Prop Delay
0
0
7
8
9
10
11
12
13
14
15
16
17
18
7
8
9
10
11
12
13
14
15
16
17
18
VDD VOLTAGE [V]
VDD VOLTAGE [V]
Figure 20. High Side Propagation Delay vs. VHB
Figure 19. Low Side Propagation Delay vs. VDD
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FAN8811
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
7
8
9
10
11
12
13
14
15
16
7
8
9
10
11
12
13
14
15
16
SUPPLY VOLTAGE [V]
SUPPLY VOLTAGE [V]
Figure 21. HO, LO Peak Source Current vs. Supply
Voltage
Figure 22. HO, LO Peak Sink Current vs. Supply
Voltage
Switching Time Definitions
Figure 23 shows the switching time waveforms
definitions of the turn on and off propagation delay times.
LIN
HIN
HIN
50%
50%
(LIN)
tHPLH
tLPLH
tHPHL
tLPHL
90%
90%
LO
HO
50%
50%
10%
HO
(LO)
10%
tR
tF
tMON
tMOFF
Figure 23. Timing Diagrams
Input to Output Definitions
Figure 24 shows an input to output timing diagram for
overall operation.
VDD UVLO period
VDD
VDD UVLO threshold voltage : Typ. 6.8 V
VDD UVLO Hysteresis
HB UVLO period
HB UVLO threshold voltage : Typ. 6.3 V
HB
VDD UVLO Hysteresis
PWM Input Threshold
PWM Input Threshold
HI
LI
HO
LO
Figure 24. Overall Operation Timing Diagram
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FAN8811
APPLICATIONS INFORMATION
The FAN8811 is designed to drive high side and the low
differential voltage is below the specified threshold. The HB
UVLO rise threshold is 6.3 V with 0.4 V hysteresis.
side N−channel power MOSFETs in a half bridge or
synchronous buck. The driver IC integrates a bootstrap
diode for the high side driver bias supply. High side and Low
side outputs are independently controlled by each of input
control signals with TTL or logic compatibility. The floating
high side driver can operate with supply voltage up to 80 V.
The FAN8811 functions consist of the input stage, level
shift, bootstrap diode, Under−Voltage Lockout (UVLO)
protection and output stage. The UVLO function is included
in both the high−and low side.
Output Stage
The FAN8811 output stage is able to Sink/Source
3.0 A /6.0 A typical which can effectively charge and
discharge a 1 nF load in few ns. High speed switching, low
resistance and high current capability of both high side and
low side drivers allow for efficient switching operation. The
low side driver is referenced from V to V and the high
DD
SS
side is referenced from HB to HS. The device logic status
shows as below.
Input Stage
Table 7. DEVICE LOGIC STATUS
The input pins (HI,LI) of gate driver devices are based on
a TTL compatible input threshold logic that is independent
HI
LI
HO
LO
of the V
supply voltage. The PWM input signal (high
DD
L
L
L
L
level) can be 3.3 V, 5 V or up to VDD logic input to
accommodate all possible applications. The input
impedance of the FAN8811 is 100 kW nominal. The 100 kW
is a pull−down resistance to ground (GND). The logic level
compatible input provides a 2.2 V rising threshold and a
1.7 V falling threshold.
L
H
H
X
H
L
L
H
H
L
H
L
Status
H
X
H
L
Level Shift
Select Bootstrap Capacitor
The level shift circuit is the interface from the high side
input to the high side driver stage which is referenced to the
switch node (HS). The level shift allows control of the HO
output referenced to the HS pin and provides excellent delay
matching with the low side driver.
To control the high side output drive utilizes a widely used
technique for high side level shifter circuit so−called pulsed
latch level translators.
The maximum allowable voltage drop across the
bootstrap capacitor to ensure enough gate−source voltage is
highly dependent to the internal under−voltage Lockout
level of the gate drive IC, and the voltage level at the source
connection of switching node HS. The maximum allowable
drop voltage can be obtained by (eq.1)
DVHB + VDD * Vf * VHB,UVLO
(eq. 1)
Where:
Bootstrap Diode
• V : Gate drive IC supply voltage
DD
The FAN8811 integrates a high voltage bootstrap diode to
generate the high side bias. It is provided to charge high side
gate drive bootstrap capacitor. The diode anode is connected
• V : Static forward voltage drop of bootstrap diode
f
• V
: HB Under−Voltage Lockout level
HB,UVLO
to V and cathode connected to HB. The boot capacitor
DD
The total charge (Q ) required by the bootstrap capacitor
can be calculated by summing the Q of the MOSFET and
the charge required for the level shifter in the gate drive IC
which is negligible quantity to compared Q of the
bs
should be connected externally to HB and the HS pins, the
HB capacitor charge is refreshed every switching cycle
when HS transitions to Ground. The bootstrap diode
provides fast recovery times, and a low resistance value of
0.7 W typ.
g
g
MOSFET.
QBS + Qg ) (IHBS TON
)
(eq. 2)
Under−Voltage Lockout (UVLO)
Both high side and low side drivers have independent
Where:
UVLO protections which monitor the V supply voltage
DD
• Q : Total gate charge of bootstrap capacitor
BS
and HB bootstrap voltage. The function of the UVLO
circuits is to ensure that there is enough supply voltages
• Q : Gate charge of the MOSFET
g
• I : Quiescent current in High side gate drive IC.
HBS
(V
and HB) to correctly bias high side and low side
DD
• T : Turning on of MOSFET
ON
circuits. This also ensures that the gate of external
MOSFETs are driven at an optimum voltage. The V
DD
The guiding criteria for calculating the minimum required
bootstrap capacitance can be obtained through (eq.4).
UVLO disables both high side and low side drivers when
is below the specified threshold. The rise V
V
DD
DD
QBS
DVHB
threshold is 6.8 V with 0.6 V hysteresis. The HB UVLO
disables only the high side driver when the HB to HS
C
BOOT.MIN w
(eq. 3)
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FAN8811
Select External Bootstrap Series Resistor
V
DD * Vf * VOHH
IOHH
IOLH
IOHL
IOLL
+
+
+
+
The FAN8811 utilizes high speed gate driving for
synchronous buck and half bridge applications. In these
applications, voltage ringing can be generated by parasitic
inductance of the primary power path, consisting of the input
Rgate
V
V
DD * Vf * VOLH
Rgate
capacitor and switching MOSFETs (C ).
oss
DD * VOHL
To reduce this ringing phenomenon, the first step is to
optimize the PCB layout to reduce parasitic components of
the power path. The second step is to add a series resistor
with the bootstrap capacitor to slow down the turn−on
transition of the high side MOSFET.
Rgate
V
DD * VOLL
(eq. 5)
Rgate
Where:
• I
• I
• I
: High side peak source current
: High side peak sink current
: Low side peak source current
OHH
Bias Supply
Input
Supply
OLH
OHL
HB
HO
RB
Bootstrap
Diode
LHS− D
• I : Low side peak sink current
OLL
CIN
• V : Bootstrap diode forward voltage drop
f
HS
Driver
• V
• V
• V
: High level output voltage drop (high side)
OHH
LHS− S
L
LCIN
HS
LS
: Low level output voltage drop (high side)
: High level output voltage drop (low side)
OLH
LHS− D
COSS
OHL
L
O
A
D
LS
Driver
• V : Low level output voltage drop (low side)
VOUT
OLL
LHS− S
GND
Gate Driver Power Dissipation
The total power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver losses
are:
Figure 25. Application Circuit with Parasitic
Components
• The static and dynamic losses related to the switching
frequency
Figure 25 shows the synchronous buck with the parasitic
component at the power path. Each of parasitic inductance
• Output load capacitance losses on high and low side
drivers
and low side C
of MOSFET made up the ringing
OSS
• Internal consumption supply voltage, V
phenomenon at the HS node, when the high side turns on.
DD
When the bootstrap series resistor R installed with
The static losses are due to the quiescent current from the
B
bootstrap capacitor, the bootstrap resistor limits the current
available to charge the gate of the high side MOSFET,
increasing the time needed to turn the high side MOSFET
on. The increased switching time slows the HS node rate of
rising and can have a significant impact on the peak voltage
on the HS node.
voltage supplies V and ground in low side driver and the
DD
leakage current in the level shifting stage in high side driver,
which are dependent on the voltage supplied on the HS pin
and proportional to the duty cycle when only the high side
power device is turned on. The quiescent current is
consumed by the device through all internal circuits such as
input stage, reference voltage, logic circuits, protections,
and also any current associated with switching of internal
devices when the driver output changes state. The effect of
the static losses within the gate driver can be safely assumed
to be negligible thanks to the FAN8811 low 0.17 mA
quiescent current.
We recommend selecting less than 10 W for R .
B
VDD * Vf
IBOOT(PEAK)
+
(eq. 4)
RB
Select Gate Resistor
The gate resistor is also sized to reduce a ringing voltage
of the HS node by parasitic inductances and capacitances.
But, it limits the current capability of the gate driver output
by the resistance value. The limited current capability value
by the gate resistor can be obtained (eq.5).
The dynamic losses are defined as follows: In the low side
driver, the dynamic losses are due to two different sources.
One is due to whenever a load capacitor is charged or
discharged through a gate resistor, half of the energy that
www.onsemi.com
11
FAN8811
goes into the capacitance is dissipated in the resistor. The
• The gate driver should be located as close as possible of
losses in the gate driver resistance, internal and external to
the gate driver, and the switching losses of the internal
CMOS circuitry. The dynamic losses of the high side driver
also have two different sources. One is due to the level
shifting circuit and one due to the charging and discharging
of the capacitance of the high side. The static losses are
neglected here because the total IC power dissipation is
mainly dynamic losses of gate drive IC and can be estimated
as:
switching MOSFET.
• The V capacitor and bootstrap capacitor should be
DD
located as near as possible to the device.
• In order to reduce a ringing voltage of the HS node, the
space between high side source and low side drain of
the MOSFET should be as small as possible.
• The exposed pad should be connected to GND plane
and use at least four or more vias for improved thermal
performance.
P
DGATE + 2 CL fS VDD2[W]
• Avoid driver input pulse signal close to the HS node.
(eq. 6)
The bootstrap circuit power dissipation is the sum of the
bootstrap diode losses and the bootstrap resistor losses if any
exist. The bootstrap diode loss is the sum of the forward bias
power loss that occurs while charging the bootstrap
capacitor and the reverse bias power loss that occurs during
reverse recovery. Since each of these events happens once
per cycle, the diode power loss is proportional to switching
frequency. Larger capacitive loads require more current to
recharge the bootstrap capacitor, resulting in more losses.
One of recommendation layout pattern for the driver is
shown in Figure 26.
PCB Layout Guideline
FAN8811 is a high speed and high current high side and
low side driver. To avoid any device malfunction during
device operation, it is very important that there is very low
parasitic inductance in the current switching path. It is very
important that the best layout practices are followed for the
PCB layout of the FAN8811. The following should be
considered before beginning a PCB layout using the
FAN8811.
Figure 26. Layout Recommendation
ORDERING INFORMATION
†
Device
Output Configuration
Temperature Range (5C)
−40 to 125
Package
Shipping
FAN8811TMPX
High−Side and Low−Side
WDFN10 4x4, 0.8P
Tape & Reel
(Pin 1 upper left near
sprocket holes)
(Pb−Free)
FAN8811MNTXG
High−Side and Low−Side
−40 to 125
WDFN10 4x4, 0.8P
Tape & Reel
(Pin 1 upper right near
sprocket holes)
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN10 4x4, 0.8P
CASE 511DU
ISSUE O
DATE 28 FEB 2017
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WDFN10 4x4, 0.8P
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