FAN9673QX [ONSEMI]
Three-Channel Interleaved CCM PFC Controller;
| 型号： | FAN9673QX |
| 厂家： | 
ONSEMI |
| 描述： | Three-Channel Interleaved CCM PFC Controller 功率因数校正 |
| 文件： | 总26页 (文件大小：2044K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAN9673
Three-Channel Interleaved
CCM PFC Controller
Description
The FAN9673 is an interleaved three−channel Continuous
Conduction Mode (CCM) Power Factor Correction (PFC) controller
IC intended for PFC pre−regulators. Incorporating circuits for the
implementation of leading edge, average current, and “boost”−type
power factor correction, the FAN9673 enables the design of a power
supply that fully complies with the IEC1000−3−2 specification.
Interleaved operation provides substantial reduction in the input and
output ripple currents and the conducted EMI filtering becomes easier
and cost effective.
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An innovative channel management function allows slave channels
to be loaded and unloaded smoothly in lower power−level conditions
according to setting voltage on the CM pin, improving the PFC
converter’s load transient response.
LQFP32
CASE 561AB
The FAN9673 also incorporates a variety of protection functions,
including: peak current limiting, input voltage brownout protection,
and TriFault Detect function.
MARKING DIAGRAM
Features
24 23 22 21 20 19 18 17
• Continuous Conduction Mode Control
• Three−Channel PFC Control (Maximum)
• Average Current−Mode Control
• PFC Slave Channel Management Function
• Programmable Operation Frequency Range: 18 kHz ∼ 40 kHz
or 55 kHz ∼ 75 kHz
VIR
OPFC3
OPFC2
CM3
CM2
CM1
IEA3
IEA2
IEA1
RDY
OPFC1
VDD
FBPFC
VEA
ON
ZXYTT
F A N 9 6 7 3
TM
• Programmable PFC Output Voltage
• Dual Current Limit Functions
• TriFault Detect Protects Against Feedback Loop Failure
• Sag Protection
SS
IAC
1
2
3
4
5
6
7
8
• Programmable Soft−Start
• Under−Voltage Lockout (UVLO)
• Differential Current Sensing
Z
X
Y
TT
T
= Assembly Plant Code
= Year Code
= Work Code
= Die Run Code
= Package Type (Q:LQFP)
= Manufacture Flow Code
• Available in 32−Pin LQFP Package
Typical Applications
M
• High Power AC−DC Power Supply
• DC Motor Power Supply
• White Goods; e.g. Air Conditioner Power Supply
• Server and Telecom Power Supply
• Industrial Welding and Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
June, 2019 − Rev. 7
FAN9673/D
FAN9673
ORDERING INFORMATION
Operating
Temperature Range
Part Number
FAN9673Q
Package
Packing Method
Tray
−40°C to 105°C
32LD, LQFP, JEDEC MS−026, Variation BBA, 7 mm
Square
FAN9673QX
Tape & Reel
TYPICAL APPLICATION
* DBP
RB1
VIN
LPFC1
LPFC2
LPFC3
DPFC1
DPFC2
DPFC3
VPFC
CB+
RFB1
COUT
AC Line
In
EMI
Filter
RFB2
SPFC1
SPFC2
SPFC3
RB1
RA1
RSEN1
RSEN2
RSEN3
CFB3
RFB3
RB2
RA2
RF
CF1
CF2
RB3
OPFC1 CS1+ CS1− OPFC2 CS2+
CS2− OPFC3
CS3+
CS3−
IAC
FBPFC
CVC2
RVC1
BIBO
SS
VEA
IEA1
IEA2
CSS
CVC1
CB1
CB2
RB4
CIC12
CVI22
CIC32
CILIMIT2
RILIMIT2
ILIMIT2
RIC1
RIC2
RIC3
CIC11
CIC21
CIC31
FAN9673
RDY
PVO
MCU
MCU signal(DC)
IEA3
LS
RLS
CGC
RGC
VDD
VIR
GC
CVDD
LPK
CM1
CM2
CM3
GND
RLPK
RRLPK
RI
ILIMIT
Standby Power
RRI
RILIMIT
MCU
RVIR
CVIR
RLPK
Channel Enable
CILIMIT
CLPK
CRLPK
* About D please reference System Design Precautions
BP
Figure 1. Typical Application Diagram for Three−Channel PFC Converter
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2
FAN9673
BLOCK DIAGRAM
ILIMIT
3
ILIMIT2
7
VDD
28
VIR
16
SS
31
FBPFC
29
SS
PVO
VEA
2
10uA
20uA
Brown Out,
Protection
GMV
V
VIR
V
VIR
< 1.5V, FR
> 3.5V, HV
VDD
1.2V / RRI
30
VDD OVP
24V/23V
60uA
2.5V
1/4X
0.3V
VVEA
B
VEA
VEA LPD
PFC UVP
0.5V
C
A
VVEA > VSS
Peak Detector
VFBPFC
LPK
RLPK
IAC
8
6
RM
2.75V/2.5V
PFC OVP
AC UVP
Imo
Ratio
V
ꢀ
V
B
I
B
O
−
U
V
P
−
B
I
B
O
−
U
V
P
VBIBO
32
10
ILIMIT2
CS1
S SET
RCLR
Q
IEA1
Q
27
OPFC1
OPFC2
GMI1
GMI2
GMI3
CM1
S SET
RCLR
Q
Q
CS1+ 23
LPT1
LPT2
LPT3
CS1− 22
IEA_SAW1
Dead1
ILIMIT2
CS2
S SET
RCLR
S SET
RCLR
Q
Q
11
IEA2
26
CM2
Q
Q
CS2+ 21
CS2− 20
IEA_SAW2
Dead2
S SET
RCLR
S SET
RCLR
Q
Q
ILIMIT2
CS3
IEA3
12
25
OPFC3
RDY
CM3
Q
Q
CS3+ 19
5V
CS3− 18
IEA_SAW3
Dead3
LS
17
4
VDD
UVLO
VGMV−
9
Brown In /Out
FR: 1.05V/1.9V
HV: 1.05V/1.75V
Oscillator
GC
Brown out
FR: 2.4V/1.25V
HV: 2.4/1.55V
55uA
55uA 55uA
1
5
13
14
15
24
GND
BIBO
RI
CM1 CM2 CM3
* FR: Full Range AC Input, AC85 V~264 V
HV: High Voltage Range AC Input, AC180 ~ 264 V
Figure 2. Functional Block Diagram
PIN CONFIGURATION
24
23
22
21
20
19
18
17
VIR
OPFC3
OPFC2
CM3
CM2
OPFC1
VDD
FBPFC
VEA
ON
ZXYTT
CM1
IEA3
IEA2
IEA1
RDY
F A N 9 6 7 3
TM
SS
IAC
1
2
3
4
5
6
7
8
Figure 3. Pin Layout (Top View)
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FAN9673
Table 1. PIN DEFINITIONS
Pin #
Name
BIBO
PVO
Description
1
2
Brown In/Out Level Setting: This pin is used for brown in/out setting.
Programmable Output Voltage: DC voltage from a microcontroller (MCU) can be applied to this pin to
program the output voltage level. The operation range is 3.5 V ∼ 0.5 V. If V < 0.5 V, the PVO function
PO
is disabled.
3
4
5
6
7
ILIMIT
GC
Current Command Clamp Setting: Average current mode is to control average value of inductor current
by a current command. Connecting a resistor and a capacitor to this pin can determine a limit value of
the current command.
Input Voltage Gain Control: Connecting a resistor on this pin to set a gain on the input−voltage signal to
match FBPFC. The signal here is used for the LPT function. A small capacitor connecting from GC to
GND is recommended for noise filtering.
RI
Oscillator Setting: There are two oscillator frequency ranges: 18 ∼ 40 kHz and 50 ∼ 75 kHz. A resistor
connected from RI to ground determines the switching frequency. A resistor value between
10.6 k ∼44.4 kꢁ is recommended.
RLPK
ILIMIT2
Ratio of V
LPK
mined by the tolerance of R
and V : Connect a resistor and a capacitor to this pin to adjust the ratio of V peak to
LPK
IN
IN
V
. Typical value is 12.4 kꢁ (1:100 of V
and V peak). The accuracy of V
is primarily deter-
LPK
IN
LPK
at this pin.
RLPK
Peak Current Limit Setting: Connect a resistor and a capacitor to this pin to set the over−current limit
threshold and to protect power devices from damage due to inductor saturation. This pin sets the over−
current threshold for cycle−by−cycle current limit.
8
9
LPK
Peak of Line Voltage: This pin can be used to provide information about the peak amplitude od the line
voltage to an MCU.
RDY
Output Ready Signal: When the feedback voltage on FBPFC exceeds 2.4 V, the RDY pin outputs a
high−state V
signal to inform the MCU the downstream power stage can start normal operation.
RDY
If AC brownout is detected, the V
signal is LOW to signal the MCU the PFC is not ready.
RDY
10
11
12
13
IEA1
IEA2
IEA3
CM1
Output 1 of PFC Current Amplifier: The signal from this pin is compared with an internal sawtooth sig-
nal to determine the pulse width for PFC gate drive 1.
Output 2 of PFC Current Amplifier: The signal from this pin is compared with an internal sawtooth sig-
nal to determine the pulse width for PFC gate drive 2.
Output 3 of PFC Current Amplifier: The signal from this pin is compared with an internal sawtooth sig-
nal to determine the pulse width for PFC gate drive 3.
Channel 1 Management Setting: This pin is used to configure the characteristics of PFC enable/
disable. Pull voltage on this pin LOW (= 0 V) to enable and HIGH (> 4 V) to disable the whole PFC
system.
14
CM2
Channel 2 Management Setting: There are two control methods for channel 2. The first uses an exter-
nal signal to enable/disable channel 2 (V
= 0 V/V
4 V). The second is linear increase/de-
CM2
CM2 >
crease loading of channel 2 when V
, proportional to power level, meets the setting level on V
.
CM2
VEA
15
16
CM3
VIR
Channel 3 Management Setting: Same as the CM2 pin, but for Channel 3.
Input Voltage Range Setting: A capacitor and a resistor are connected in parallel from this pin to GND.
When V
> 3.5 V, the PFC controller only works for the high−voltage input range (180 V ∼264 V
)
VIR
IAC
AC
AC
and R
must be 12 Mꢁ. When V
< 1.5 V, the PFC controller works for the Universal Input voltage
VIR
range (90 V ∼264 V ) and R must be 6 Mꢁ. Voltage between 1.5 V and 3.5 V is not allowed.
AC
AC
IAC
17
LS
Setting for Current Predict Function: A resistor, connected from this pin to ground, is used to adjust the
compensation of linear predict function (LPT). A small capacitor connected from this pin to GND is
recommended for noise filtering.
18
19
20
21
22
23
24
25
CS3−
CS3+
CS2−
CS2+
CS1−
CS1+
GND
Channel 3 Negative PFC Current Sense Input
Channel 3 Positive PFC Current Sense Input
Channel 2 Negative PFC Current Sense Input
Channel 2 Positive PFC Current Sense Input
Channel 1 Negative PFC Current Sense Input
Channel 1 Positive PFC Current Sense Input
Ground Reference and Return
OPFC3
Channel 3 PFC Gate Drive: The totem−pole output drive for the MOSFET or IGBT. This pin has an
internal 15 V clamp to protect the external power switch.
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4
FAN9673
Table 1. PIN DEFINITIONS (continued)
Pin #
Name
Description
26
OPFC2
Channel 2 PFC Gate Drive: The totem−pole output drive for the MOSFET or IGBT. This pin has an
internal 15 V clamp to protect the external power switch.
27
28
29
30
31
32
OPFC1
VDD
FBPFC
VEA
Channel 1 PFC Gate Drive: The totem−pole output drive for the MOSFET or IGBT. This pin has an
internal 15 V clamp to protect the external power switch.
External Bias Supply for the IC: The typical turn−on and turn−off threshold voltages are 12.8 V and
10.8 V respectively.
Voltage Feedback Input for PFC: Inverting input of the PFC error amplifier. This pin is connected to the
PFC output through a resistor−divider network.
Output of PFC Voltage−Loop Amplifier: An error−amplifier output for the PFC voltage feedback loop.
A compensation network is connected between this pin and ground.
SS
Soft−Start: Connect a capacitor to this pin to set the soft−start time. Pulling this pin to ground can dis-
able the gate drive outputs OPFC1, OPFC2 and OPFC3.
IAC
Input AC Current: During normal operation, this input provides a current reference for an internal gain
modulator. The recommended maximum current on IAC is 65 ꢂ A.
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Min
Max
Unit
V
V
DD
DC Supply Voltage
30
V
Voltage on OPFC1, OPFC2, OPFC3 Pins
−0.3
−0.3
V
DD
+ 0.3 V
V
OPFC
V
L
Voltage on IAC, BIBO, LPK RLPK, FBPFC, VEA, CS1+, CS2+, CS3+,
CS1−, CS2−, CS3−, CM1, CM2, CM3, ILIMIT, ILIMIT2, RI, PVO, GC, LS,
VIR Pins
7.0
V
V
Voltage on IEA1, IEA2, IEA3, SS Pins
Input AC Current
0
8
1
V
mA
A
IEA
I
IAC
I
Peak PFC OPFC Current, Source or Sink
0.5
1640
77
PFC−OPFC
P
Power Dissipation, T < 50 °C
mW
°C/W
°C
D
A
R
Thermal Resistance (Junction−to−Air)
Operating Junction Temperature
Storage Temperature Range
ꢃ
J−A
T
−40
−55
150
150
260
4
J
T
STG
°C
T
Lead temperature (Soldering)
Electrostatic Discharge Capability
°C
L
ESD
Human Body Model,
kV
ANSI/ESDA/JEDEC JS−001−2012
Charged Device Model,
JESD22−C101
2
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
V
V
Operating Voltage
15
DD−OP
L
Boost Inductor Mismatch
−5
+5
%
MISMATCH
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
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FAN9673
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V = 15 V and T = −40~105°C)
DD
J
Symbol
Parameter
Condition
Min
Typ
Max Unit
VDD SECTION
I
Startup Current
V
V
= V
- 0.1 V
30
6
80
7
ꢂ A
DD ST
DD
TH−ON
I
Operating Current
= 14 V, Output Not Switching, R
25 kꢁ
=
4
mA
DD−OP
DD
RI
V
Turn−On Threshold Voltage
V
Rising
11.7
2
12.8
13.9
3
V
V
TH−ON
DD
ΔV
UVLO Hysteresis
TH
DD−OVP
V
V
DD
V
DD
V
DD
OVP Threshold
OPFC1~3 Disabled, IEA1~3 and SS Pull Low
23
24
1
25
V
ΔV
OVP Hysteresis
OVP Debounce Time
V
DD−OVP
D−OVP
t
80
μs
OSCILLATOR (Note 3)
V
Sourcing Voltage on RI
PFC Frequency Test Case 1
PFC Frequency Test Case 2
Voltage Stability
R
R
R
= 25 kꢁ
= 25 kꢁ
= 12.5 kꢁ
1.15
30
1.20
32
1.25
34
66
2
V
kHz
kHz
%
RI
RI
RI
RI
f
f
OSC1
OSC2
58
62
f
13 V ≤ V ≤ 22 V
DD
DV
f
DT
Temperature Stability
2
%
ΔV
ΔV
D
V
V
of PFC Frequency 32 kHz
of PFC Frequency 64 kHz
R
R
= 25 kꢁ
5
V
IEA−SAW32
IEA−SAW64
PFC−MAX
IEA−SAW
IEA−SAW
RI
= 12.5 kꢁ
5.15
97
V
RI
Maximum Duty Cycle
V
> 7 V
< 1 V
94
%
IEA
IEA
D
Minimum Duty Cycle
V
0
%
PFC−MIN
RANGE1
RANGE2
f
f
Frequency Range 1 (Notes 3, 4)
Frequency Range 2 (Notes 3, 4)
Minimum Dead Time
18
55
40
75
kHz
kHz
ns
t
R
R
= 10.7 kꢁ
600
DEAD−MIN
RI
INPUT−RANGE SETTING (VIR)
V
VIR−H
HIGH Setting Level for High Voltage In-
put Range
= 500 kꢁ (V = 5 V)
VIR
3.5
V
V
VIR
V
VIR−L
LOW Setting Level for Low Voltage In-
put Range or Full Voltage Input Range
V
VIR
= 0 V
1.5
13
I
Sourcing Current of VIR Pin
7
10
22
60
ꢂ
A
VIR
PFC SOFT−START
I
SS
Constant Current Output for Soft−Start
Maximum Voltage on SS
System Brown−in
ꢂ A
V
V
6.8
SS
SS−Discharge
I
Discharge Current of SS Pin
Brownout, SAG, V
Short, OTP
> 4 V, R Open /
ꢂ
A
CM1
RI
VOLTAGE ERROR AMPLIFIER
V
Reference Voltage
PVO = GND, T = 25°C
2.45
42
2.50
65
2.55
V
REF
J
A
Open-Loop Gain (Note 3)
Transconductance
dB
ꢂ S
ꢂ A
ꢂ A
ꢂ A
nA
V
V
G
V
V
V
− V
= 0.5 V, T = 25°C
100
50
mv
NONINV
INV
J
I
Maximum Source Current
Maximum Sink Current
Input Bias Current Range
Pull High Current for FBPFC
= 2 V, V
= 3 V
= 3 V
40
−1
FBPFC−L
FBPFC−H
FBPFC
FBPFC
VEA
VEA
I
= 3 V, V
−50
−40
I
1
BS
FBPFC−FL
I
FBPFC Floating
500
6.0
0
V
VEA H
Output High Voltage on V
V
= 2 V
= 3 V
5.7
-
VEA
VEA
FBPFC
FBPFC
V
VEA L
Output Low Voltage on V
V
0.15
V
-
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FAN9673
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V = 15 V and T = −40~105°C)
DD
J
Symbol
Parameter
Condition
Min
Typ
Max Unit
VOLTAGE ERROR AMPLIFIER
I
Discharge Current
Brownout, R Open /Short, OTP, SAG
10
ꢂ A
VEA−DIS
RI
V
Threshold Voltage for Low−Power De-
tection
When V
IEA1~3
< V , V are Off &
VEA−OFF OPFC1~3
0.3
V
-
VEA
VEA OFF
V
are Pulled Low
CURRENT ERROR AMPLIFIERS
G
Transconductance
V
V
= V , V = 4 V,
INV IEA
88
0
ꢂ S
mi
NONINV
ILIMIT
> 0.6 V, T = 25°C
J
V
Input Offset Voltage
V
VEA
V
IAC
V
VIR
= 0.45 V, R
= 12 Mꢁ,
mV
OFFSET
IAC
= 311 V, V
= 2 V,
FBPFC
> 5 V, T = 25°C
J
V
Output High Voltage
Output Low Voltage
Sourcing Current
6.8
35
7.0
0
V
IEA−H
V
0.4
V
IEA−L
I
L
V
V
− V , = +0.6 V,
50
ꢂ A
NONINV
IEA
INV
= 1 V, V
>0.6 V
ILIMIT
I
H
Sinking Current
V
V
− V , = −0.6 V,
−50
−35
ꢂ
A
NONINV
IEA
INV
= 6.5 V, V
>0.6 V
ILIMIT
A
Open−Loop Gain (Note 3)
IEA Pin Pull−Low Capability
40
50
dB
I
I
V
IEA
≥ 5 V
500
μA
IEA−LOW
GAIN MODULATOR (Current Command Generator)
I
Input for AC Current (Notes 3, 5)
Bandwidth (Notes 3, 5)
Multiplier Linear Range
0
65
ꢂ A
kHz
V
AC
BW
I
= 40 ꢂ A
2
AC
V
Gain Modulator Output (I * R ) Test
0.490
V
= 106.07 V, R
= 6 Mꢁ, V
CM2, CM3
=
RM
MO
M
IAC
IAC
FBPFC
Cases
2.25 V, V
= 2 V, V
V
> 4.5 V,
BIBO
T = 25°C
J
V
= 120.21 V, R
= 6 Mꢁ, V
CM2, CM3
=
0.430
0.327
0.320
0.260
7.5
IAC
IAC
FBPFC
2.25 V, V
= 2 V, V
V
> 4.5 V,
BIBO
T = 25°C
J
V
IAC
= 155.56 V, R
= 6 Mꢁ, V
CM2, CM3
=
IAC
FBPFC
2.25 V, V
= 2 V, V
V
> 4.5 V,
BIBO
T = 25°C
J
V
IAC
= 311.13 V, R
= 12 Mꢁ, V
FBPFC
=
=
IAC
2.25 V, V
= 2 V, V
V
> 4.5 V,
BIBO
CM2, CM3
V
VIR
> 3.5 V, T = 25°C
J
V
IAC
= 373.35 V, R
= 12 Mꢁ, V
FBPFC
IAC
2.25 V, V
= 2 V, V
V > 4.5 V,
BIBO
CM2, CM3
V
VIR
> 3.5 V, T = 25°C
J
R
Resistor of Gain Modulator Output
ILIMIT (Current Command Limit)
Range of Peak Value in Current Com-
R
= V /I
RM MO
kꢁ
M
M
V
0.2
0.8
V
V
RM−R
mand (V /4)
ILIMIT
V
Current Command Limit Test Case
R
= 42 kꢁ, R = 25 kꢁ,
0.504
49
RM−ILIMIT
ILIMIT
RI
V
R
= R
* I
/4
RM−LIMIT
ILIMIT ILIMIT
I
Sourcing Current of ILIMIT Pin
= 25 kꢁ
ꢂ A
ILIMIT
RI
ILIMIT2 (CS1 /CS2 /CS3, Pulse−by−Pulse Current Limit)
V
V
V
Peak Current Limit Voltage Test Case
R
= 30 kꢁ, R = 25 kꢁ,
1.48
1.48
1.48
49.5
V
V
ILIMIT2−CS1
ILIMIT2−CS2
ILIMIT2−CS3
ILIMIT2
RI
CS1~3 > V
ILIMIT2
OPFC1 Disables, V
Pull Low
IEA1~3
V
I
Sourcing Current for ILIMIT2 Pin
R
= 25 kꢁ, T = 25°C
ꢂ A
ILIMIT2
RI
J
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FAN9673
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V = 15 V and T = −40~105°C)
DD
J
Symbol
Parameter
Condition
Min
Typ
Max Unit
ILIMIT2 (CS1 /CS2 /CS3, Pulse−by−Pulse Current Limit)
t
t
t
Leading−Edge Blanking Time of ILIMIT
V
= 15 V, OPFC Drops to 9 V
250
250
250
200
200
200
4.0
ns
ns
ns
PFC−BNK1
PFC−BNK2
PFC−BNK3
DD
of Each Channel
t
t
t
Propagation Delay to Output of Each
Channel
400
400
400
4.2
ns
ns
ns
V
PD1
PD2
PD3
V
Threshold of ILIMIT2 Open−Circuit Pro- OPFC1~3 Disabled and V
tection
Pull Low
3.8
ILIMIT2−OPEN
IEA1~3
TriFault Detect™
V
FBPFC Under−Voltage Protection
FBPFC Over−Voltage Protection (OVP)
FBPFC OVP
0.4
2.70
200
0.5
2.75
250
2
0.6
2.80
300
V
V
PFC−UVP
PFC−OVP
V
ΔV
mV
ms
PFC−OVP
t
FBPFC Open Delay (Note 3)
V
= V
to FBPFC Open, 470 pF
-
FBPFC
PFC−UVP
FBPFC OPEN
from FBPFC to GND
t
Under−Voltage Protection Debounce
Time
50
ꢂ s
FBPFC−UVP
PVO
V
PVO
Programmable Output Setting Range on
PVO Pin
0.3
3.5
V
V
PVO Disable Voltage
PVO< V
0.2
1.6
V
V
PVO_DIS
PVO_DIS
V
Low−clamp of FBPFC based on PVO
FBPFC Voltage Test Cases
FBPFC Connected to VEA, V
FBPFC Connected to VEA, V
FBPFC Connected to VEA, V
PVO Open
= 4 V
PVO−CLAMPH
PVO
PVO
PVO
V
V
= 0.3 V
= 3.5 V
2.425
1.625
1
V
FBPFC1
FBPFC2
V
I
PVO Discharge Current
ꢂ A
PVO−Discharge
GAIN COMPENSATION (GC) SECTION (Note 6)
I
Test Cases of Mirror Current of I on
V
V
V
= 0 V, V
= 0 V, V
= 5 V, V
= 127.28 V, R
= 6 Mꢁ,
= 6 Mꢁ,
= 12 Mꢁ.
20.71
51.86
51.86
100
ꢂ A
ꢂ A
ꢂ A
nA
V
GC−L1
GC−L2
AC
VIR
VIR
VIR
IAC
IAC
IAC
IAC
IAC
IAC
GC Pin
I
= 311.13 V, R
= 311.13 V, R
I
GC−HV
I
Pull High Current for GC−Pin Open
GC−Pin Open Voltage
GC−OPEN
V
V
GC
> V V
GC−OPEN IEA
, OPFC1, 2, 3 Blanking 2.85
12
3.00
3.15
87
GC−OPEN
INDUCTANCE SETTING (LS) SECTION (Note 6)
Acceptable Range of Inductance Setting
Voltage Difference between V and
R
kꢁ
LS
V
V
– V ≥ 0 V
50
mV
LS−MIN
FBPFC
FBPFC
VIR
GC
V
GC
on LS Pin
BROWN IN /OUT
V
Threshold of Brown−out at VIR=LOW
Setting (Full AC−Input Range)
V
V
< 1.5 V, R
= 6 Mꢁ
1.00
1.05
850
1.05
700
450
1.10
1.10
V
BIBO−FL
IAC
ΔV
Hysteresis
> V
+△V ,
BIBO−F
mV
V
BIBO−F
BIBO
BIBO−FL
Brown−in, Start SS
V
Threshold of BO at VIR=HIGH Setting
(High AC−Input Range)
V
VIR
> 3.5 V, R
= 12 Mꢁ
1.00
BIBO−HL
IAC
ΔV
Hysteresis
V
BIBO
> V
+△V ,
BIBO−H
mV
ms
BIBO−H
BIBO−HL
Brown−in, Start SS
t
Under−Voltage Protection Delay Time
UVP
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8
FAN9673
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V = 15 V and T = −40~105°C)
DD
J
Symbol
Parameter
Condition
Min
Typ
Max Unit
SAG PROTECTION SECTION
V
SAG Voltage of BIBO
SAG Debounce Time
1. V
2. V
< V
& V
& V
High for 33 ms, or
0.85
33
V
SAG
BIBO
BIBO
SAG
SAG
RDY
RDY
< V
Low, Brownout,
t
V
BIBO
< V
& V High
RDY
ms
SAG−DT
SAG
RLPK, VOLTAGE−SETTING RESISTANCE FOR PEAK DETECTOR
I
Pull High Current for RLPK Open
100
nA
RLPK−OPEN
V
Threshold of RLPK−pin Open−Circuit
Protection
RLPK Open
2.28
2.40
2.52
V
RLPK−OPEN
LPK, PEAK−DETECTOR OUTPUT (Note 7)
V
V
Output Test Cases
V
V
J
= 311 V, R
= 1 2Mꢁ,
3.168
3.80
1.29
3.80
32
V
V
V
V
LPK−H1
LPK
IAC
VIR
IAC
> 3.5 V, R
= 12.4 kꢁ,
LPK
T = 25°C
V
V
IAC
V
VIR
= 373 V, R
= 12 Mꢁ,
= 12.4 kꢁ,
LPK−H2
IAC
> 3.5 V, R
LPK
T = 25°C
J
V
V
V
IAC
V
VIR
= 127 V, R
= 6 Mꢁ,
= 12.4 kꢁ,
LPK−L1
IAC
< 1.5 V, R
LPK
T = 25°C
J
V
IAC
V
VIR
= 373 V, R
= 6 Mꢁ,
= 12.4 kꢁ,
LPK−L2
IAC
< 1.5 V, R
LPK
T = 25°C
J
V
AC OFF Threshold Voltage Test Case
AC ON Threshold Voltage Test Case
V
= 373 V, R
= 12 Mꢁ, V
Pull Low
> 3.5V
> 3.5 V
V
V
AC−OFF
IAC
IAC
VIR
After t
V
AC−OFF IEA
V
V
IAC
= 373 V, R
= 12 Mꢁ, V
V
AC−OF
AC−ON
IAC
VIR
+26
F
CM1 SECTION
I
CM1 Sourcing Current
PFC Disable Voltage
55
4
ꢂ A
CM1
V
I R > 4 V
CM1 * CM1
V
CM1−disable
OPFC1~3 Disabled and IEA1~3 Pull Low
and SS Pull Low
When I
R
< 4 V or Short
0
°
°
°
ꢃ 1
ꢃ 2
ꢃ 3
Phase of OPFC1
CM1 * CM1
Phase of OPFC2 (Note 8)
Phase of OPFC3 (Note 8)
110
230
120
240
130
250
CM2 SECTION
I
CM2 Sourcing Current
55
4
ꢂ
A
CM2
CM2−disable
V
Channel−2 Disable Voltage
I
* R
> 4 V or CM2 Floating
V
CM2
CM2
OPFC2 Disables and IEA2 PulIs Low
V
Set VEA Unload Voltage
Phase of OPFC1 (Note 8)
Phase of OPFC3 (Note 8)
0
3.8
V
°
CM2−range
I
* R
> 4 V or CM2 Floating
0
ꢃ
1
CM2
CM2
ꢃ
3
170
180
190
°
CM3 SECTION
I
CM3 Output Current
55
4
ꢂ A
CM3
CM3−disable
V
Channel−3 Disable Voltage
I
* R
> 4 V or CM3 Floating
V
CM3
CM3
OPFC3 Disables and IEA3 PulIs Low
V
Set VEA Unload Voltage
Phase of OPFC1 (Note 8)
Phase of OPFC2 (Note 8)
0
3.8
V
°
CM3−range
When I
* R
> 4 V or CM3 Floating
0
ꢃ
1
CM3
CM3
ꢃ 2
170
180
190
°
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9
FAN9673
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V = 15 V and T = −40~105°C)
DD
J
Symbol
Parameter
Condition
Min
Typ
Max Unit
RDY SECTION
V
Level of V
to Pull RDY High
V
V
V
= 0 V, Brown−in, V
> V
FB−RD
2.3
2.4
1.15
0.85
100
5.0
2.5
V
V
FB−RD
FBPFC
PVO
PVO
PVO
FBPFC
ΔV
Hysteresis
Hysteresis
= 0 V, V < 1.5 V
IR
FB−RD−L
FB−RD−H
ΔV
= 0 V, V > 3.5 V
V
IR
Z
Pull High Input Impedance
HIGH Voltage of RDY
LOW Voltage of RDY
T = 25°C
J
kꢁ
V
RDY
RDY−High
V
4.8
V
Pull High Current = 1 mA
0.5
V
RDY−Low
PFC OUTPUT DRIVER 1~3
Gate Output Clamping Voltage
V
V
V
V
= 22 V
13
8
15
17
V
V
GATE−CLAMP
DD
DD
DD
V
Gate Low Voltage
Gate High Voltage
Gate Rising Time
= 15 V, I = 100 mA
1.5
GATE−L
GATE−H
O
V
= 13 V, I = 100 mA
V
O
t
r
V
V
= 15 V, C = 4.7 nF,
from 2 V to 9 V
70
60
ns
DD
OPFC
L
t
f
Gate Falling Time
V
V
= 15 V, C = 4.7 nF,
from 9 V to 2 V
ns
DD
OPFC
L
OTP
T
Over−Temperature Protection (Note 3)
140
30
°C
°C
OTP−ON
ΔT
Hysteresis (Note 3)
OTP
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. This parameter, although guaranteed by design, is not 100% production tested.
4. The setting range of resistance at the RI pin is between 53.3 kꢁ and 10.7 kꢁ.
5. Frequency of AC input should be <75 Hz.
6. The RLS and RGC setting suggestion follows the calculation result from application notes AN−4164 and AN−4165.
7. LPK specification is guaranteed at state of PFC working.
8. Pull the CM pin low to ground, ensuring VCM < 0.2 V, to enable an individual channel.
THEORY OF OPERATION
Continuous Conduction Mode (CCM)
L
The boost converter, shown in Figure 4, is the most
popular topology for power factor correction in AC−DC
power supplies. This popularity can be attributed to the
continuous input current waveform provided by the boost
inductor and the boost converter’s input voltage range low
down to 0 V. These fundamental properties make
close−to−unity power factor easier to achieve.
Figure 4. Basic PFC Boost Converter
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10
FAN9673
The boost converter can operate in Continuous
These are the three inputs to the gain modulator:
Conduction Mode (CCM) or in Boundary Conduction Mode
(BCM). These two descriptive names refer to the current
flowing in the energy storage inductor of the boost power
stage.
• I : A current representing the instantaneous input
IAC
voltage (amplitude and wave shape) to the PFC. The
rectified AC input sine wave is converted to a
proportional current via a resistor and fed into the gain
modulator. A sampling mechanism on I
ground noise, important in high−power, switching−power
minimizes
IAC
I
conversion environment. The gain modulator responds
linearly to I
.
AC
• V : Voltage proportional to the peak-voltage output of
LPK
t
the bridge rectifier when the PFC is working. The signal
Typical Inductor Current Waveform In Continuous Conduction Mode
is the output of peak−detect circuit detecting from the I
.
AC
This factor of the gain modulator is input−voltage
feed−forward control. This voltage information is not
valid when the PFC is not working.
I
• V
: The output of the voltage error amplifier. The gain
modulator responds linearly to variations of this voltage.
VEA
The output of the gain modulator is a current signal, I
,
0A
t
MO
as eq. 1:
Typical Inductor Current Waveform In Boundary Conduction Mode
IAC VVEA
Figure 5. Basic PFC Boost Converter
(eq. 1)
IMO + K
2
VLPK
As the names indicate, the inductor current in CCM is
continuous and always above zero. In BCM, the new
switching period is initiated when the inductor current
returns to zero. There are many fundamental differences in
CCM and BCM operations and the respective designs of the
boost converter. The FAN9673 is design for CCM control,
as Figure 5 shows. This method reduces inductor current
ripple because the start current of each cycle is not 0 A
typically. The ripple is controlled by the operation frequency
and inductance design. This characteristic makes the peak
current in the power semiconductor devices lower.
where the K term is about 0.8 for V < 1.5 V and 3.2 for
IR
V
IR
> 3.5V respectively.
The current signal, I , is in the form of a full−wave
MO
rectified sinusoid at twice of the line frequency. The gain
modulator forms the reference for the current−loop and
ultimately controls the instantaneous current drawn from the
power line.
VPFC
VIN
IL
RFB1
VFBPFC
RFB2
CO
RIAC
Gain Modulator (IA, LPK, VEA)
I
IAC
RCS
The FAN9673 employs two control loops for power factor
correction: a current control loop and a voltage control loop.
The current control loop shapes inductor current, as shown
in Figure 6, through a current command, IMO, from the gain
modulator.
A (IAC)
IAC
Current Command
(C. Comd.)
A
C (VLPK)
VLPK
Peak
Detector
C
B
IMO
B (VEA)
Gain Modulator
Current Command
IL
A x B
C2
=
VEA
(C. Comd.)
2.5V
VFBPFC
R
IL
M
Average of I + I
MO
L
PO
VO
V
R
CS
VGS
VEA
Figure 6. CCM PFC Operation Waveforms
C. Comd.
IL
The gain modulator is the block that provides the
reference to control PFC input current. The output signal of
the gain modulator, IMO, is a function of VVEA, IIAC, and
VLPK; as shown in the Figure 7.
Figure 7. Input of Gain Modulation
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11
FAN9673
Current Balance
Interleaving
Current matching of different channel is an important
topic of multi−channel control. In FAN9673, control of
The FAN9673 controller is used to control three−channel
boost converters connected in parallel. The controller
operates in average−current mode and supports Continuous
Conduction Mode (CCM). Each channel affords one−third
the power when the system operates close to full load or
when channel management is disabled.
current in each channel is based on sensed signal V to
CS
track the current command from the gain modulator, as
shown in Figure 8.
Parallel power processing increases the number of power
components, but the current rating of independent channels
is reduced, allowing power semiconductors with lower
current ratings to be applied.
AVG
The switches of the three boost converters can operate at
three−channel with 120° out−of−phase or two−channel with
180° out−of−phase (one channel disable at light load). The
interleaving controller can reduce the total ripple current of
input. Simultaneously, the output current ripple of each
channel is evenly distributed and sequentially rippled on the
output capacitor, which can extend the life of the capacitor.
I , High Inductance Frequency
L
I , Low Inductance Frequency
L
Figure 8. Average Current Mode Control
The main factors to balance current in each channel are
layout and device tolerance. The tolerance of the shunt
resistor for the current sense is especially important. If the
Channel Management 2/3: CM Control
The CM pin is used for controlling channel management.
The channel management is realized by changing a gain,
acting as changing relative weighting, for the current
command. The relationship of CM and the gain of the slave
channel is shown in Figure 10. The level of CM set the
feedback signal, V , has large deviation due to the
CS
tolerance of the sense resistor, the current of the channels
tends to be unbalanced. High precision resistors are
recommended.
High−power applications implies current values are high,
so the distance of layout trace between the current sense
resistors and the controller or power ground (negative of
output capacitor) to IC ground is important, as shown in
Figure 9. The longer trace and large current make the offset
voltage and ground bounce differ significantly for different
channels. Decreasing the deviation help balancing different
channels. Please check the layout guidance in application
notes AN−4164 or AN−4165.
threshold of power level, representing by V
reducing the current command for the slave PFC. The
, for
VEA
FAN9673 starts to reduce the current command (I × R )
MO
M
for channel 2/3 by G
from one to zero when the V
ain2/3
VEA
level is lower than its CM level, as Figure 11 and Figure 12
show. The output power of the slave channel is reduced in
response to reduction in current command. For example,
when CM2 is set at 3 V and V
is less than the CM2
VEA
voltage, the channel management block reduces the
command for channel 2 as:
VIN
VO
Vgmi2) + IMO RM Gain2
(eq. 2)
Gate2
RCS2
Gate1
RCS1
VIN
VO
VCS1
V
Gate2
ISENSE2
Gate1
ISENSE1
Differential
Differential
Sense Filter
Sense Filter
Current
Current
Close
Gate1
Gate2
Command
Command
Loop 1
Generator
Gain1
100%
CS2−
CS2+
GND
CS1−
CS1+
Current
Loop 2
CM
Block
Voltage
Loop
VO
VVEA
FAN9673
Gain2
0~100%
V
Figure 10. Current Balance Factors
Filter Ground
IC GND to Power ground
Figure 9. Current Balance Factors
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12
FAN9673
Vgmi+
Channel
Management
Table 2 explains the phase and gain change of each
channel when the PFC operates at various loads. The loading
decreases the gain to the slave until it is disabled. The phase
of Channel Management (CM) mode doesn’t change when
channel 3 is disabled. The behavior shown in Figure 13.
Without Channel
Management
Full load, all channel operation
IL3
VEA
0
VCM
V AC
IL2
IL1
IL1
time
Mid. load ~ light load, linear decrease gain of
channel 2 & 3, final only left Channel 1 at light load
VAC
Po
IL3
IL2
IL1
IL2
Gain2 = 0
0< Gain2 <1
Gain2 = 1
Figure 11. VVEA and CM Relationship
0°
120° 240°
Figure 13. Phase and Gain Change of CM Control
V
AC
I
I
L1
L2
P
O
V
V
VEA
CM
Gain2=1
L2
Gain to I
Channel Management
Area, Gain2 < 1
Figure 12. VVEA and VCM Relationship in
Channel Management Operation
Table 2. PHASE AND GAIN CHANGE OF CM CONTROL
CM (Channel Management)
Channel 1
Phase and Gain
Channel 2
Channel 3
Heavy Load (All Channel 100% Works)
Mid. Load (Channel 3 is Disabled)
Light Load (Only Channel1 Left)
0° (Gain1 = 1)
0° (Gain1 = 1)
0° (Gain1 = 1)
120° (Gain2 = 1)
120° (0 < Gain2 < 1)
Disable (Gain2 = 0)
240° (0 < Gain3 < 1)
Disable (Gain3 = 0)
Disable (Gain3 = 0)
Channel Management 2: External Control
Channel Management (CM) function can also be accessed
by an MCU through the connection shown in Figure 14. CM
pins have internal pull−up current source. If V > 4 V, the
channel is disabled. To enable the channel, make V = 0 V,
determine when to turn on/off the slave channel. For
example, as shown in Figure 16, two thresholds, V
P2−OFF−L
and
V
V
are set in MCU program. When
P2−OFF−H,
< V
P2−OFF−L
> V
P2−OFF−H
,
the slave PFC turns off. If
CM
VEA
V
VEA
, the slave PFC turns on.
CM
as shown in Figure 15.
The CM pin of the slave should be connected with a switch
S to ground. One pin of MCU must read the V
signal to
2
VEA
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13
FAN9673
CS+ CS−
When CM is accessed this way, relative phase of OPFC of
each channel changes when the loading changes, as
illustrated in Table 3 and Figure 17. When the MCU disables
channel 3 at mid−load, the relative phase angle of channel 2
gmi
Sample
& Hold
CM
S
CM
Channel
enable
signal
to channel 1 shifts from 120°C to 180°C. G
of each
ain2/3
channel under this control method switches between 100%
and 0%.
from MCU
55uA
OSC
Gain
Modulator
Full load, all channel operation
IL3
IL2
IL1
Figure 14. Channel Management by MCU
VCM(V)
Mid. load, disable channel 3 by external signal
IL3
6
VCM−LIMIT (4V)
120˚à 180˚
IL2
V VEA
IL1
0°
180°
time
time
0
Figure 17. Phase Change under
External Signal Control
VAC
IL
Figure 15. Channel Management by MCU
VAC
IL1
IL2
P O
V VEA
V P2−OFF−H
V P2−OFF−L
à
MCU S2
MCU Turn−Off Slaver
Figure 16. Channel Management by
External Signal from MCU
Table 3. PHASE CHANGE OF EXTERNAL SIGNAL CONTROL
Phase
(Disable Channel: V
> 4 V, Enable Channel: V
= 0 V)
External Signal Control
CM
CM
Channel 1
Channel 2
120°
Channel 3
240°
Heavy Load (All Channels Enabled)
Mid. Load (Channel3 Disabled)
Light Load (Channel 2/3 Disabled)
Disable All System
0°
0°
0°
180°
Disable (V
> 4 V)
> 4 V)
CM3
CM3
Disable (V
> 4 V)
Disable (V
CM2
V
CM1
> 4 V, All Channels Disabled
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14
FAN9673
FUNCTIONAL DESCRIPTION
Internal Oscillator (RI)
TriFault Detect Technology
Frequency of an internal oscillator is determined by an
To improve power supply reliability, reduce system
component count, and simplify compliance to UL 1950
safety standards, the FAN9673 brings TriFault Detect
technology. This feature monitors FBPFC for certain PFC
fault conditions.
In the case of a feedback path failure, the output of the PFC
can exceed operating limits. Should FBPFC go too low, too
high, or open, the TriFault Detect senses the fault and
terminates the PFC output drive.
external resistor, R , on the RI pin. The frequency of the
RI
oscillator is given by eq. 3. The frequency can be freely set
in two ranges, 18 kHz ~ 40 kHz and 55 kHz~75 kHz. Setting
frequency between 40 kHz and 55 kHz is not allowed in
FAN9673.
8 108
RRI
(eq. 3)
fosc
+
Current−Control Loop of Boost Stage
TriFault Detect is an entirely internal circuit. It requires no
external components to perform its function.
As shown in Figure 18, the two control loops for power
factor correction are a current−control loop and a
voltage−control loop. Based on the reference signal
obtained at the IAC pin, the error amplifier in
current−control loop regulates current signal as:
PFC Over−Voltage Protection (OVP)
FAN9673 has an auto−restart OVP function. When the
feedback level, V
, reaches 2.75 V (reference level is
FBPFC
2.5 V), the PFC gate signal stops. The PFC gate signal
resumes when V returns to 2.5 V.
I
V
AC
EA
2
I
R
+ I
R G
+ K
R G
M
ain2ń3
FBPFC
L
CS
MO
M
ain2ń3
V
LPK
(eq. 4)
PFC Brown In/Out (BIBO)
An internal AC Under−Voltage Protection (UVP)
Average value of sensed current, I × R , is regulated to
L
CS
comparator monitors the AC input information from V , as
the current command, I × R . G
is a gain between
IN
MO
M
ain2/3
shown in Figure 19. The OPFC is disabled when the V
0 ~ 1 when the channel management block is engaged for
the slave channels. G term is equal to one for channel 1.
BIBO
is less than 1.05 V for 410 ms. If V
is larger than 1.9 V
BIBO
ain2/3
(V
< 1.5 V) or 1.75 V (V
> 3.5 V), the PFC stage is
VIR
VIR
Voltage−Control Loop of Boost Stage
The voltage−control loop regulates PFC output voltage by
enabled. The VIR pin is used to set the AC input range
according to Table 4.
using the internal error amplifier, G , making voltage on
mv
FBPFC same as the internal reference voltage, 2.5 V. It
stabilizes PFC output voltage and decreases 120−Hz ripple
on PFC output voltage.
Table 4. BIBO SETTING OF VARIOUS AC INPUT
R
VIR
R
IAC
Input
Setting Setting
Range
(kW)
(MW)
AC (V)
BIBO Level (V)
85/75
V
IN
VPFC
Full−Range 85 ∼ 264
HV−Single 180 ∼ 264
10
6
IL
470
12
170/160
RCS
1.9V/1.7V (PFC brown−in threshold)
VIN
CS−
CS+
VBIBO
LS
gmi
LPT
CM
IEA
GC
CM
RI1
CI1
RM
RIAC
CI2
1.05V (brownout protection trip point)
IMO
IAC
PFC runs
Drive
Peak
Detecter
LPK
VEA
Figure 19. VBIBO According to the PFC Operation
Logic
OPFC
RI
OSC
RFB1+FB2
RV1
CV1
gmv
PFC Gate Driver
CV2
PVO
2.5V
For high−power applications, the switch device of the
system requires high driving current. The totem−pole circuit
shown in Figure 20 is recommended.
FBPFC
RFB3
Figure 18. Gain Modulation Block
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15
FAN9673
VDD
V
ILIMIT2
, are configurable through ILIMIT and ILIMIT2
pins.
S
PFC
Power (Normal State)
In the normal case, average input power is controlled by
the command V
. When V
rises to 5.6 V, it is
VEA
VEA
internally clamped. Input power can’t increase further.
R
CS
Current Limit 1 (Abnormal State)
The current command from the gain modulator is
2
K × I ×V
/V
. In abnormal state, such as AC cycle
AC
VEA LPK
Figure 20. Gate Drive Circuit
miss and recover in a short period, the V
has a delay
LPK
before returning to the original level. This delay makes the
current command increased. If the command is greater than
Differential Current Sensing (CS+, CS−)
the limit clamp level, V , current command will be
ILIMIT
Switching noise problems in interleaved PFC control is
more critical than on a single channel, especially for current
sensing. The FAN9673 uses a differential amplifier to
eliminate switching noise from other channels. The
FAN9673 has three groups of differential current−sensing
pins. The CSn+ and CSn− are the inputs of the internal
differential amplifiers. This makes the PFC more stable in
higher−power applications and eliminates switching noise
from other channels. As Figure 21 shows, ground bounce
can be decreased by a differential sense function.
clamped, as shown in Figure 22 and Figure 23. The peak
current of this state can be used as the maximum current for
inductor design, assuring inductor is not saturated.
1.2V
I
RI
5
A
ILIMIT
3
C
I × R
ILIMIT
RILIMIT
Differential
Current Sense
4
VRM
B
Gain Modulator
Figure 22. Current Command Limit by ILIMIT
Period
Period
Current Limit 2 (Saturation State)
Use 80% ~ 90% of the maximum current of the switch
Figure 21. Gate Drive Circuit
device to serve as the saturation protection. V
is a
LIMIT2
cycle−by−cycle limit.
Linear Predict Function (GC & LS)
Current sense signal reflects inductor current only when
OPFC is on. The linear predict function is used to emulate
the behavior of inductor current when the OPFC is off.
Resistor on the LS pin is used to set equivalent inductance
value for the internal emulator. Resistor on the GC pin is
used to align sensed input voltage (IAC) and output voltage
(FBPFC) signals. Values of those resistors can be
determined by:
VILIMIT2 = Saturation Protection
V
Non−Saturation
VCS.PK
VCS
PFC
Command
Gmi+
VILIMIT/4
Case1:
Max. Power (Normal),
“B” = 6 V
Case2:
Case3:
LPFC
> Max. Power (Abnormal),
V “B” = 6 V
> Max. Power (Abnormal),
AC cycle drop, as left case,
but user uses wrong choke
can not afford current at Max.
mommand.
RLS
+
V
VEA−MAX
VEA−MAX
AC cycle drop
= 6V, but “C” abnormal
(RFB1)RFB2)RFB3
)
1.5 10*9 RCS
V
RFB3
VEA
short time, clamp by V
ILIMIT
(eq. 5)
(eq. 6)
Right design,
max power
limited by
VVEA
Right design at
abnormal test,
command from
Multiplier clamp
by VILIMIT
Wrong design at
abnormal test, but
6 106
RFB1)RFB2)RFB3
protect by V
ILIMIT2
RGC
+
(
)
RFB3
Figure 23. ILIMIT and ILIMIT2 Setting
Care must be taken that RLS value need to be within
12~87 kꢁ.
Programmable PFC Output Voltage (PVO)
Current−Limit Protection
The FAN9673 includes three factors that limits current to
manage OCP and inductor saturation: V
In some cases, decreasing the PFC output voltage can
improve efficiency of the PFC stage. The PVO pin is used
to program output voltage, as shown in Figure 24. An
limit, V
,
VEA
ILIMIT
and V
. The current-limit thresholds, V
and
ILIMIT2
ILIMIT1
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16
FAN9673
VPFC
external voltage signal, from MCU or other source, is
provided to PVO pin.
IL
This function is enabled when V
> 0.5 V. Upon
PVO
enabled, V
regulation target becomes:
FBPFC
VPVO
4
+ 2.5 V * ƪ ƫ
(eq. 7)
VFBPFC
RFB1 + FB2
VREF
For instance, if PVO input is 1 V, R +R
= 3.7 Mꢁ,
FB1
FB2
RDY
MCU
FBPFC
and R
= 23.7 kꢁ, V
will be regulated to 2.25 V,
FB3
FBPFB
RFB3
making PFC V = 354 V.
O
FR: 2.4V/1.25V
HV: 2.4V/1.55V
VPFC
Brown out
VO
IL
Figure 25. RDY Function to MCU
393V
354V
RCS
V
AC
External
Signal
(MCU)
IL
AC OFF
RFB1
(AC Long Time Drop)
V
IN−OK = 2.4V
IN−OFF = 1.25V (FR) /
1.55V (HV)
VFBPFC
V
2.5V
PVO
RFB2
2.25V
Brownout & PFC Soft
RDY Pull−Low Start
VFBPFC
PFC Soft Start
gmv
VFBPFC
PVO
FBPFC
2.5V
1V
0V
RFB3
VSS
Voltage Protection
VVEA
VRDY à MCU
Second Power Stage working
Figure 24. Programmable PFC Output Voltage
Figure 26. When AC Drops for a Long Time
RDY Function and AC Line Off/AC “SAG”
The ready (RDY) function is used to signal the MCU that
the PFC stage is ready and the downstream power stage can
start to operate. When the feedback voltage on FBPFC rises
V
AC
IL
V
IN−OK = 2.4V
above 2.4 V, V
signal pulls HIGH as shown in Figure 25.
RDY
VIN−OFF = 1.25V (FR) /
If the AC line is OFF (or AC signal drops for a long time),
the FAN9673 enters brown−out and V pulls LOW to
1.55V (HV)
VFBPFC
AC Short Time Drop
RDY
PFC Soft Start
indicate to the MCU that the power stage should stop, as
shown in Figure 26.
When the AC signal drops for only a short time (i.e. 1~1.5
VSS
VVEA
AC cycles), brown−out is not triggered and V
drop too much. In this case, RDY will not go LOW as shown
in Figure 27.
may not
FBPFC
VRDY MCU
à
Second Power Stage working
Figure 27. AC Drops Briefly
AC “sag” means the AC drops to a low level, such as
110 V / 220 V → 40 V. AC “missing” means the AC drops
to 0 V. If AC drops, the PFC attempts to transfer energy to
V before V drops to the 50% level. If AC is 0 V, the PFC
O
O
can’t transfer energy. If the level reaches 50%, the PFC
stops, and FAN9673 resets and waits for AC to return.
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17
FAN9673
Soft−Start
One of the important benefits of this approach is that the
peak indicates the correct RMS value even at no load. At no
load, the HF filter capacitor at the input side of the boost
converter is not discharged around the zero−crossing of the
line waveform. Another notable benefit is that, during line
transients, when the peak exceeds the previously measured
value, the input−voltage feed−forward circuit can react
immediately without waiting for a valid integral value at the
end of the half−line period.
Soft−start is combined with RDY pin operation, as
Figure 26 and Figure 27 show. During startup, the RDY pin
remains LOW until the PFC output voltage reaches 96% of
its nominal value. When the supply voltage of the
downstream converter is controlled by the RDY pin, the
PFC stage always starts with no load because the
downstream converter does not operate until the PFC output
voltage reaches the required level for the design.
Usually, the error amplifier output, V
, is saturated to
The relationship of V
to V
is shown in Figure 29.
VEA
IN.PK
LPK
HIGH during startup because the actual output voltage is
less than the target value. V remains saturated to HIGH
The peak detection circuits recognizes the V information
IN
from I . When recommended design values in Table 4 are
VEA
AC
until the PFC output voltage reaches its target value. Once
the PFC output reaches its target value, the error amplifier
comes out of saturation. However, it takes several line cycles
followed, RLPK pin sets the ratio of V to V
via a
IN
LPK
resistor R
as described in eq. 8. The target value of
RLPK
V
LPK
is usually set as one percent (1%) of V
. The
IN_pk
for V
to drop to its proper value for output regulation,
maximum V
should not exceed 3.8 V when system
VEA
LPK
which delivers more power to the load than required and
causes output voltage overshoot. To prevent output voltage
overshoot during startup caused by the saturation of error
amplifier, the FAN9673 clamps the error amplifier output
operation is at maximum AC input.
As in the below design example, assume the maximum
V
IN.PK
V
IN.PK
at 373 V (264 V ), the relationship of
AC
/ V
is 100, and V
= 3.73 V < 3.8 V.
LPK
LPK
voltage (V ) by the V value until PFC output reaches
EA
SS
VIN.PK
100
RRLPK
12.4k
VLPK
+
(eq. 8)
96% of its nominal value.
Input Voltage Peak Detection
VIN
The input AC peak voltage is sensed at the IAC pin.
Ideally, RMS value of the input voltage should be used for
feed−forward control in the gain modulator circuit. Since the
RMS value of the AC input voltage is directly proportional
to its peak, it is sufficient to find the peak instead of the
more−complicated and slower method of integrating the
input voltage over a half line cycle. The internal circuit of the
IAC pin works with peak detection on the input AC
waveform and output to the LPK pin for MCU use, as shown
in Figure 28.
RIAC
IAC
RLPK
Ratio
R
LPK
tBLANK =5ms
No update after AC− OFF
LPK
VIN/100 >VLPK +0.2V
Step− up tracking
Peak
Detector
VLPK
tBLANK = 5ms
VLPK
Figure 29. Relationship of VIN.PK to VLPK
VIN/100
95%
t
AC−OFF =2.5ms
IEA pull low
tUPDATE = 3.5ms
tAC−OFF = 2.5ms
IEA pull low
VAC−OFF =10%*VLPK
VAC−ON = 20%* VLPK
Figure 28. Waveform of LPK Function
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18
FAN9673
Typical Performance Characteristics
Typical characteristics are provided at T = 25°C and V = 15 V unless otherwise noted.
A
DD
Figure 31. VDD−OVP vs. Temperature
Figure 30. IDD−OP vs. Temperature
Figure 33. VRI vs. Temperature
Figure 32. fosc vs. Temperature
Figure 35. VBIBO−FH vs. Temperature
Figure 34. VBIBO−FL vs. Temperature
Figure 36. VBIBO−HL vs. Temperature
Figure 37. VBIBO−HH vs. Temperature
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19
FAN9673
Typical Performance Characteristics (continued)
Typical characteristics are provided at V = 15 V unless otherwise noted.
DD
Figure 39. GmV−MAX vs. Temperature
Figure 38. VFBPFC−RD vs. Temperature
Figure 40. VOFFSET vs. Temperature
Figure 42. VPFC−OVP vs. Temperature
Figure 44. ILIMIT vs. Temperature
Figure 41. GMI vs. Temperature
Figure 43. VREF vs. Temperature
Figure 45. VLIMIT vs. Temperature
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20
FAN9673
Typical Performance Characteristics (continued)
Typical characteristics are provided at V = 15 V unless otherwise noted.
DD
Figure 47. VILIMIT2−CS1 vs. Temperature
Figure 46. ILIMIT2 vs. Temperature
Figure 49. VRLPK−OPEN vs. Temperature
Figure 48. tPFC−BNK vs. Temperature
Figure 51. VLPK−H2 vs. Temperature
Figure 50. VLPK−H1 vs. Temperature
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21
FAN9673
Table 5. TYPICAL APPLICATION CIRCUIT
Application
Output Power
5000 W
Input Voltage
180 ∼ 264 V
Output Voltage/Output Current
Single−Stage, Three−Channel PFC
393 V/12.72 A
AC
Features
• 180 V ~264 V, Three−Channel PFC Using FAN9673
AC
• Switch−Charge Technique of Gain Modulator for Better
PF and Lower THD
• 40 kHz Low Switching Frequency Operation with IGBT
• Protections:
Over−Voltage
Protection
(OVP),
Under−Voltage Protection (UVP), and Over−Current
Protection (I ), Inductor Saturation Protection
LIMIT
(I
)
LIMIT2
* DBP1, 2
1N5406
LPFC1
RB1
DPFC1
FFH30S60STU
VPFC
100 ꢂH
LPFC2
DPFC2
FFH30S60STU
100 ꢂH
CB
1 ꢂF
RFB1
2.2 Mꢁ
COUT
2040 ꢂF
LPFC3
DPFC3
FFH30S60STU
100 ꢂH
SPFC1~3
FGH40N60SMDF
RFB2
1.5 Mꢁ
RB1
RA1
1 Mꢁ
6 Mꢁ
VDD
VDD
VDD
CFB
RFB3
RB2
1 Mꢁ
RA2
6 Mꢁ
Rsen3
15 mꢁ
Rsen1
15 mꢁ
Rsen2
15 mꢁ
470 pF 23.7 kꢁ
RF1~2
470 ꢁ
CF1
2.2 nF
CF2
2.2 nF
RB3
OPFC1 CS1− CS1+ OPFC2 CS2− CS2+ OPFC3 CS3− CS3+
200 kꢁ
IAC
FBPFC
BIBO
SS
CVC2
RVC1
100 nF
CB1
CB2
RB4
16.2 kꢁ
VEA
IEA1
CVC1
CIC11
CIC21
1 ꢂF
47 nF 0.47 ꢂF
75 kꢁ
CSS
0.47 ꢂF
RLPK
CIC12
RIC11
100 pF
CRLPK
10 nF
1 nF
17.4 kꢁ
RLPK 12.1 kꢁ
CIC122
100 pF
LS
FAN9673
IEA2
IEA3
VDD
CLS
470 pF
43 kꢁ
1 nF
1 nF
RIC21
17.4 kꢁ
RLS
CIC32
RIC31
100 pF
GC
CIC31
CGC
470 pF
17.4 kꢁ
RGC 38.2 kꢁ
ILIMIT2
CVDD
C
22 ꢂF
ILIMIT210 nF
Standby
Power
RILIMIT2
10 kꢁ
VIR
LPK
CVIR
1 nF
MCU
RLPK
RVIR 470 kꢁ
CLPK
0.1 ꢂF
4.7 kꢁ
RI
ILIMIT
CM1
CM2
CM3
PVO
GND
RDY
RRI
CILIMIT RILIMIT
20 kꢁ 10 nF 30 kꢁ
MCU/
MCU signal
(DC)
Sec. Stage
(PFC Ready)
DC Setting Level
Figure 52. Schematic of Design Example
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22
FAN9673
Specification
• Switching Frequency: 40 kHz
for RDY: 2.4 V/1.55 V (96% / 62%)
• V Maximum Rating: 20 V
DD
• V
FBPFC
• V OVP: 24 V
DD
• R : 12 Mꢁ
IAC
• V UVLO: 10.3 V/12.8 V
CC
Inductor Schematic Diagram
• Core: QP2925H (3C94)
• Bobbin: 4 Pins
• PVO: 0 V ∼ 1 V
• PFC Soft−Start: C = 0.47 ꢂ F
SS
• Brown−In/Out: 175 V/165 V
Figure 53. Inductor Schematic Diagram
Table 6. WINDING SPECIFICATION
No.
1
Winding
Pin (S " F)
1 → 4
Wire
Turns
Winding Method
N1
0.1ꢄ × 40 *1
46
Solenoid Winding
2
Insulation: Polyester Tape t = 0.025 mm, 2−Layer
Copper−Foil 1.2T to PIN3
3
Table 7. MOSFET AND DIODE REFERENCE SPECIFICATION
IGBT’s
Voltage Rating
600 V (IGBT)
FGH40N60SMDF
Boost Diodes
FFH30S60STU
600 V
Typical Performance
Table 8. EFFICIENCY
25% Load
50% Load
96.5%
75% Load
96.5%
100% Load
96.2%
180 V/50 Hz
220 V/50 Hz
264 V/50 Hz
96.5%
97.0%
97.6%
97.1%
97.2%
97.1%
97.9%
97.7%
97.6%
Table 9. POWER FACTOR
25% Load
0.9912
50% Load
0.9947
75% Load
0.9971
100% Load
0.9974
180 V/50 Hz
220 V/50 Hz
264 V/50 Hz
0.9800
0.9868
0.9905
0.9924
0.9365
0.9369
0.9526
0.9600
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23
FAN9673
Table 10. TOTAL HARMONIC DISTORTION
25% Load
50% Load
9.17%
75% Load
6.62%
100% Load
6.40%
180 V/50 Hz
220 V/50 Hz
264 V/50 Hz
10.55%
14.32%
25.85%
14.36%
33.22%
12.55%
29.59%
11.26%
27.29%
System Design Precautions
downstream power stage is enabled to operate at full load
once the PFC output voltage has reaches a level close to
the specified steady−state value.
• Pay attention to the inrush current when AC input is first
connected to the boost PFC convertor. It is recommended
to use NTC and a parallel connected relay circuit to reduce
inrush current.
• Add bypass diode to provide a path for inrush current
when PFC start up.
• The PVO function is used to change the output voltage of
PFC, V . The V
should be kept at least 25 V higher
PFC
PFC
than V .
IN
• The PFC stage is normally used to provide power to a
downstream DC−DC or inverter. It’s recommend that
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24
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
LQFP−32, 7x7
CASE 561AB−01
ISSUE O
DATE 19 JUN 2008
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DESCRIPTION:
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32 LEAD LQFP, 7X7
PAGE 1 OF 1
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