FDC021N30 [ONSEMI]

N 沟道,PowerTrench® MOSFET,30V,6.1A,26 mΩ;
FDC021N30
型号: FDC021N30
厂家: ONSEMI    ONSEMI
描述:

N 沟道,PowerTrench® MOSFET,30V,6.1A,26 mΩ

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June 2016  
FDC021N30  
N-Channel PowerTrench® MOSFET  
30 V, 6.1 A, 26 mΩ  
Features  
General Description  
„ Max rDS(on) = 26 mΩ at VGS = 10 V, ID = 6.1 A  
This N-Channel PowerTrench MOSFET is produced using  
Fairchild’s advanced PowerTrench® process that has been  
especially tailored to minimize on-state resistance and yet  
maintain low gate charge for superior switching performance.  
„ Max rDS(on) = 33 mΩ at VGS = 4.5 V, ID = 5.3 A  
„ High Performance Trench Technology for Extremely Low  
rDS(on)  
Applications  
„ High Power and Current Handling Capability in a Widely Used  
Surface Mount Package  
„ Load Switch  
„ Fast Switching Speed  
„ RoHS Compliant  
„ Battery Protection  
„ Power Management  
D
D
D
D
S
G
MOSFET Maximum Ratings TA= 25°C unless otherwise noted.  
Symbol  
VDS  
VGS  
Parameter  
Ratings  
Units  
Drain to Source Voltage  
Gate to Source Voltage  
30  
±20  
V
V
(Note 3)  
(Note 1a)  
(Note 4)  
-Continuous  
-Pulsed  
Power Dissipation  
Power Dissipation  
Operating and Storage Junction Temperature Range  
TA = 25°C  
6.1  
ID  
A
62  
( Note 1a)  
(Note 1b)  
1.6  
PD  
W
0.7  
TJ, TSTG  
-55 to + 150  
°C  
Thermal Characteristics  
RθJA  
RθJA  
Thermal Resistance, Junction to Ambient  
Thermal Resistance, Junction to Ambient  
(Note 1a)  
(Note 1b)  
78  
°C/W  
°C/W  
175  
Package Marking and Ordering Information  
Device Marking  
Device  
Package  
SSOT-6TM  
Reel Size  
7 ’’  
Tape Width  
8 mm  
Quantity  
21N  
FDC021N30  
3000 units  
1
©2016 Fairchild Semiconductor Corporation  
FDC021N30 Rev.1.0  
www.fairchildsemi.com  
Electrical Characteristics TJ = 25°C unless otherwise noted.  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Units  
Off Characteristics  
BVDSS  
Drain to Source Breakdown Voltage  
ID = 250 μA, VGS = 0 V  
30  
V
ΔBVDSS  
ΔTJ  
Breakdown Voltage Temperature  
Coefficient  
I
D = 250 μA, referenced to 25°C  
16  
mV/°C  
IDSS  
IGSS  
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
VDS = 24 V, VGS = 0 V  
VGS = 20 V, VDS = 0 V  
1
μA  
100  
nA  
On Characteristics  
VGS(th)  
Gate to Source Threshold Voltage  
VGS = VDS, ID = 250 μA  
1.0  
1.8  
-5  
3.0  
V
ΔVGS(th)  
ΔTJ  
Gate to Source Threshold Voltage  
Temperature Coefficient  
I
D = 250 μA, referenced to 25°C  
VGS = 10 V, ID = 6.1 A  
GS = 4.5 V, ID = 5.3 A  
mV/°C  
19  
23  
26  
33  
V
rDS(on)  
Static Drain to Source On Resistance  
Forward Transconductance  
mΩ  
VGS = 10 V, ID = 6.1 A,  
TJ = 125°C  
26  
30  
37  
gFS  
VDS = 5 V, ID = 6.1 A  
S
Dynamic Characteristics  
Ciss  
Coss  
Crss  
Rg  
Input Capacitance  
510  
170  
22  
710  
240  
30  
pF  
pF  
pF  
Ω
VDS = 15 V, VGS = 0 V,  
f = 1 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate Resistance  
0.1  
1.3  
2.6  
Switching Characteristics  
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Rise Time  
6
12  
10  
ns  
ns  
2
VDD = 15 V, ID = 6.1 A,  
V
GS = 10 V, RGEN = 6 Ω  
Turn-Off Delay Time  
Fall Time  
13  
2
24  
ns  
10  
ns  
Qg(TOT)  
Qg(TOT)  
Qgs  
Total Gate Charge  
Total Gate Charge  
Gate to Source Charge  
Gate to Drain “Miller” Charge  
VGS = 0 V to 10 V  
VGS = 0 V to 4.5 V  
7.7  
3.7  
1.4  
1.1  
10.8  
5.2  
nC  
nC  
nC  
nC  
VDD = 15 V,  
ID=6.1A  
Qgd  
Drain-Source Diode Characteristics  
VSD  
trr  
Source to Drain Diode Forward Voltage  
Reverse Recovery Time  
VGS = 0 V, IS = 6.1 A  
(Note 2)  
0.8  
14  
3
1.2  
25  
10  
V
ns  
nC  
IF = 6.1 A, di/dt = 100 A/μs  
Qrr  
Reverse Recovery Charge  
Notes:  
1: R  
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.  
θJA  
R
is guaranteed by design while R  
is determined by the user’s board design.  
θJC  
θCA  
b.175 °C/W when mounted on  
a minimum pad of 2 oz copper  
a. 78 °C/W when mounted on  
a 1 in pad of 2 oz copper  
2
2: Pulse Test: Pulse Width<300 us, Duty Cycle<2.0%.  
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.  
4. Pulsed Id please refer to Fig 11 SOA graph for more details.  
www.fairchildsemi.com  
©2016 Fairchild Semiconductor Corporation  
FDC021N30 Rev.1.0  
2
Typical Characteristics TJ = 25 °C unless otherwise noted.  
35  
8
6
4
2
0
VGS = 10 V  
PULSE DURATION = 80 μs  
VGS = 4.5 V  
VGS = 4 V  
30  
25  
20  
15  
10  
5
DUTY CYCLE = 0.5% MAX  
VGS = 3 V  
VGS = 3.5 V  
VGS = 3.5 V  
VGS = 4 V  
VGS = 3 V  
PULSE DURATION = 80 μs  
VGS = 10 V  
28  
VGS = 4.5 V  
DUTY CYCLE = 0.5% MAX  
0
0
1
2
3
4
5
0
7
14  
21  
35  
VDS, DRAIN TO SOURCE VOLTAGE (V)  
ID, DRAIN CURRENT (A)  
Figure 1. On-Region Characteristics  
Figure2. N o r m a l i z e d O n - R e s i s ta n c e  
vs. Drain Current and Gate Voltage  
1.5  
150  
ID = 6.1 A  
PULSE DURATION = 80 μs  
DUTY CYCLE = 0.5% MAX  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
VGS = 10 V  
ID = 6.1 A  
100  
50  
0
TJ = 125 o  
C
TJ = 25 o  
C
-75 -50 -25  
0
25 50 75 100 125 150  
2
4
6
8
10  
TJ, JUNCTION TEMPERATURE (oC)  
VGS, GATE TO SOURCE VOLTAGE (V)  
F i gu re 3 . N orma li zed On - Res is ta nc e  
vs. Junction Temperature  
Figure4. On-Resistance vs. Gate to  
Source Voltage  
35  
40  
VGS = 0 V  
PULSE DURATION = 80 μs  
10  
DUTY CYCLE = 0.5% MAX  
28  
VDS = 5 V  
TJ = 150 o  
C
1
21  
TJ = 25 o  
C
TJ = 150 o  
C
0.1  
14  
7
TJ = 25 o  
C
0.01  
0.001  
TJ = -55 o  
C
TJ = -55 o  
C
0
0
1
2
3
4
5
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
VGS, GATE TO SOURCE VOLTAGE (V)  
VSD, BODY DIODE FORWARD VOLTAGE (V)  
Figure 5. Transfer Characteristics  
Figure6. Source to Drain Diode  
Forward Voltage vs. Source Current  
www.fairchildsemi.com  
©2016 Fairchild Semiconductor Corporation  
FDC021N30 Rev.1.0  
3
Typical Characteristics TJ = 25 °C unless otherwise noted.  
10  
1000  
100  
10  
ID = 6.1 A  
8
Ciss  
VDD = 15 V  
6
Coss  
VDD = 10 V  
VDD = 20 V  
4
2
0
f = 1 MHz  
GS = 0 V  
V
Crss  
0
2
4
6
8
0.1  
1
10  
30  
VDS, DRAIN TO SOURCE VOLTAGE (V)  
Qg, GATE CHARGE (nC)  
Figure 7. Gate Charge Characteristics  
Figure8. C a p a c i t a n c e v s . D r a i n  
to Source Voltage  
5
4
3
2
1
0
20  
10  
VGS = 10 V  
TJ = 25 o  
C
TJ = 100 o  
C
VGS = 4.5 V  
TJ = 125 o  
C
RθJA = 175 oC/W  
1
0.001  
0.01  
0.1  
1
10  
25  
50  
75  
100  
125  
150  
TA, AMBIENT TEMPERATURE (oC)  
tAV, TIME IN AVALANCHE (ms)  
Figure9. U n c l a m p e d I n d u c t i v e  
Switching Capability  
Figure 10. Maximum Continous Drain Current  
vs. Ambient Temperature  
10000  
100  
10  
THIS AREA IS  
LIMITED BY rDS(on)  
SINGLE PULSE  
RθJA = 175 oC/W  
10 μs  
1000  
T
A = 25 oC  
100  
10  
1
100 μs  
1
1 ms  
10 ms  
100 ms  
1 s  
SINGLE PULSE  
0.1  
0.01  
T
J = MAX RATED  
θJA = 175 oC/W  
A = 25 o  
R
10 s  
DC  
CURVE BENT TO  
MEASURED DATA  
T
C
0.1  
10-5 10-4 10-3 10-2 10-1  
1
10  
100 1000  
0.01  
0.1  
1
10  
100200  
t, PULSE WIDTH (sec)  
VDS, DRAIN to SOURCE VOLTAGE (V)  
Figure 12. Single Pulse Maximum  
Power Dissipation  
Figure 11. Forward Bias Safe  
Operating Area  
www.fairchildsemi.com  
©2016 Fairchild Semiconductor Corporation  
FDC021N30 Rev.1.0  
4
Typical Characteristics TJ = 25 °C unless otherwise noted.  
2
DUTY CYCLE-DESCENDING ORDER  
1
D = 0.5  
0.2  
0.1  
0.1  
P
DM  
0.05  
0.02  
0.01  
0.01  
t
1
t
2
NOTES:  
(t) = r(t) x R  
Z
0.001  
0.0001  
θJA  
θJA  
SINGLE PULSE  
o
R
= 175 C/W  
θJA  
Peak T = P  
x Z (t) + T  
J
DM  
θJA A  
Duty Cycle, D = t / t  
1
2
10-5  
10-4  
10-3  
10-2  
10-1  
1
10  
100  
1000  
t, RECTANGULAR PULSE DURATION (sec)  
Figure 13. Junction-to-Ambient Transient Thermal Response Curve  
www.fairchildsemi.com  
©2016 Fairchild Semiconductor Corporation  
FDC021N30 Rev.1.0  
5
Dimensional Outline and Pad Layout  
SYMM  
C
L
0.95  
0.95  
3.00  
A
2.80  
1.00 MIN  
6
4
B
3.00  
2.60  
2.60  
1.70  
1.50  
1
3
0.50  
0.30  
0.95  
0.70 MIN  
M
0.20  
A B  
1.90  
LAND PATTERN RECOMMENDATION  
(0.30)  
1.10 MAX  
SEE DETAIL A  
1.00  
0.70  
C
0.10  
0.10  
0.00  
0.20  
0.08  
C
GAGE PLANE  
0.25  
NOTES: UNLESS OTHERWISE SPECIFIED  
A) THIS PACKAGE CONFORMS TO JEDEC MO-193.  
VAR. AA, ISSUE C, DATED JANUARY 2000.  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C) DIMENSIONING AND TOLERANCING  
PER ASME Y14.5M - 2009.  
D) DRAWING FILE NAME: MKT-MA06AREV5  
0.55  
0.35  
SEATING PLANE  
0.60 REF  
DETAIL A  
SCALE: 50X  
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without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
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cifically the warranty therein, which covers Fairchild products.  
www.fairchildsemi.com  
©2016 Fairchild Semiconductor Corporation  
FDC021N30 Rev.1.0  
6
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intended to be an exhaustive list of all such trademarks.  
®
AccuPower™  
F-PFS™  
FRFET  
OPTOPLANAR  
®*  
®
AttitudeEngine™  
®
®
Global Power ResourceSM  
GreenBridge™  
Green FPS™  
tm  
Awinda  
®
TinyBoost  
TinyBuck  
®
AX-CAP *  
Power Supply WebDesigner™  
®
®
BitSiC™  
PowerTrench  
TinyCalc™  
Build it Now™  
CorePLUS™  
CorePOWER™  
CROSSVOLT™  
CTL™  
Green FPS™ e-Series™  
Gmax™  
GTO™  
IntelliMAX™  
ISOPLANAR™  
PowerXS™  
®
TinyLogic  
Programmable Active Droop™  
TINYOPTO™  
TinyPower™  
TinyPWM™  
TinyWire™  
®
QFET  
QS™  
Quiet Series™  
Current Transfer Logic™  
Marking Small Speakers Sound Louder RapidConfigure™  
TranSiC™  
®
DEUXPEED  
and Better™  
MegaBuck™  
MICROCOUPLER™  
MicroFET™  
TriFault Detect™  
TRUECURRENT *  
Dual Cool™  
®
®
EcoSPARK  
Saving our world, 1mW/W/kW at a time™  
SignalWise™  
μSerDes™  
EfficentMax™  
ESBC™  
MicroPak™  
SmartMax™  
MicroPak2™  
MillerDrive™  
MotionMax™  
SMART START™  
®
®
Solutions for Your Success™  
UHC  
®
®
SPM  
Ultra FRFET™  
UniFET™  
VCX™  
VisualMax™  
VoltagePlus™  
XS™  
Fairchild  
®
®
MotionGrid  
STEALTH™  
Fairchild Semiconductor  
FACT Quiet Series™  
®
®
MTi  
SuperFET  
®
®
MTx  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
FACT  
®
MVN  
FastvCore™  
FETBench™  
FPS™  
®
mWSaver  
®
OptoHiT™  
OPTOLOGIC  
SupreMOS  
Xsens™  
®
®
SyncFET™  
仙童  
Sync-Lock™  
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.  
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Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Datasheet contains the design specifications for product development. Specifications  
may change in any manner without notice.  
Advance Information  
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Datasheet contains preliminary data; supplementary data will be published at a later  
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Not In Production  
Rev. I77  
www.fairchildsemi.com  
7
©2016 Fairchild Semiconductor Corporation  
FDC021N30 Rev.1.0  
SYMM  
C
L
0.95  
0.95  
C
3.00  
2.80  
A
1.00 MIN  
6
4
B
3.00  
2.60  
2.60  
1.70  
1.50  
C
1
3
0.50  
0.30  
0.95  
0.70 MIN  
M
0.20  
A B  
1.90  
LAND PATTERN RECOMMENDATION  
SEE DETAIL A  
(0.30)  
1.10 MAX  
H
1.00  
0.70  
C
0.10  
0.20  
0.08  
0.10  
0.00  
NOTES: UNLESS OTHERWISE SPECIFIED  
A) THIS PACKAGE CONFORMS TO JEDEC MO-193.  
VAR. AA, ISSUE E.  
C
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C PACKAGE LENGTH DOES NOT INCLUDE MOLD  
FLASH, PROTRUSIONS OR GATE BURRS. MOLD  
FLASH, PROTRUSIONS OR GATE BURRS SHALL  
NOT EXCEED 0.25mm PER END. PACKAGE WIDTH  
DOES NOT INCLUDE INTERLEAD FLASH OR  
PROTRUSION. INTERLEAD FLASH OR  
GAGE PLANE  
0.25  
8°  
0°  
PROTRUSION SHALL NOT EXCEED 0.25mm PER  
SIDE. PACKAGE LENGTH AND WIDTH DIMENSIONS  
ARE DETERMINED AT DATUM H.  
D) DRAWING FILE NAME: MKT-MA06AREVF  
0.55  
0.35  
SEATING PLANE  
0.60 REF  
DETAIL A  
SCALE: 50X  
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