FDD10AN06A0 [ONSEMI]
N 沟道,PowerTrench® MOSFET,60V,50A,10.5mΩ;型号: | FDD10AN06A0 |
厂家: | ONSEMI |
描述: | N 沟道,PowerTrench® MOSFET,60V,50A,10.5mΩ PC 开关 晶体管 |
文件: | 总14页 (文件大小:388K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET – N-Channel,
POWERTRENCH)
V
R
MAX
I MAX
D
DSS
DS(on)
60 V
10.5 mW @ 10 V
50 A
60 V, 50 A, 10.5 mW
DRAIN
(FLANGE)
FDD10AN06A0
GATE
SOURCE
Features
• R
= 9.4 mW (Typ.), V = 10 V, I = 50 A
GS D
DS(on)
DPAK3 (TO−252 3 LD)
CASE 369AS
• Q (tot) = 28 nC (Typ.), V = 10 V
g
GS
• Low Miller Charge
• Low Qrr Body Diode
MARKING DIAGRAM
• UIS Capability (Single Pulse and Repetitive Pulse)
• This Device is Pb−Free, Halide Free and is RoHS Compliant
&Z&3&K
FDD10AN0
6A0
Applications
• Motor / Body Load Control
• ABS Systems
&Z
&3
&K
= Assembly Plant Code
= 3−Digit Date Code
= 2−Digits Lot Run Traceability Code
• Powertrain Management
• Injection Systems
FDD10AN06A0 = Specific Device Code
• DC−DC Converters and Off−line UPS
• Distributed Power Architectures and VRMs
• Primary Switch for 12 V and 24 V Systems
D
MOSFET MAXIMUM RATINGS (T = 25°C, unless otherwise noted)
C
G
Symbol
Parameter
Drain to Source Voltage
Ratings
60
Unit
V
S
V
DSS
N−Channel MOSFET
V
GS
Gate to Source Voltage
20
V
I
Drain Current
Continuous (T < 115°C, V = 10 V)
Continuous (T
A
D
50
11
C
GS
= 25°C, V = 10 V,
amb
GS
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
R
= 52°C/W)
q
JA
Pulsed
Figure 4
429
E
AS
Single Pulse Avalanche Energy (Note 1)
Power Dissipation
mJ
W
P
135
D
Derate above 25°C
0.9
W/°C
°C
T , T
Operating and Storage Temperature
−55 to 175
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Starting T = 25°C, L = 8.58 mH, I = 10 A.
J
AS
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
June, 2023 − Rev. 4
FDD10AN06A0/D
FDD10AN06A0
THERMAL CHARACTERISTICS (T = 25°C, unless otherwise noted)
C
Symbol
Parameter
Ratings
1.11
Unit
R
q
JC
Thermal Resistance Junction to Case, TO−252
°C/W
R
Thermal Resistance Junction to Ambient, TO−252
Thermal Resistance Junction to Ambient, TO−252, 1 in Copper Pad Area
100
q
JA
JA
2
R
q
52
°C/W
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
I
= 250 mA, V = 0 V
60
−
−
−
−
−
−
V
VDSS
D
GS
I
V
V
V
= 50 V, V = 0 V
1
mA
DSS
DS
DS
GS
GS
= 50 V, V = 0 V, T = 150°C
−
250
100
GS
C
I
Gate to Source Leakage Current
=
20 V
−
nA
GSS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
= V , I = 250 mA
2
−
−
−
4
V
GS(TH)
GS
DS D
R
I
D
D
= 50 A, V = 10 V
0.0094
0.020
0.0105
0.023
W
DS(on)
GS
I
= 50 A, V = 10 V, T = 175°C
GS
J
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 25 V, V = 0 V, f = 1 MHz
−
−
−
−
1840
340
110
28
−
−
pF
pF
pF
nC
ISS
DS
GS
C
Output Capacitance
OSS
RSS
C
Reverse Transfer Capacitance
Total Gate Charge at 10 V
−
Q
g(TOT)
V
GS
= 0 V to 10 V, V = 30 V, I = 50 A,
37
DD
D
I = 1.0 mA
g
Q
g(TH)
Threshold Gate Charge
V
= 0 V to 2 V, V = 30 V, I = 50 A,
−
3.5
4.6
nC
GS
DD
D
I = 1.0 mA
g
Q
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V
DD
= 30 V, I = 50 A, I = 1.0 mA
−
−
−
9.8
6.4
7.8
−
−
−
nC
nC
nC
gs
D
g
Q
gs2
Q
gd
SWITCHING CHARACTERISTICS (V = 10 V)
GS
t
Turn−On Time
Turn−On Delay Time
Rise Time
V
DD
V
GS
= 30 V, I = 50 A
−
−
−
−
−
−
−
8
131
−
ns
ns
ns
ns
ns
ns
ON
D
= 10 V, R = 10 W
GS
t
d(ON)
t
r
79
32
32
−
−
t
Turn−Off Delay Time
Fall Time
−
d(OFF)
t
f
−
t
Turn−Off Time
97
OFF
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Voltage
I
I
I
I
= 50 A
= 25 A
−
−
−
−
−
−
−
−
1.25
1.0
27
V
V
SD
SD
SD
SD
SD
t
Reverse Recovery Time
= 50 A, dI /dt = 100 A/ms
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 50 A, dI /dt = 100 A/ms
23
RR
SD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDD10AN06A0
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted)
C
1.2
1.0
0.8
0.6
0.4
0.2
80
CURRENT LIMITED
BY PACKAGE
60
40
20
0
0
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
101
101
T , CASE TEMPERATURE (°C)
T , CASE TEMPERATURE (°C)
C
C
Figure 1. Normalized Power Dissipation vs.
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs.
Case Temperature
2
DUTY CYCLE − DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
1
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t / t
1
2
SINGLE PULSE
10−4
PEAK T = P
x Z
x R
+ T
JC C
q
q
J
DM
JC
0.01
10−5
10−3
10−2
10−1
100
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
T
C
= 25°C
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25°C DERATE PEAK
CURRENT AS FOLLOWS:
175 * TC
Ǹ
I + I25 ƪ ƫ
150
V
GS
= 10 V
100
40
10−5
10−4
10−3
10−2
10−1
100
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
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3
FDD10AN06A0
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)
C
500
500
100
If R = 0
t
AV
= (L) (I ) / (1.3 x RATED BV
− V
)
AS
DSS
DD
10 ms
100 ms
If R ≠ 0
= (L / R) ln [(I x R) / (1.3 x RATED BV
t
AV
− V ) + 1]
DD
AS
DSS
100
10
1
1 ms
10
1
STARTING T = 25°C
J
OPERATION IN THIS
AREA MAY BE LIMITED
BY R
DS(on)
10 ms
STARTING T = 150°C
J
SINGLE PULSE
T = MAX RATED
DC
J
T
C
= 25°C
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
0.01
0.1
t , TIME IN AVALANCHE (ms)
AV
1
10
V
DS
NOTE: Refer to onsemi Application Notes AN7514 and AN7515
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching Capability
100
100
PULSE DURATION = 80 ms
V
GS
= 10 V
V
GS
= 7 V
DUTY CYCLE = 0.5% MAX
V
DD
= 15 V
75
50
25
0
75
50
25
0
V
V
= 6 V
= 5 V
GS
T = 25°C
J
GS
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
T = 175°C
J
T = −55°C
J
T
C
= 25°C
3
4
5
6
7
0
0.5
1.0
1.5
2.0
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
18
16
14
12
10
8
2.5
2.0
1.5
1.0
0.5
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
GS
= 6 V
V
GS
= 10 V
V
= 10 V, I = 50 A
GS
D
0
10
20
30
40
50
−80
−40
0
40
80
120
160
200
I , DRAIN CURRENT (A)
D
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Drain to Source On Resistance vs.
Drain Current
Figure 10. Normalized Drain to Source On Resistance
vs. Junction Temperature
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FDD10AN06A0
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)
C
1.4
1.2
1.0
0.8
0.6
0.4
1.2
V
= V , I = 250 mA
I = 250 mA
D
GS
DS
D
1.1
1.0
0.9
−80
−40
0
40
80
120
160
200
−80
−40
0
40
80
120
160
200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Normalized Gate Threshold Voltage vs.
Junction Temperature
Figure 12. Normalized Drain to Source Breakdown
Voltage vs. Junction Temperature
10
3000
V
DD
= 30 V
C
= C + C
GS GD
ISS
8
6
4
2
0
1000
C
@ C + C
DS GD
OSS
C
= C
GD
RSS
WAVEFORMS IN
DESCENDING ORDER:
100
50
I
D
I
D
= 50 A
= 11 A
V
GS
= 0 V, f = 1 MHz
1
0.1
10
60
0
5
10
15
20
25
30
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 13. Capacitance vs. Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
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5
FDD10AN06A0
TEST CIRCUITS AND WAVEFORMS
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
R
REQUIRED PEAK I
G
AS
V
DD
−
V
GS
DUT
t
P
I
0 V
AS
0
0.01 W
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
Q
g(TOT)
V
DS
V
DD
V
DS
V
GS
L
V
= 10 V
GS
V
GS
Q
+
gs2
V
DD
−
V
= 2 V
DUT
GS
0
I
Q
g(REF)
g(TH)
Q
Q
gs
gd
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
t
t
V
ON
OFF
t
d(OFF)
DS
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
−
90%
50%
DUT
R
GS
V
0
GS
50%
PULSE WIDTH
10%
V
GS
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
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6
FDD10AN06A0
THERMAL RESISTANCE VS. MOUNTING PAD AREA
The maximum rated junction temperature, T , and the
can be evaluated using the onsemi device Spice thermal
JM
thermal resistance of the heat dissipating path determines
model or manually utilizing the normalized maximum
transient thermal impedance curve.
the maximum allowable device power dissipation, P , in
DM
an application. Therefore the application’s ambient
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and Equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
temperature, T (°C), and thermal resistance R
(°C/W)
qJA
A
must be reviewed to ensure that T is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
ǒT
Ǔ
JM * TA
PDM
+
23.84
(eq. 1)
RqJA + 33.32 )
RqJA
(eq. 2)
(0.268 ) Area)
In using surface mount devices such as the TO−252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
Area in Inches Squared
154
RqJA + 33.32 )
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
is
(eq. 3)
(1.73 ) Area)
DM
Area in Centimeters Squared
1. Mounting pad area onto which the device is
attached and whether there is copper on one side
or both sides of the board.
2. The number of copper layers and the thickness of
the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width,
125
R
= 33.32 + 23.84 / (0.268 + Area) eq.2
= 33.32 + 154 / (1.73 + Area) eq.3
q
JA
R
q
JA
100
75
the duty cycle and the transient thermal response of
the part, the board and the environment they are in.
onsemi provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
50
25
defines the R for the device as a function of the top copper
qJA
0.01
0.1
(0.645)
1
10
(64.5)
(component side) area. This is for a horizontally positioned
FR−4 board with 1 oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
(0.0645)
(6.45)
2
2
AREA, TOP COPPER AREA in (cm )
Figure 21. Thermal Resistance vs. Mounting Pad Area
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7
FDD10AN06A0
PSPICE ELECTRICAL MODEL
.SUBCKT FDD10AN06A0 2 1 3 ;
Ca 12 8 7e−10
rev July 2002
Cb 15 14 7e−10
Cin 6 8 1.8e−9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 67.2
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 3.2e−9
Ldrain 2 5 1.0e−9
Lsource 3 7 1.2e−9
RLgate 1 9 32
RLdrain 2 5 10
RLsource 3 7 12
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8
MweakMOD Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.35e−3
Rgate 9 20 3.6
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 6e−3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*250),7))}
.MODEL DbodyMOD D (IS=2E−11 N=1.06 RS=3.3e−3 TRS1=2.4e−3 TRS2=1.1e−6
+ CJO=1.25e−9 M=5.3e−1 TT=4.2e−8 XTI=3.9)
.MODEL DbreakMOD D (RS=2.7e−1 TRS1=1e−3 TRS2=−8.9e−6)
.MODEL DplcapMOD D (CJO=4.7e−10 IS=1e−30 N=10 M=0.44)
.MODEL MmedMOD NMOS (VTO=3.5 KP=5.5 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=3.6)
.MODEL MstroMOD NMOS (VTO=4.25 KP=80 IS=1e−30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.92 KP=0.03 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=36 RS=0.1)
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FDD10AN06A0
.MODEL RbreakMOD RES (TC1=9e−4 TC2=5e−7)
.MODEL RdrainMOD RES (TC1=2.5e−2 TC2=7.8e−5)
.MODEL RSLCMOD RES (TC1=1e−3 TC2=3.5e−5)
.MODEL RsourceMOD RES (TC1=1e−3 TC2=1e−6)
.MODEL RvthresMOD RES (TC1=−5.3e−3 TC2=−1.3e−5)
.MODEL RvtempMOD RES (TC1=−2.6e−3 TC2=1.3e−6)
.MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−8 VOFF=−5)
.MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−5 VOFF=−8)
.MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−2 VOFF=−1.5)
.MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.5 VOFF=−2)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written
by William J. Hepp and C. Frank Wheatley.
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
DBODY
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
−
+
50
−
17
18
−
RDRAIN
6
8
EBREAK
ESG
EVTHRES
+
16
21
+
−
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
6
+
−
18
22
MMED
9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
S2B
RVTEMP
19
−
S1B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
−
−
8
22
RVTHRES
Figure 22.
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9
FDD10AN06A0
SABER ELECTRICAL MODEL
REV July 2002
template FDD10AN06A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2e−11,nl=1.06,rs=3.3e−3,trs1=2.4e−3,trs2=1.1e−6,cjo=1.25e−9,m=5.3e−1,tt=4.2e−8,xti=3.9)
dp..model dbreakmod = (rs=2.7e−1,trs1=1e−3,trs2=−8.9e−6)
dp..model dplcapmod = (cjo=4.7e−10,isl=10e−30,nl=10,m=0.44)
m..model mmedmod = (type=_n,vto=3.5,kp=5.5,is=1e−30, tox=1)
m..model mstrongmod = (type=_n,vto=4.25,kp=80,is=1e−30, tox=1)
m..model mweakmod = (type=_n,vto=2.92,kp=0.03,is=1e−30, tox=1,rs=0.1) sw_vcsp..model s1amod =
(ron=1e−5,roff=0.1,von=−8,voff=−5)
sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−5,voff=−8)
sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−2,voff=−1.5)
sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=−1.5,voff=−2)
c.ca n12 n8 = 7e−10
c.cb n15 n14 = 7e−10
c.cin n6 n8 = 1.8e−9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 67.2
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 3.2e−9
l.ldrain n2 n5 = 1.0e−9
l.lsource n3 n7 = 1.2e−9
res.rlgate n1 n9 = 32
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 12
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9e−4,tc2=5e−7
res.rdrain n50 n16 = 1.35e−3, tc1=2.5e−2,tc2=7.8e−5
res.rgate n9 n20 = 3.6
res.rslc1 n5 n51 = 1e−6, tc1=1e−3,tc2=3.5e−5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6e−3, tc1=1e−3,tc2=1e−6
res.rvthres n22 n8 = 1, tc1=−5.3e−3,tc2=−1.3e−5
res.rvtemp n18 n19 = 1, tc1=−2.6e−3,tc2=1.3e−6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
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10
FDD10AN06A0
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 7))
}
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
DBREAK
50
−
RDRAIN
6
8
11
ESG
DBODY
EVTHRES
+
16
21
+
−
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
+
6
−
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
−
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
S2B
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
−
S1B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
−
−
8
22
RVTHRES
Figure 23.
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11
FDD10AN06A0
JUNCTION
th
SPICE ELECTRICAL MODEL
REV 23 July 2002
FDD10AN06A0T
CTHERM1 TH 6 3.2e−3
CTHERM2 6 5 3.3e−3
CTHERM3 5 4 3.4e−3
CTHERM4 4 3 3.5e−3
CTHERM5 3 2 6.4e−3
CTHERM6 2 TL 1.9e−2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 TH 6 5.5e−4
RTHERM2 6 5 5.0e−3
RTHERM3 5 4 4.5e−2
RTHERM4 4 3 1.5e−1
RTHERM5 3 2 3.37e−1
RTHERM6 2 TL 3.5e−1
5
4
3
2
SABER ELECTRICAL MODEL
SABER thermal model FDD10AN06A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.2e−3
ctherm.ctherm2 6 5 =3.3e−3
ctherm.ctherm3 5 4 =3.4e−3
ctherm.ctherm4 4 3 =3.5e−3
ctherm.ctherm5 3 2 =6.4e−3
ctherm.ctherm6 2 tl =1.9e−2
rtherm.rtherm1 th 6 =5.5e−4
rtherm.rtherm2 6 5 =5.0e−3
rtherm.rtherm3 5 4 =4.5e−2
rtherm.rtherm4 4 3 =1.5e−1
rtherm.rtherm5 3 2 =3.37e−1
rtherm.rtherm6 2 tl =3.5e−1
}
tl
CASE
Figure 24.
ORDERING INFORMATION
†
Device
Device Marking
Package
Reel Size
Tape Width
Shipping
FDD10AN06A0
FDD10AN06A0
DPAK3 (TO−252 3 LD)
(Pb−Free, Halide Free)
330 mm
16 mm
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK3 (TO−252 3 LD)
CASE 369AS
ISSUE A
DATE 28 SEP 2022
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
AYWWZZ
XXXX = Specific Device Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ
= Assembly Lot Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON13810G
DPAK3 (TO−252 3 LD)
PAGE 1 OF 1
DESCRIPTION:
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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