FDD13AN06A0_技术文档

DATA SHEET

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MOSFET – N-Channel,

POWERTRENCH⁾

V

R

MAX

I MAX

D

DSS

DS(on)

60 V

13.5 mW @ 10 V

50 A

60 V, 50 A, 13 mW

D

FDD13AN06A0

G

S

Features

• R

• Q

= 11.5 mW (Typ.) @ V = 10 V, I = 50 A

GS D

DS(on)

G(tot)

DPAK3 (TO−252 3 LD)

CASE 369AS

= 22 nC (Typ.) @ V = 10 V

GS

• Low Miller Charge

• Low Q Body Diode

rr

MARKING DIAGRAM

• UIS Capability (Single Pulse and Repetitive Pulse)

• This Device is Pb−Free, Halide Free and is RoHS Compliant

&Z&3&K

FDD13AN0

6A0

Applications

• Consumer Appliances

• LED TV

• Synchronous Rectification

• Battery Protection Circuit

• Motor Drives and Uninterruptible Power Supplies

&Z

&3

&K

= Assembly Plant Code

= 3−Digit Date Code

= 2−Digits Lot Run Traceability Code

FDD13AN06A0 = Device Code

D

MOSFET MAXIMUM RATINGS (T = 25°C, unless otherwise noted)

C

Symbol

Parameter

Drain to Source Voltage

Ratings

60

Unit

V

DSS

V

GS

Gate to Source Voltage

20

V

G

I

Drain Current

A

D

Continuous (T < 80°C, V = 10 V)

50

9.9

C

GS

= 52°C/W)

Continuous (T = 25°C, V = 10 V,

A

S

R

q

JA

Pulsed

Figure 4

56

N−Channel

E

AS

Single Pulse Avalanche Energy (Note 1)

Power Dissipation

mJ

W

P

115

D

Derate above 25°C

0.77

W/°C

°C

ORDERING INFORMATION

See detailed ordering and shipping information on page 12 of

this data sheet.

T , T

Operating and Storage Temperature

−55 to 175

J

STG

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

THERMAL CHARACTERISTICS (T = 25°C, unless otherwise noted)

C

Symbol

Parameter

Ratings

Unit

R

q

JC

Thermal Resistance Junction to Case, Max.

D−PAK

1.3

°C/W

R

Thermal Resistance Junction to Ambient,

Max. D−PAK

100

52

q

JA

R

q

Thermal Resistance Junction to Ambient,

°C/W

2

Max. D−PAK, 1 in Copper Pad Area

1

Publication Order Number:

May, 2023 − Rev. 3

FDD13AN06A0/D

FDD13AN06A0

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

C

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

OFF CHARACTERISTICS

B

Drain to Source Breakdown Voltage

Zero Gate Voltage Drain Current

I

= 250 mA, V = 0 V

60

−

V

VDSS

D

GS

I

V

= 50 V, V = 0 V

1

mA

DSS

DS

GS

= 50 V, V = 0 V, T = 150°C

−

250

100

GS

C

I

Gate to Source Leakage Current

=

20 V

−

nA

GSS

ON CHARACTERISTICS

V

Gate to Source Threshold Voltage

Drain to Source On Resistance

V

= V , I = 250 mA

2

−

4

V

GS(TH)

GS

DS D

R

I

D

I

D

I

D

= 50 A, V = 10 V

0.0115

0.022

0.026

0.0135

0.034

0.030

W

DS(on)

GS

= 25 A, V = 6 V

GS

= 50 A, V = 10 V, T = 175°C

GS

J

DYNAMIC CHARACTERISTICS

C

Input Capacitance

V

= 25 V, V = 0 V, f = 1 MHz

−

1350

260

90

−

pF

nC

ISS

DS

GS

C

Output Capacitance

OSS

RSS

C

Reverse Transfer Capacitance

Total Gate Charge at 10 V

−

Q

g(TOT)

V

GS

= 0 V to 10 V, V = 30 V, I = 50 A,

22

29

DD

D

I = 1.0 mA

g

Q

g(TH)

Threshold Gate Charge

V

= 0 V to 2 V, V = 30 V, I = 50 A,

−

2.6

3.4

nC

GS

DD

D

I = 1.0 mA

g

Q

Gate to Source Gate Charge

Gate Charge Threshold to Plateau

Gate to Drain “Miller” Charge

V

DD

= 30 V, I = 50 A, I = 1.0 mA

−

8.2

5.6

6.4

−

nC

gs

D

g

Q

gs2

Q

gd

SWITCHING CHARACTERISTICS (V = 10 V)

GS

t

Turn−On Time

Turn−On Delay Time

Rise Time

V

DD

V

GS

= 30 V, I = 50 A

−

9

130

−

ns

ON

D

= 10 V, R = 12 W

GS

t

d(ON)

t

r

77

26

25

−

t

Turn−Off Delay Time

Fall Time

−

d(OFF)

t

f

−

t

Turn−Off Time

77

OFF

DRAIN−SOURCE DIODE CHARACTERISTICS

V

Source to Drain Diode Voltage

I

= 50 A

= 25 A

−

1.25

1.0

24

V

SD

t

Reverse Recovery Time

= 50 A, dI /dt = 100 A/ms

ns

nC

rr

SD

Q

Reverse Recovered Charge

= 50 A, dI /dt = 100 A/ms

15

RR

SD

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. Starting T = 25°C, L = 45 mH, I = 50 A.

J

AS

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2

FDD13AN06A0

TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted)

C

1.2

1.0

0.8

0.6

0.4

0.2

80

CURRENT LIMITED

BY PACKAGE

60

40

20

0

25

50

75

100

125

150

175

25

50

75

100

125

150

175

10¹

T , CASE TEMPERATURE (°C)

C

Figure 1. Normalized Power Dissipation vs.

Ambient Temperature

Figure 2. Maximum Continuous Drain Current vs.

Case Temperature

2

DUTY CYCLE − DESCENDING ORDER

0.5

0.2

0.1

0.05

0.02

0.01

1

P

DM

0.1

t

1

t

2

NOTES:

DUTY FACTOR: D = t / t

1

2

SINGLE PULSE

10⁻⁴

PEAK T = P

x Z

x R

+ T

JC C

q

J

DM

JC

0.01

10⁻⁵

10⁻³

10⁻²

10⁻¹

10⁰

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

800

T

C

= 25°C

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

FOR TEMPERATURES

ABOVE 25°C DERATE PEAK

CURRENT AS FOLLOWS:

175 * T_C

Ǹ

I + I₂₅ƪ ƫ

V

GS

= 10 V

150

100

10

10⁻⁵

10⁻⁴

10⁻³

10⁻²

10⁻¹

10⁰

t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

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3

FDD13AN06A0

TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)

C

1000

100

10

100

If R = 0

t

AV

= (L) (I ) / (1.3 x RATED BV

− V

)

AS

DSS

DD

10 ms

100 ms

1 ms

If R ≠ 0

= (L / R) ln [(I x R) / (1.3 x RATED BV

t

AV

− V ) + 1]

DD

AS

DSS

STARTING T = 25°C

J

10

OPERATION IN THIS

AREA MAY BE LIMITED

STARTING T = 150°C

J

10 ms

BY R

DS(on)

1

SINGLE PULSE

T = MAX RATED

DC

J

T

C

= 25°C

1

0.01

0.1

1

10

, DRAIN TO SOURCE VOLTAGE (V)

100

0.1

1

10

100

V

DS

t , TIME IN AVALANCHE (ms)

AV

NOTE: Refer to onsemi Application Notes AN7514 and AN7515

Figure 5. Forward Bias Safe Operating Area

Figure 6. Unclamped Inductive Switching Capability

100

PULSE DURATION = 80 ms

DUTY CYCLE = 0.5% MAX

T

C

= 25°C

V

= 20 V

= 10 V

GS

80

60

40

20

0

80

60

40

20

0

V

DD

= 15 V

GS

V

GS

= 6 V

PULSE DURATION = 80 ms

DUTY CYCLE = 0.5% MAX

T = 175°C

J

T = 25°C

J

T = −55°C

J

V

GS

= 5 V

3

4

5

6

7

0

0.5

1.0

1.5

2.0

V

GS

, GATE TO SOURCE VOLTAGE (V)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics

Figure 8. Saturation Characteristics

30

25

20

15

10

2.5

2.0

1.5

1.0

0.5

PULSE DURATION = 80 ms

DUTY CYCLE = 0.5% MAX

PULSE DURATION = 80 ms

DUTY CYCLE = 0.5% MAX

V

GS

= 6 V

V

GS

= 10 V

V

= 10 V, I = 50 A

D

GS

0

10

20

30

40

50

−80

−40

0

40

80

120

160

200

I , DRAIN CURRENT (A)

D

T , JUNCTION TEMPERATURE (°C)

J

Figure 9. Drain to Source On Resistance vs.

Drain Current

Figure 10. Normalized Drain to Source On Resistance

vs. Junction Temperature

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4

FDD13AN06A0

TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)

C

1.4

1.2

1.0

0.8

0.6

0.4

1.2

V

= V , I = 250 mA

I = 250 mA

D

GS

DS

D

1.1

1.0

0.9

−80

−40

0

40

80

120

160

200

−80

−40

0

40

80

120

160

200

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 11. Normalized Gate Threshold Voltage vs.

Junction Temperature

Figure 12. Normalized Drain to Source Breakdown

Voltage vs. Junction Temperature

10

3000

V

DD

= 30 V

8

6

4

2

0

C

= C + C

GS GD

ISS

1000

C

@ C + C

DS GD

OSS

C

= C

GD

RSS

WAVEFORMS IN

DESCENDING ORDER:

100

40

I

D

I

D

= 50 A

= 25 A

V

= 0 V, f = 1 MHz

1

GS

0.1

10

60

0

5

10

15

20

25

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

Q , GATE CHARGE (nC)

g

Figure 13. Capacitance vs. Drain to Source Voltage

Figure 14. Gate Charge Waveforms for Constant

Gate Currents

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5

FDD13AN06A0

TEST CIRCUITS AND WAVEFORMS

V

BV

DSS

DS

t

P

V

DS

L

I

AS

V

DD

VARY t TO OBTAIN

P

+

R

REQUIRED PEAK I

G

AS

V

DD

−

V

GS

DUT

t

P

I

0 V

AS

0

0.01 W

t

AV

Figure 15. Unclamped Energy Test Circuit

Figure 16. Unclamped Energy Waveforms

Q

g(TOT)

V

DS

V

DD

V

DS

V

GS

L

V

= 10 V

GS

V

GS

Q

+

gs2

V

DD

−

V

= 2 V

DUT

GS

0

I

Q

g(REF)

g(TH)

Q

gs

gd

I

g(REF)

0

Figure 17. Gate Charge Test Circuit

Figure 18. Gate Charge Waveforms

t

V

ON

OFF

t

d(OFF)

DS

t

d(ON)

t

f

r

R

L

V

DS

90%

+

V

GS

V

DD

10%

0

−

90%

50%

DUT

R

GS

V

0

GS

50%

PULSE WIDTH

10%

V

GS

Figure 19. Switching Time Test Circuit

Figure 20. Switching Time Waveforms

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6

FDD13AN06A0

THERMAL RESISTANCE VS. MOUNTING PAD AREA

The maximum rated junction temperature, T , and the

can be evaluated using the onsemi device Spice thermal

JM

thermal resistance of the heat dissipating path determines

model or manually utilizing the normalized maximum

transient thermal impedance curve.

the maximum allowable device power dissipation, P , in

DM

an application. Therefore the application’s ambient

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using

Equation 2 or 3. Equation 2 is used for copper area defined

in inches square and Equation 3 is for area in centimeters

square. The area, in square inches or square centimeters is

the top copper area including the gate and source pads.

temperature, T (°C), and thermal resistance R

(°C/W)

qJA

A

must be reviewed to ensure that T is never exceeded.

JM

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

ǒ_T

Ǔ

_JM* T_A

P_DM

+

23.84

(eq. 1)

R_qJA+ 33.32 )

R_qJA

(eq. 2)

(0.268 ) Area)

In using surface mount devices such as the TO−252

package, the environment in which it is applied will have a

significant influence on the part’s current and maximum

Area in Inches Squared

154

R_qJA+ 33.32 )

power dissipation ratings. Precise determination of P

complex and influenced by many factors:

is

(eq. 3)

(1.73 ) Area)

DM

Area in Centimeters Squared

1. Mounting pad area onto which the device is

attached and whether there is copper on one side

or both sides of the board.

2. The number of copper layers and the thickness of

the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width,

125

R

= 33.32 + 23.84 / (0.268 + Area) eq.2

= 33.32 + 154 / (1.73 + Area) eq.3

q

JA

R

q

JA

100

75

the duty cycle and the transient thermal response of

the part, the board and the environment they are in.

onsemi provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21

50

25

defines the R for the device as a function of the top copper

qJA

0.01

0.1

(0.645)

1

10

(64.5)

(component side) area. This is for a horizontally positioned

FR−4 board with 1 oz copper after 1000 seconds of steady

state power with no air flow. This graph provides the

necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse applications

(0.0645)

(6.45)

2

AREA, TOP COPPER AREA in (cm )

Figure 21. Thermal Resistance vs. Mounting Pad Area

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7

FDD13AN06A0

PSPICE ELECTRICAL MODEL

.SUBCKT FDD13AN06A0 2 1 3 ; rev August 2002

Ca 12 8 5.1e−10

Cb 15 14 5.8e−10

Cin 6 8 1.3e−9

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 65.40

Eds 14 8 5 8 1

Egs 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtemp 20 6 18 22 1

It 8 17 1

Lgate 1 9 5.2e−9

Ldrain 2 5 1.0e−9

Lsource 3 7 2.14e−9

RLgate 1 9 52

RLdrain 2 5 10

RLsource 3 7 21.4

Mmed 16 6 8 8 MmedMOD

Mstro 16 6 8 8 MstroMOD

Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 3.1e−3

Rgate 9 20 3.71

RSLC1 5 51 RSLCMOD 1e−6

RSLC2 5 50 1e3

Rsource 8 7 RsourceMOD 5.5e−3

Rvthres 22 8 RvthresMOD 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*160),6))}

.MODEL DbodyMOD D (IS=1.0E−11 N=1.08 RS=3.5e−3 TRS1=2.2e−3 TRS2=2.5e−9

+ CJO=.9e−9 M=5.1e−1 TT=1e−9 XTI=3.9)

.MODEL DbreakMOD D (RS=1.5e−1 TRS1=1e−3 TRS2=−8.9e−6)

.MODEL DplcapMOD D (CJO=4.1e−10 IS=1e−30 N=10 M=0.45)

.MODEL MmedMOD NMOS (VTO=3.5 KP=6 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=3.71)

.MODEL MstroMOD NMOS (VTO=4.3 KP=50 IS=1e−30 N=10 TOX=1 L=1u W=1u)

.MODEL MweakMOD NMOS (VTO=2.91 KP=0.05 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=3.71e+1 RS=0.1)

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8

FDD13AN06A0

.MODEL RbreakMOD RES (TC1=9e−4 TC2=−5e−7)

.MODEL RdrainMOD RES (TC1=1.3e−2 TC2=5.2e−5)

.MODEL RSLCMOD RES (TC1=1.8e−3 TC2=1.7e−5)

.MODEL RsourceMOD RES (TC1=1e−3 TC2=1e−6)

.MODEL RvthresMOD RES (TC1=−5.3e−3 TC2=−1.0e−5)

.MODEL RvtempMOD RES (TC1=−2.5e−3 TC2=1e−6)

.MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−5 VOFF=−2)

.MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−2 VOFF=−5)

.MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.5 VOFF=.5)

.MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=.5 VOFF=−1.5)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET

Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written

by William J. Hepp and C. Frank Wheatley.

LDRAIN

DPLCAP

DRAIN

2

5

10

RLDRAIN

DBODY

RSLC1

51

DBREAK

+

RSLC2

5

ESLC

11

51

−

+

50

−

17

18

−

RDRAIN

6

8

EBREAK

ESG

EVTHRES

+

16

21

+

−

19

8

MWEAK

LGATE

EVTEMP

RGATE

GATE

1

6

+

−

18

22

MMED

9

20

MSTRO

8

RLGATE

LSOURCE

CIN

SOURCE

3

7

RSOURCE

RLSOURCE

S1A

S2A

RBREAK

12

15

13

8

14

13

17

18

S2B

RVTEMP

19

−

S1B

13

CB

CA

IT

14

+

VBAT

6

8

5

8

EGS

EDS

+

−

8

22

RVTHRES

Figure 22.

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9

FDD13AN06A0

SABER ELECTRICAL MODEL

rev August 2002

template FDD13AN06A0 n2,n1,n3

electrical n2,n1,n3

{

var i iscl

dp..model dbodymod = (isl=1.0e−11,nl=1.08,rs=3.5e−3,trs1=2.2e−3,trs2=2.5e−9,cjo=.9e−9,m=5.1e−1,tt=1e−9,xti=3.9)

dp..model dbreakmod = (rs=1.5e−1,trs1=1e−3,trs2=−8.9e−6)

dp..model dplcapmod = (cjo=4.1e−10,isl=10e−30,nl=10,m=0.45)

m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e−30, tox=1)

m..model mstrongmod = (type=_n,vto=4.3,kp=50,is=1e−30, tox=1)

m..model mweakmod = (type=_n,vto=2.91,kp=0.05,is=1e−30, tox=1,rs=0.1)

sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−5,voff=−2)

sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−2,voff=−5)

sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−1.5,voff=.5)

sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=.5,voff=−1.5)

c.ca n12 n8 = 5.1e−10

c.cb n15 n14 = 5.8e−10

c.cin n6 n8 = 1.3e−9

dp.dbody n7 n5 = model=dbodymod

dp.dbreak n5 n11 = model=dbreakmod

dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 65.40

spe.eds n14 n8 n5 n8 = 1

spe.egs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evthres n6 n21 n19 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1

l.lgate n1 n9 = 5.2e−9

l.ldrain n2 n5 = 1.0e−9

l.lsource n3 n7 = 2.14e−9

res.rlgate n1 n9 = 52

res.rldrain n2 n5 = 10

res.rlsource n3 n7 = 21.4

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=9e−4,tc2=−5e−7

res.rdrain n50 n16 = 3.1e−3, tc1=1.3e−2,tc2=5.2e−5

res.rgate n9 n20 = 3.71

res.rslc1 n5 n51 = 1e−6, tc1=1.8e−3,tc2=1.7e−5

res.rslc2 n5 n50 = 1e3

res.rsource n8 n7 = 5.5e−3, tc1=1e−3,tc2=1e−6

res.rvthres n22 n8 = 1, tc1=−5.3e−3,tc2=−1.0e−5

res.rvtemp n18 n19 = 1, tc1=−2.5e−3,tc2=1e−6

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

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10

FDD13AN06A0

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51−>n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/160))** 6))

}}

LDRAIN

DPLCAP

DRAIN

2

5

10

RLDRAIN

RSLC1

51

RSLC2

ISCL

DBREAK

50

−

RDRAIN

6

8

11

ESG

DBODY

EVTHRES

+

16

21

+

−

19

8

MWEAK

LGATE

EVTEMP

RGATE

GATE

1

+

6

−

18

22

EBREAK

+

MMED

9

20

MSTRO

8

17

18

−

RLGATE

LSOURCE

CIN

SOURCE

3

7

RSOURCE

RLSOURCE

S1A

S2A

S2B

RBREAK

12

15

13

8

14

13

17

18

RVTEMP

19

−

S1B

13

CB

CA

IT

14

+

VBAT

6

8

5

8

EGS

EDS

+

−

8

22

RVTHRES

Figure 23.

www.onsemi.com

11

FDD13AN06A0

JUNCTION

th

PSPICE ELECTRICAL MODEL

REV 22 August 2002

FDD13AN06A0T

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

CTHERM1

CTHERM1 TH 6 9.7e−4

CTHERM2 6 5 6.2e−3

CTHERM3 5 4 4.6e−3

CTHERM4 4 3 4.9e−3

CTHERM5 3 2 8e−3

6

CTHERM2

CTHERM3

CTHERM4

CTHERM5

CTHERM6

CTHERM6 2 TL 4.2e−2

5

RTHERM1 TH 6 5.24e−2

RTHERM2 6 5 10.08e−2

RTHERM3 5 4 4.28e−1

RTHERM4 4 3 1.8e−1

RTHERM5 3 2 1.9e−1

RTHERM6 2 TL 2.1e−1

4

3

2

SABER ELECTRICAL MODEL

SABER thermal model FDD13AN06A0T

template thermal_model th tl

thermal_c th, tl

{

ctherm.ctherm1 th 6 =9.7e−4

ctherm.ctherm2 6 5 =6.2e−3

ctherm.ctherm3 5 4 =4.6e−3

ctherm.ctherm4 4 3 =4.9e−3

ctherm.ctherm5 3 2 =8e−3

ctherm.ctherm6 2 tl =4.2e−2

rtherm.rtherm1 th 6 =5.24e−2

rtherm.rtherm2 6 5 =10.08e−2

rtherm.rtherm3 5 4 =4.28e−1

rtherm.rtherm4 4 3 =1.8e−1

rtherm.rtherm5 3 2 =1.9e−1

rtherm.rtherm6 2 tl =2.1e−1

}

tl

CASE

Figure 24.

PACKAGE MARKING AND ORDERING INFORMATION

†

Device

Device Marking

Package

Reel Size

330 mm

Tape Width

Shipping

FDD13AN06A0

DPAK3 (TO−252 3 LD)

(Pb−Free, Halide Free)

16 mm

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States

and/or other countries.

www.onsemi.com

12

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

DPAK3 (TO−252 3 LD)

CASE 369AS

ISSUE A

DATE 28 SEP 2022

GENERIC

MARKING DIAGRAM*

XXXXXX

AYWWZZ

XXXX = Specific Device Code

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

A

Y

= Assembly Location

= Year

WW = Work Week

ZZ

= Assembly Lot Code

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

98AON13810G

DPAK3 (TO−252 3 LD)

PAGE 1 OF 1

DESCRIPTION:

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

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


型号：	FDD13AN06A0
厂家：	ONSEMI
描述：	N 沟道，PowerTrench® MOSFET，60V，50A，13mΩ 开关晶体管
文件：	总14页 (文件大小：387K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FDD13AN06A0 [ONSEMI]

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