FDG316P [ONSEMI]
P 沟道，逻辑电平，PowerTrench® MOSFET，-30 V，-1.6 A，190 mΩ;
| 型号： | FDG316P |
| 厂家： | 
ONSEMI |
| 描述： | P 沟道，逻辑电平，PowerTrench® MOSFET，-30 V，-1.6 A，190 mΩ PC 开关 光电二极管 晶体管 |
| 文件： | 总7页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET– P-Channel, Logic
Level, POWERTRENCH)
FDG316P
General Description
This P−Channel Logic Level MOSFET is produced using
ON Semiconductor’s advanced POWERTRENCH process that has
been especially tailored to minimize on−state resistance and yet
maintain superior switching performance.
These devices are well suited for low voltage and battery powered
applications where low in−line power loss and fast switching are
required.
www.onsemi.com
S
D
D
G
D
D
Features
SC−88/SC70−6/SOT−363
CASE 419B−02
• −1.6 A, −30 V
♦ R
♦ R
= 0.19 W @ V = −10 V
GS
DS(ON)
= 0.30 W @ V = −4.5 V
DS(ON)
GS
MARKING DIAGRAM
• Low Gate Charge (3.5 nC Typical)
• High Performance Trench Technology for Extremely Low R
• Compact Industry Standard SC70−6 Surface Mount Package
• These Devices are Pb−Free and are RoHS Compliant
DS(ON)
36M
Applications
36
M
= Specific Device Code
= Assembly Operation Month
• DC/DC Converter
• Load Switch
• Power Management
PIN CONNECTIONS
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
1
6
5
4
Symbol
Parameter
Drain−Source Voltage
Ratings
−30
Units
V
DSS
V
GSS
V
V
A
2
3
Gate−Source Voltage
20
I
D
Drain Current
Continuous
(Note 1a)
−1.6
Pulsed
−6
0.75
P
Power Dissipation for
Single Operation
(Note 1a)
(Note 1b)
W
D
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
0.48
T , T
J
Operating and Storage Junction
Temperature Range
−55 to +150
°C
stg
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
Unit
R
Thermal Resistance, Junction−to−Ambient (Note 1b)
260
_C/W
q
JA
1. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
q
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design.
q
q
JC
CA
2
a) 170°C/W when mounted on a 1 in pad of 2 oz copper.
b) 260°C/W when mounted on a minimum pad.
© Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
FDG316P/D
June, 2020 − Rev. 4
FDG316P
PACKAGE MARKING AND ORDERING INFORMATION
†
Device Marking
Device
Reel Size
Tape Width
Shipping
36
FDG316P
7”
8 mm
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
V
I
= 0 V, I = −250 mA
−30
−
−
−
V
DSS
GS
D
DBV
/ DT
Breakdown Voltage Temperature
Coefficient
= −250 mA, Referenced to 25_C
−
−34
mV/_C
DSS
J
D
I
Zero Gate Voltage Drain Current
Gate−Body Leakage Forward
Gate−Body Leakage Reverse
V
DS
V
GS
V
GS
= −24 V, V = 0 V
−
−
−
−
−
−
−1
100
mA
nA
nA
DSS
GS
I
= 16 V, V = 0 V
DS
GSS
GSS
I
= −16 V, V = 0 V
−100
DS
ON CHARACTERISTICS (Note 2)
V
Gate Threshold Voltage
V
I
= V , I = −250 mA
−1
−1.6
−3
V
GS(th)
DS
GS
D
DV
/ DT
Gate Threshold Voltage
Temperature Coefficient
= −250 mA, Referenced to 25_C
−
3.5
−
mV/_C
GS(th)
J
D
R
Static Drain−Source
On−Resistance
V
GS
V
GS
V
GS
= −10 V, I = −1.6 A
−
−
−
0.16
0.22
0.23
0.19
0.31
0.30
W
DS(on)
D
= −10 V, I = −1.6 A, T = 125_C
D
J
= −4.5 V, I = −1.3 A
D
I
On−State Drain Current
V
GS
V
DS
= −4.5 V, V = −5 V
−3
−
−
−
A
S
D(on)
DS
g
FS
Forward Transconductance
= −5 V, I = −0.5 A
−
3
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= −15 V, V = 0 V, f = 1.0 MHz
−
−
−
165
60
−
−
−
pF
pF
pF
iss
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
25
rss
SWITCHING CHARACTERISTICS (Note 2)
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
V
V
= −15 V, I = −1 A,
−
−
−
−
−
−
−
8
9
20
20
30
10
5
ns
ns
d(on)
DD
GS
D
= −10 V, R
= 6 W
GEN
t
r
t
14
2
ns
d(off)
t
f
ns
Q
V
DS
V
GS
= −15 V, I = −1.6 A,
3.5
0.6
0.8
nC
nC
nC
g
D
= −10 V
Q
−
gs
gd
Q
−
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain−Source Diode Forward Current
I
S
−
−
−
−0.42
−1.2
A
V
V
SD
Drain−Source Diode Forward
Voltage
V
GS
= 0 V, I = −0.42 A (Note 2)
0.75
S
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%
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2
FDG316P
TYPICAL PERFORMANCE CHARACTERISTICS
2
10
8
VGS = −10 V
−8.0 V
−7.0 V
−6 V
1.8
−5.0 V
VGS = −4.0 V
−4.5 V
1.6
1.4
1.2
1
−4.5 V
−5.0 V
6
4
2
0
−4.0 V
−3.5 V
−6.0 V
−7.0 V
−8.0 V
−10 V
−3.0 V
−2.5 V
0.8
0
1
2
3
4
5
0
2
4
6
8
10
−VDS, DRAIN−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 1. On−Region Characteristics
Figure 2. On−Resistance Variation with
Drain Current and Gate Voltage
1.6
1.4
1.2
1
0.6
ID= −1.6 A
VGS = −10 V
ID = −0.8 A
0.5
0.4
0.3
0.2
0.1
0
TA = 125°C
TA = 25°C
0.8
0.6
2
4
6
8
10
−50
−25
0
25
50
75
100
125
150
°
−VGS, GATE TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE ( C)
Figure 3. On−Resistance Variation with
Figure 4. On−Resistance Variation with
Gate−to−Source Voltage
Temperature
10
10
1
VDS = −5 V
VGS = 0 V
°
TA = −55 C
°
25 C
°
125C
8
6
4
2
0
°
TA = 125 C
°
25 C
0.1
°
−55 C
0.01
0.001
0.0001
0
2
4
6
8
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
−VGS, GATE TO SOURCE VOLTAGE (V)
−VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature
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3
FDG316P
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
10
8
250
200
f = 1 MHz
= 0 V
ID = −1.6 A
V
GS
VDS= 5 V
10 V
CISS
15 V
6
150
100
50
4
COSS
CRSS
2
0
0
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
Qg, GATE CHARGE (nC)
−VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance Characteristics
10
30
24
18
12
6
RDS(ON) LIMIT
SINGLE PULSE
R
= 260°C/W
q
JA
1 ms
10 ms
T
A
= 25°C
1
0.1
100 ms
1 s
10 s
DC
V
= −10 V
GS
SINGLE PULSE
R
= 260°C/W
q
JA
T
A
= 25°C
0.01
0
0.1
1
10
100
0.0001 0.001
0.01
0.1
1
10
100
1000
−VDS, DRAIN−SOURCE VOLTAGE (V)
SINGLE PULSE TIME (sec)
Figure 10. Single Pulse Maximum Power
Dissipation
Figure 9. Maximum Safe Operating Area
1
D = 0.5
0.5
R
R
(t) = r(t) * R
= 260°C/W
q
q
q
JA
JA
0.2
0.1
JA
0.1
P(pk)
0.05
0.01
0.02
0.05
t1
t 2
Single Pulse
T
− T = P * R
A
(t)
q
J
JA
0.01
Duty Cycle, D = t / t
1
2
0.005
0.0001
0.001
0.01
0.1
1
10
100
300
t1, TIME (sec)
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
Figure 11. Transient Thermal Response Curve
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United
States and/or other countries.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
DATE 11 DEC 2012
SCALE 2:1
2X
aaa H
D
NOTES:
D
H
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
D
GAGE
PLANE
6
1
5
2
4
3
L
L2
E1
E
DETAIL A
aaa
C
2X
2X 3 TIPS
bbb H
D
e
MILLIMETERS
DIM MIN NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−− 0.043
−−− 0.004
6X b
B
TOP VIEW
A
−−−
−−−
1.10
A1 0.00
A2 0.70
0.10 0.000
M
ddd
C A-B D
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1 1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6
6X
0.30
XXXMG
6X
0.66
G
1
2.50
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
0.65
(Note: Microdot may be in either location)
PITCH
*Date Code orientation and/or position may
vary depending upon manufacturing location.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1. ANODE 2
2. N/C
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
PIN 1. ANODE
2. ANODE
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
3. COLLECTOR
3. CATHODE 1
4. ANODE 1
5. N/C
4. EMITTER
5. BASE
6. COLLECTOR 2
6. ANODE
6. CATHODE
6. CATHODE 2
STYLE 7:
STYLE 8:
CANCELLED
STYLE 9:
STYLE 10:
STYLE 11:
STYLE 12:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
4. SOURCE 1
5. DRAIN 1
6. GATE 2
4. DRAIN 1
5. DRAIN 2
6. GATE 2
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
5. BASE 2
6. COLLECTOR 2
STYLE 13:
PIN 1. ANODE
2. N/C
STYLE 14:
PIN 1. VREF
2. GND
STYLE 15:
STYLE 16:
STYLE 17:
STYLE 18:
PIN 1. VIN1
2. VCC
PIN 1. ANODE 1
2. ANODE 2
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
3. COLLECTOR
4. EMITTER
5. BASE
3. GND
3. ANODE 3
3. VOUT2
4. VIN2
5. GND
6. VOUT1
4. IOUT
5. VEN
6. VCC
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
5. EMITTER 1
6. COLLECTOR 1
5. EMITTER 2
6. COLLECTOR 1
6. CATHODE
STYLE 19:
PIN 1. I OUT
2. GND
STYLE 20:
STYLE 21:
PIN 1. ANODE 1
2. N/C
STYLE 22:
PIN 1. D1 (i)
2. GND
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
STYLE 24:
PIN 1. CATHODE
2. ANODE
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
3. GND
3. ANODE 2
4. CATHODE 2
5. N/C
3. D2 (i)
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
4. V CC
4. EMITTER
5. COLLECTOR
6. COLLECTOR
4. D2 (c)
5. VBUS
6. D1 (c)
4. N/C
5. V EN
5. CH2
6. N/C
6. V REF
6. CATHODE 1
STYLE 30:
STYLE 25:
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
STYLE 29:
PIN 1. ANODE
2. ANODE
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
3. DRAIN 2
4. SOURCE 2
5. GATE 2
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
4. SOURCE
5. DRAIN
6. DRAIN
5. EMITTER
6. COLLECTOR 1
6. DRAIN 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
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相关型号：
FDG316PD87Z
Small Signal Field-Effect Transistor, 1.6A I(D), 30V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SC-70, 6 PIN
FAIRCHILD
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