FDG6301N-F085P [ONSEMI]
双 N 沟道，数字 FET，25V，0.22A，4Ω;
| 型号： | FDG6301N-F085P |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 沟道，数字 FET，25V，0.22A，4Ω |
| 文件： | 总6页 (文件大小：637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual N-Channel, Digital FET
FDG6301N-F085
Features
• 25 V, 0.22 A Continuous, 0.65 A Peak
• R
• R
= 4 Ω @ V = 4.5 V,
DS(ON)
GS
= 5 Ω @ V = 2.7 V.
DS(ON)
GS
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• Very Low Level Gate Drive Requirements allowing Directop−
Eration in 3 V Circuits (V
< 1.5 V)
GS(th)
• Gate−Source Zener for ESD Ruggedness ( >6 kV Human Body
Model)
• Compact Industry Standard SC70−6 Surface Mount Package.
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
SC−88 (SC−70 6 Lead), 1.25x2
CASE 419AD
• Low Voltage Applications as a Replacement for Bipolar Digital
Transistors and Small Signal MOSFETs
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Symbol
VDSS
VGS
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current Continuous
Pulsed
Ratings
25
Units
V
V
A
8
ID
0.22
0.65
0.3
PD
Power Dissipation
W
TJ, TSTG Operating and Storage Temperature
−55 to 150
6.0
°C
ESD
Electrostatic Discharge Rating
MIL−STD−883D Human Body Model
(100 pF / 1500 W)
kV
Thermal Resistance, Junction to Ambient
415
°C/W
R
q
JA
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. R
is the sum of the junction−to−case and case−to−ambient thermal
θ
JA
resistance, where the case thermal reference is defined as the Solder
mounting surface of the drain pins. R is guaranteed by design, while R
is determined by the board design. R
mounting on FR−4 board in still air.
θ
θ
JA
JC
= 415 °C/W on minimum pad
θ
JA
2. A suffix as “...F085P” has been temporarily introduced in order to manage a
double source strategy as ON Semiconductor has officially announced in
August 2014.
3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%
ORDERING INFORMATION
†
Device
Device Marking
Package
Shipping
FDG6301N−F085
FDG6301N
SC−88 (SC−70 6 Lead)
(Pb−Free, Halogen Free)
3,000 units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
September, 2019 − Rev. 3
FDG6301N−F085/D
FDG6301N−F085
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Parameter
Off Characteristics
Symbol
Test Conditions
Min
Typ
Max
Units
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
I
= 250 mA, V = 0 V
25
V
D
GS
1
mA
V
= 20 V, V = 0 V
GS
DS
GS
T = 55°C
J
10
100
Gate to Source Leakage Current
IGSS
V
=
8 V
nA
On Characteristics
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS(th)
rDS(on)
V
= V
I = 250 mA
0.65
0.22
0.85
2.6
1.5
4
V
GS
DS, D
W
I
D
= 0.22 A, V = 4.5 V
GS
I
I
= 0.19 A, V = 2.7 V
3.7
5.3
5
7
D
GS
= 0.22 A, V = 4.5 V, T = 125°C
D
GS
J
On−State Drain Current
Forward Transconductance
Dynamic Characteristics
Input Capacitance
ID(on)
gFS
V
GS
= 4.5 V, V = 5 V
DS
s
I
D
= 0.22 A, V = 5 V
0.2
DS
V
DS
= 10 V, V = 0 V, f = 1 MHz
GS
Ciss
9.5
6
pF
pF
Output Capacitance
Coss
Reverse Transfer Capacitance
Total Gate Charge at −4.5 V
Crss
4.5
pF
nC
Qg(TOT)
0.4
V
V
= 0 to 4.5 V; V = 5 V, I = 0.22 A
0.29
0.12
0.03
GS
DD
D
= 5 V I = 0.22 A
,
DD
D
Gate to Source Gate Charge
Qgs
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
V
R
= 5 V, I = 0.5 A, V = 4.5 V,
DD
D
GS
10
10
8
Turn−On Delay Time
Rise Time
td(on)
5
ns
ns
ns
ns
= 50 W
GEN
t
r
4.5
4
Turn−Off Delay Time
td(off)
7
Fall Time
t
f
3.2
Drain−Source Diode Characteristics
Maximum Continuous Source Current
Source to Drain Diode Voltage
0.25
1.2
IS
A
V
VSD
I
= 0.25 A, V = 0 V
0.8
SD
GS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDG6301N−F085
TYPICAL CHARACTERISTICS
Figure 2. On−Resistance Variation with Drain Current
Figure 1. On−Region Characteristics
and Gate Voltage
Figure 3. On−Resistance Variation with Temperature
Figure 4. On−Resistance Variation with
Gate−to−Source Voltage
Figure 6. Body Diode Forward Voltage Variation with
Source Current and Temperature
Figure 5. Transfer Characteristics
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3
FDG6301N−F085
TYPICAL CHARACTERISTICS
Figure 8. Capacitance Characteristics
Figure 7. Gate Charge Characteristics
Figure 10. Single Pulse Maximum Power Dissipation
Figure 9. Maximum Safe Operating Area
Figure 11. Transient Thermal Response Curve
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88 (SC−70 6 Lead), 1.25x2
CASE 419AD
ISSUE A
DATE 07 JUL 2010
1
SYMBOL
MIN
NOM
MAX
D
0.80
A
1.10
e
e
A1
A2
0.00
0.80
0.10
1.00
b
c
0.15
0.10
1.80
1.80
1.15
0.30
0.18
2.20
2.40
1.35
D
2.00
2.10
E1
E
E
E1
e
1.25
0.65 BSC
0.36
L
0.26
0.46
L1
L2
0.42 REF
0.15 BSC
TOP VIEW
0º
4º
8º
θ
10º
θ1
q1
A2
A1
A
q
L
b
L1
q1
c
L2
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-203.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34266E
SC−88 (SC−70 6 LEAD), 1.25X2
PAGE 1 OF 1
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