FDN86501LZ [ONSEMI]
N 沟道，屏蔽门极，PowerTrench® MOSFET，60 V，2.6 A，116 mΩ;
| 型号： | FDN86501LZ |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，屏蔽门极，PowerTrench® MOSFET，60 V，2.6 A，116 mΩ |
| 文件： | 总7页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET – N-Channel,
Shielded Gate,
POWERTRENCH)
V
r
MAX
I MAX
D
DS
DS(on)
60 V
116 mW @ 10 V
173 mW @ 4.5 V
2.6 A
60 V, 2.6 A, 116 mW
FDN86501LZ
General Description
This N−Channel MOSFET is produced using onsemi’s advanced
POWERTRENCH process that incorporates Shielded Gate technology.
SOT−23/SUPERSOTt−23, 3 LEAD, 1.4x2.9
CASE 527AG
This process has been optimized for r , switching performance and
DS(on)
ruggedness.
Features
MARKING DIAGRAM
8650M
• Shielded Gate MOSFET Technology
• Max r
• Max r
= 116 mW at V = 10 V, I = 2.6 A
DS(on)
GS
D
= 173 mW at V = 4.5 V, I = 2.1 A
DS(on)
GS
D
• High Performance Trench Technology for Extremely Low r
DS(on)
8650 = Specific Device Code
M
= Date Code
• High Power and Current Handling Capability in a Widely Used
Surface Mount Package
• Fast Switching Speed
PIN ASSIGNMENT
• 100% UIL Tested
• This Device is Pb−Free, Halide Free and is RoHS Compliant
D
Applications
• Primary DC−DC Switch
• Load Switch
MOSFET MAXIMUM RATINGS (T = 25°C, unless otherwise noted)
A
G
S
Symbol
Parameter
Drain to Source Voltage
Ratings
Unit
V
V
DS
V
GS
60
Gate to Source Voltage
Continuous (Note 1a)
20
V
I
D
2.6
A
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
Pulsed (Note 4)
24
E
AS
Single Pulse Avalanche Energy (Note 3)
6
1.5
mJ
W
P
D
Power Dissipation
(Note 1a)
(Note 1b)
0.6
T , T
Operating and Storage Junction
Temperature Range
−55 to 150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS (T = 25°C, unless otherwise noted)
A
Symbol
Parameter
Ratings
Unit
R
Thermal Resistance, Junction−to−Case
(Note 1)
75
°C/W
q
JC
R
Thermal Resistance, Junction−to−Ambient
(Note 1a)
80
°C/W
q
JA
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
January, 2023 − Rev. 2
FDN86501LZ/D
FDN86501LZ
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= 250 mA, V = 0 V
60
−
−
−
−
V
DSS
D
GS
Breakdown Voltage Temperature Coefficient
= 250 mA, referenced to 25_C
68
mV/_C
DBVDSS
DTJ
D
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
V
= 48 V, V = 0 V
−
−
−
−
1
mA
mA
DSS
GSS
DS
GS
I
=
20 V, V = 0 V
10
GS
DS
ON CHARACTERISTICS (Note 2)
V
Gate to Source Threshold Voltage
V
I
= V , I = 250 mA
1.0
−
1.9
−5
2.4
−
V
GS(th)
GS
DS D
Gate to Source Threshold Voltage
Temperature Coefficient
= 250 mA, referenced to 25_C
mV/_C
DVGS(th)
DTJ
D
r
Static Drain to Source On Resistance
Forward Transconductance
V
GS
V
GS
V
GS
V
DS
= 10 V, I = 2.6 A
−
−
−
−
89
121
152
8
116
173
198
−
mW
DS(on)
D
= 4.5 V, I = 2.1 A
D
= 10 V, I = 2.6 A, T = 125_C
D
J
g
FS
= 10 V, I = 2.6 A
S
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= 30 V, V = 0 V, f = 1 MHz
−
−
236
77
335
110
10
pF
pF
pF
W
iss
GS
C
oss
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
C
rss
−
4.9
0.8
R
0.1
2.0
g
SWITCHING CHARACTERISTICS (Note 2)
t
Turn−On Delay Time
Rise Time
V
R
= 30 V, I = 2.6 A, V = 10 V,
−
−
−
−
−
4.4
1.2
9.6
1.2
3.8
10
10
20
10
5.4
ns
ns
ns
ns
nC
d(on)
DD
D
GS
= 6 W
GEN
t
r
t
Turn−Off Delay Time
Fall Time
d(off)
t
f
Q
g
Total Gate Charge
V
GS
V
DD
= 0 V to 10 V
= 30 V, I = 2.6 A
D
Q
g
Total Gate Charge
V
GS
V
DD
= 0 V to 4.5 V
−
1.9
2.7
nC
= 30 V, I = 2.6 A
D
Q
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
DD
= 30 V, I = 2.6 A
−
−
0.7
0.6
−
−
nC
nC
gs
D
Q
gd
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
V
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
= 0 V, I = 2.6 A (Note 2)
−
−
−
0.9
31
19
1.3
50
31
V
SD
GS
S
t
I = 2.6 A, di/dt = 100 A/ms
F
ns
nC
rr
Q
Reverse Recovery Charge
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
q
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design.
q
q
CA
JC
a. 80°C/W when mounted on a
b. 180°C/W when mounted on a
minimum pad.
2
1 in pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%.
3. E of 6 mJ is based on starting T = 25°C, L = 3 mH, I = 2 A, V = 60 V, V = 10 V. 100% test at L = 0.1 mH, I = 9 A.
AS
J
AS
DD
GS
AS
4. Pulsed Id please refer to Figure 11 SOA graph for more details.
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2
FDN86501LZ
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
J
5
4
3
2
1
10
8
V
= 10 V
= 5.5 V
GS
V = 3 V
GS
V
GS
= 4.5 V
V
GS
V
GS
= 3.5 V
6
V
GS
= 3.5 V
4
V
GS
= 4.5 V
2
V
= 10 V
V
= 3 V PULSE DURATION = 80 ms
GS
GS
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
V
GS
= 5.5 V
8
0
0
0
2
4
6
10
0
1
2
3
4
5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
Figure 1. On−Region Characteristics
Figure 2. Normalized On−Resistance vs.
Drain Current and Gate Voltage
2.0
1.8
500
I
V
= 2.6 A
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
D
= 10 V
GS
400
I
D
= 2.6 A
1.6
1.4
1.2
1.0
300
200
100
0
T = 125°C
J
0.8
0.6
T = 25°C
J
−75 −50 −25
0
25 50 75 100 125 150
2
3
4
5
6
7
8
9
10
T , JUNCTION TEMPERATURE (°C)
J
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On−Resistance vs.
Junction Temperature
Figure 4. On−Resistance vs. Gate to Source Voltage
20
10
10
PULSE DURATION = 80 ms
V
GS
= 0 V
DUTY CYCLE = 0.5% MAX
8
V
DS
= 5 V
1
6
4
2
0
T = 150°C
J
0.1
T = 25°C
J
T = 150°C
T = 25°C
J
J
0.01
0.001
T = −55°C
J
T = −55°C
J
1
2
3
4
5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward Voltage
vs. Source Current
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3
FDN86501LZ
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted) (continued)
J
10
8
1000
I
D
= 2.6 A
C
V
DD
= 20 V
iss
100
10
1
V
= 30 V
DD
C
oss
6
V
= 40 V
DD
4
C
rss
2
f = 1 MHz
= 0 V
V
GS
0
0
1
2
3
4
0.1
1
10
60
Q , GATE CHARGE (nC)
g
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain to Source Voltage
10−1
20
V
= 0 V
DS
10−2
10−3
10−4
10−5
10−6
10−7
10−8
10−9
10
T = 25°C
J
T = 125°C
J
T = 100°C
J
T = 25°C
J
T = 125°C
J
1
0.001
0.01
0.1
1
10
0
6
, GATE TO SOURCE VOLTAGE (V)
GS
12
18
24
30
36
t , TIME IN AVALANCHE (ms)
AV
V
Figure 9. Unclamped Inductive Switching
Capability
Figure 10. Gate Leakage Current vs.
Gate to Source Voltage
50
1000
SINGLE PULSE
= 180°C/W
T = 25°C
A
R
qJA
10
10 ms
100
10
1
100 ms
1 ms
10 ms
1
THIS AREA IS
0.1
LIMITED BY r
100 ms
DS(on)
1 s
SINGLE PULSE
10 s
T = MAX RATED
0.01
J
DC
R
q
JA
= 180°C/W CURVE BENT TO
T = 25°C
A
MEASURED DATA
0.001
0.1
0.1
1
10
100 300
10−5 10−4 10−3 10−2 10−1
1
10 100 1000
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
Figure 11. Forward Bias Safe Operating Area
Figure 12. Single Pulse Maximum Power Dissipation
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4
FDN86501LZ
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted) (continued)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
0.01
PDM
0.1
0.05
0.02
0.01
t1
t2
NOTES:
SINGLE PULSE
Z
q
(t) = r(t) x R
q
JA
= 180°C/W
JA
0.001
0.0001
R
q
JA
Peak T = P
x Z (t) + T
q
JA A
J
DM
Duty Cycle, D = t / t
1
2
10−5
10−4
10−3
10−2
10−1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (s)
Figure 13. Junction−to−Ambient Transient Thermal Response Curve
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
Device Marking
Package
Reel Size
Tape Width
8 mm
Shipping
FDN86501LZ
8650
SOT−23/SUPERSOT−23, 3 LEAD, 1.4x2.9
(Pb−Free, Halide Free)
7”
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SUPERSOT is trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23/SUPERSOTt−23, 3 LEAD, 1.4x2.9
CASE 527AG
ISSUE A
DATE 09 DEC 2019
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
XXX = Specific Device Code
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
M
= Month Code
XXXMG
G
= Pb−Free Package
G
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34319E
SOT−23/SUPERSOT−23, 3 LEAD, 1.4X2.9
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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© Semiconductor Components Industries, LLC, 2019
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