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FDS3672 [ONSEMI]

N 沟道，PowerTrench® MOSFET，100V，7.5A，22mΩ;
FDS3672
型号： FDS3672
厂家： ONSEMI    ONSEMI
描述：

N 沟道，PowerTrench® MOSFET，100V，7.5A，22mΩ

PC 开关 光电二极管 晶体管
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April 2012  
FDS3672  
N-Channel PowerTrench® MOSFET  
100V, 7.5A, 22mΩ  
Features  
Applications  
•
•
•
•
•
•
rDS(ON) = 19mΩ (Typ.), VGS = 10V, ID = 7.5A  
Qg(tot) = 28nC (Typ.), VGS = 10V  
Low Miller Charge  
•
•
•
•
DC/DC converters and Off-Line UPS  
Distributed Power Architectures and VRMs  
Primary Switch for 24V and 48V Systems  
High Voltage Synchronous Rectifier  
Low QRR Body Diode  
Optimized efficiency at high frequencies  
UIS Capability (Single Pulse and Repetitive Pulse)  
Formerly developmental type 82763  
Branding Dash  
5
6
7
8
4
3
2
1
5
1
2
3
4
SO-8  
MOSFET Maximum Ratings TA = 25°C unless otherwise noted  
Symbol  
VDSS  
VGS  
Parameter  
Ratings  
100  
Units  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current  
V
V
±20  
Continuous (TA = 25oC, VGS = 10V, RθJA = 50oC/W)  
Continuous (TA = 100oC, VGS = 10V, RθJA = 50oC/W)  
Pulsed  
7.5  
4.8  
A
A
ID  
Figure 4  
416  
A
EAS  
Single Pulse Avalanche Energy (Note 1)  
mJ  
Power dissipation  
Derate above 25oC  
2.5  
W
PD  
20  
mW/oC  
oC  
TJ, TSTG  
Operating and Storage Temperature  
-55 to 150  
Thermal Characteristics  
RθJA  
RθJA  
RθJC  
Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)  
50  
85  
25  
oC/W  
oC/W  
oC/W  
Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)  
Thermal Resistance, Junction to Case (Note 2)  
Package Marking and Ordering Information  
Device Marking  
Device  
Package  
Reel Size  
Tape Width  
12mm  
Quantity  
2500 units  
FDS3672  
FDS3672  
SO-8  
330mm  
©2012 Fairchild Semiconductor Corporation  
FDS3672 Rev. C2  
Electrical Characteristics TA = 25°C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
BVDSS  
Drain to Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
ID = 250µA, VGS = 0V  
100  
-
-
-
-
-
V
V
DS = 80V  
-
-
-
1
IDSS  
µA  
nA  
VGS = 0V  
TC = 150oC  
250  
±100  
IGSS  
VGS = ±20V  
On Characteristics  
VGS(TH)  
Gate to Source Threshold Voltage  
VGS = VDS, ID = 250µA  
2
-
-
4
V
ID = 7.5A, VGS = 10V  
0.019 0.023  
0.023 0.028  
I
D = 6.8A, VGS = 6V  
ID = 7.5A, VGS = 10V,  
C = 150oC  
-
rDS(ON)  
Drain to Source On Resistance  
Ω
-
0.035 0.043  
T
Dynamic Characteristics  
CISS  
Input Capacitance  
-
-
-
-
-
-
-
-
2015  
285  
70  
-
-
pF  
pF  
pF  
nC  
nC  
nC  
nC  
nC  
VDS = 25V, VGS = 0V,  
f = 1MHz  
COSS  
CRSS  
Qg(TOT)  
Qg(TH)  
Qgs  
Output Capacitance  
Reverse Transfer Capacitance  
Total Gate Charge at 10V  
Threshold Gate Charge  
-
VGS = 0V to 10V  
28  
37  
6
-
VGS = 0V to 2V  
4
VDD = 50V  
D = 7.5A  
Ig = 1.0mA  
Gate to Source Gate Charge  
Gate Charge Threshold to Plateau  
Gate to Drain “Miller” Charge  
I
10  
Qgs2  
6.8  
6
-
Qgd  
-
Switching Characteristics (VGS = 10V)  
tON  
td(ON)  
tr  
Turn-On Time  
Turn-On Delay Time  
Rise Time  
-
-
-
-
-
-
-
51  
-
ns  
ns  
ns  
ns  
ns  
ns  
14  
20  
37  
27  
-
-
V
V
DD = 50V, ID = 4A  
GS = 10V, RGS = 10Ω  
td(OFF)  
tf  
Turn-Off Delay Time  
Fall Time  
-
-
tOFF  
Turn-Off Time  
96  
Drain-Source Diode Characteristics  
I
I
SD = 7.5A  
SD = 4A  
-
-
-
-
-
-
-
-
1.25  
1.0  
55  
V
V
VSD  
Source to Drain Diode Voltage  
trr  
Reverse Recovery Time  
ISD= 7.5A, dISD/dt= 100A/µs  
ISD= 7.5A, dISD/dt= 100A/µs  
ns  
nC  
QRR  
Reverse Recovered Charge  
90  
Notes:  
1: Starting T = 25°C, L = 13mH, I = 8A.  
J
AS  
2: R  
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the  
θJA  
drain pins. R  
is guaranteed by design while R  
is determined by the user’s board design.  
θJC  
θCA  
2
3: R  
is measured with 1.0 in copper on FR-4 board  
θJA  
©2012 Fairchild Semiconductor Corporation  
FDS3672 Rev. C2  
Typical Characteristics TA = 25°C unless otherwise noted  
8
6
4
2
0
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
V
= 10V  
GS  
0
25  
50  
75  
100  
125  
150  
25  
50  
75  
100  
125  
150  
o
o
T
, CASE TEMPERATURE ( C)  
T
, AMBIENT TEMPERATURE ( C)  
C
A
Figure 1. Normalized Power Dissipation vs  
Ambient Temperature  
Figure 2. Maximum Continuous Drain Current vs  
Case Temperature  
2
DUTY CYCLE - DESCENDING ORDER  
1
0.5  
o
R
=50 C/W  
0.2  
θJA  
0.1  
0.05  
0.02  
0.01  
0.1  
P
DM  
t
1
0.01  
0.001  
t
2
SINGLE PULSE  
NOTES:  
DUTY FACTOR: D = t /t  
1
2
PEAK T = P  
J
x Z  
x R  
+ T  
DM  
θJA  
θJA A  
-5  
-4  
-3  
-2  
-1  
0
1
2
3
10  
10  
10  
10  
10  
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
Figure 3. Normalized Maximum Transient Thermal Impedance  
1000  
o
T
= 25 C  
A
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
FOR TEMPERATURES  
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
o
150 - T  
C
I = I  
V
= 10V  
25  
GS  
125  
100  
10  
5
-5  
-4  
-3  
-2  
-1  
0
1
2
3
10  
10  
10  
10  
10  
t, PULSE WIDTH (s)  
10  
10  
10  
10  
Figure 4. Peak Current Capability  
©2012 Fairchild Semiconductor Corporation  
FDS3672 Rev. C2  
Typical Characteristics TA = 25°C unless otherwise noted  
300  
10  
10µs  
100  
8
6
100µs  
TJ = 25 o  
C
10  
4
TJ = 100 o  
C
1ms  
1
OPERATION IN THIS  
AREA MAY BE  
LIMITED BY r  
DS(ON)  
10ms  
2
1
100ms  
TJ = 125 o  
C
0.1  
SINGLE PULSE  
T
T
= MAX RATED  
J
o
= 25 C  
C
1s  
0.01  
0.1  
1
10  
100  
0.1  
1.0  
10.0  
100  
300  
tAV, TIME IN AVALANCHE (ms)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
Figure 6. Unclamped Inductive Switching  
Capability  
Figure 5. Forward Bias Safe Operating Area  
30  
30  
20  
10  
0
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
V
= 10V  
GS  
V
= 6V  
GS  
V
= 5V  
GS  
V
= 15V  
DD  
20  
10  
0
o
T
o
= 150 C  
J
V
= 4.5V  
GS  
T
= 25 C  
J
o
T
= 25 C  
A
o
T
= -55 C  
J
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
V
, GATE TO SOURCE VOLTAGE (V)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
GS  
DS  
Figure 7. Transfer Characteristics  
Figure 8. Saturation Characteristics  
24  
22  
20  
18  
2.0  
1.5  
1.0  
0.5  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
V
= 6V  
GS  
V
= 10V  
GS  
V
= 10V, I = 7.5A  
D
GS  
0
2
4
6
8
-80  
-40  
0
40  
80  
120  
160  
o
I
, DRAIN CURRENT (A)  
T , JUNCTION TEMPERATURE ( C)  
D
J
Figure 9. Drain to Source On Resistance vs Drain  
Current  
Figure 10. Normalized Drain to Source On  
Resistance vs Junction Temperature  
©2012 Fairchild Semiconductor Corporation  
FDS3672 Rev. C2  
Typical Characteristics TA = 25°C unless otherwise noted  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
1.10  
1.05  
1.00  
0.95  
0.90  
I
= 250µA  
V
= V , I = 250µA  
DS D  
D
GS  
-80  
-40  
0
40  
80  
120  
160  
-80  
-40  
0
40  
80  
120  
160  
o
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
Figure 11. Normalized Gate Threshold Voltage vs  
Junction Temperature  
Figure 12. Normalized Drain to Source  
Breakdown Voltage vs Junction Temperature  
5000  
10  
C
= C + C  
GS GD  
V
= 50V  
ISS  
DD  
8
6
4
2
0
1000  
100  
10  
C
C
+ C  
DS GD  
OSS  
C
= C  
GD  
RSS  
WAVEFORMS IN  
DESCENDING ORDER:  
I
I
= 7.5A  
= 4A  
D
D
V
= 0V, f = 1MHz  
1
GS  
0.1  
10  
100  
0
5
10  
15  
20  
25  
30  
V
, DRAIN TO SOURCE VOLTAGE (V)  
Q , GATE CHARGE (nC)  
DS  
g
Figure 13. Capacitance vs Drain to Source  
Voltage  
Figure 14. Gate Charge Waveforms for Constant  
Gate Currents  
©2012 Fairchild Semiconductor Corporation  
FDS3672 Rev. C2  
Test Circuits and Waveforms  
V
BV  
DSS  
DS  
t
P
V
DS  
L
I
AS  
V
DD  
VARY t TO OBTAIN  
P
+
-
R
REQUIRED PEAK I  
G
AS  
V
DD  
V
GS  
DUT  
t
P
I
0V  
0
AS  
0.01Ω  
t
AV  
Figure 15. Unclamped Energy Test Circuit  
Figure 16. Unclamped Energy Waveforms  
V
DS  
V
Q
DD  
g(TOT)  
V
DS  
L
V
= 10V  
GS  
V
GS  
+
V
DD  
V
GS  
-
V
= 2V  
DUT  
GS  
Q
gs2  
0
I
g(REF)  
Q
g(TH)  
Q
Q
gd  
gs  
I
g(REF)  
0
Figure 17. Gate Charge Test Circuit  
Figure 18. Gate Charge Waveforms  
V
DS  
t
t
ON  
OFF  
t
d(OFF)  
t
d(ON)  
R
t
t
f
L
r
V
0
DS  
90%  
90%  
+
V
GS  
V
DD  
10%  
10%  
-
DUT  
90%  
50%  
R
GS  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
0
Figure 19. Switching Time Test Circuit  
Figure 20. Switching Time Waveforms  
©2012 Fairchild Semiconductor Corporation  
FDS3672 Rev. C2  
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