FDS6912 [ONSEMI]

双 N 沟道,逻辑电平,PWM 优化,PowerTrench® MOSFET,30V,6A,28mΩ;
FDS6912
型号: FDS6912
厂家: ONSEMI    ONSEMI
描述:

双 N 沟道,逻辑电平,PWM 优化,PowerTrench® MOSFET,30V,6A,28mΩ

开关 脉冲 光电二极管 晶体管
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July 2000  
FDS6912  
Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET  
General Description  
Features  
These N-Channel Logic Level MOSFETs have been  
designed specifically to improve the overall efficiency of  
DC/DC converters using either synchronous or  
conventional switching PWM controllers.  
6 A, 30 V.  
RDS(ON) = 0.028 @ VGS = 10 V  
DS(ON) = 0.042 @ VGS = 4.5 V.  
R
Optimized for use in switching DC/DC converters  
with PWM controllers  
These MOSFETs feature faster switching and lower  
gate charge than other MOSFETs with comparable  
RDS(ON) specifications.  
Very fast switching.  
Low gate charge  
The result is a MOSFET that is easy and safer to drive  
(even at very high frequencies), and DC/DC power  
supply designs with higher overall efficiency.  
D1  
D1  
5
6
7
8
4
3
2
1
D2  
Q1  
Q2  
D2  
G1  
S1  
SO-8  
G2  
S2  
Absolute Maximum Ratings TA=25oC unless otherwise noted  
Symbol  
VDSS  
Parameter  
Drain-Source Voltage  
Ratings  
Units  
30  
V
V
A
VGSS  
Gate-Source Voltage  
±25  
ID  
Drain Current – Continuous  
– Pulsed  
(Note 1a)  
6
20  
PD  
W
Power Dissipation for Dual Operation  
Power Dissipation for Single Operation  
2
(Note 1a)  
(Note 1b)  
(Note 1c)  
1.6  
1
0.9  
TJ, Tstg  
Operating and Storage Junction Temperature Range  
-55 to +150  
°C  
Thermal Characteristics  
Thermal Resistance, Junction-to-Ambient  
(Note 1a)  
(Note 1)  
78  
40  
RθJA  
°C/W  
°C/W  
Thermal Resistance, Junction-to-Case  
RθJC  
Package Marking and Ordering Information  
Device Marking  
Device  
Reel Size  
Tape width  
Quantity  
FDS6912  
FDS6912  
13’’  
12mm  
2500 units  
FDS6912 Rev F (W)  
2000 Fairchild Semiconductor Corporation  
Electrical Characteristics  
TA = 25°C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min Typ Max Units  
Off Characteristics  
BVDSS  
Drain–Source Breakdown Voltage  
30  
V
VGS = 0 V, ID = 250 µA  
Breakdown Voltage Temperature  
Coefficient  
20  
BVDSS  
TJ  
ID = 250 µA, Referenced to 25°C  
mV/°C  
IDSS  
Zero Gate Voltage Drain Current  
VDS = 24 V,  
VGS = 0 V  
1
µA  
10  
TJ = 55°C  
IGSSF  
IGSSR  
Gate–Body Leakage, Forward  
Gate–Body Leakage, Reverse  
VGS = 25 V,  
VGS = –25 V  
VDS = 0 V  
VDS = 0 V  
100  
nA  
nA  
–100  
On Characteristics  
(Note 2)  
VGS(th)  
Gate Threshold Voltage  
1
2
3
V
VDS = VGS, ID = 250 µA  
Gate Threshold Voltage  
Temperature Coefficient  
–5  
VGS(th)  
TJ  
ID = 250 µA, Referenced to 25°C  
mV/°C  
RDS(on)  
Static Drain–Source  
On–Resistance  
VGS = 10 V,  
ID = 6 A  
TJ = 125°C  
0.024 0.028  
0.034 0.048  
VGS = 4.5 V,  
VGS = 10 V,  
VDS = 10 V,  
ID = 4.9 A  
VDS = 5 V  
ID = 6 A  
0.035 0.042  
ID(on)  
gFS  
On–State Drain Current  
20  
A
S
Forward Transconductance  
20  
Dynamic Characteristics  
Ciss  
Coss  
Crss  
Input Capacitance  
740  
170  
75  
pF  
pF  
pF  
V
DS = 15 V,  
V GS = 0 V,  
f = 1.0 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Switching Characteristics (Note 2)  
td(on)  
tr  
td(off)  
tf  
Turn–On Delay Time  
Turn–On Rise Time  
Turn–Off Delay Time  
Turn–Off Fall Time  
Total Gate Charge  
Gate–Source Charge  
Gate–Drain Charge  
8
13  
18  
8
16  
24  
29  
16  
10  
ns  
ns  
VDD = 15 V,  
VGS = 10 V,  
ID = 1 A,  
RGEN = 6 Ω  
ns  
ns  
Qg  
Qgs  
Qgd  
7
nC  
nC  
nC  
V
DS = 10 V,  
ID = 6 A,  
VGS = 5 V  
3.8  
2.5  
Drain–Source Diode Characteristics and Maximum Ratings  
IS  
Maximum Continuous Drain–Source Diode Forward Current  
1.3  
1.2  
A
V
VSD  
Drain–Source Diode Forward  
Voltage  
VGS = 0 V, IS = 1.3 A  
(Note 2)  
0.75  
Notes:  
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of  
the drain pins. θJC is guaranteed by design while RθCA is determined by the user's board design.  
R
a) 78°/W when  
b) 125°/W when  
mounted on a 0.02  
in2 pad of 2 oz  
copper  
c) 135°/W when mounted on a  
minimum mounting pad.  
mounted on a 0.5in2  
pad of 2 oz copper  
Scale 1 : 1 on letter size paper  
2.  
Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%  
FDS6912 Rev E (W)  
Typical Characteristics  
30  
2
1.8  
1.6  
1.4  
1.2  
1
6.0V  
VGS= 10V  
5.0V  
4.5V  
24  
VGS = 4.0V  
18  
4.5V  
4.0V  
3.5V  
5.0V  
12  
6
6.0V  
7.0V  
30  
10V  
3.0V  
0.8  
0
10  
20  
40  
50  
0
0
1
1
2
2
3
3
V
,D RAIN-SOUR CE VOLTAGE (V)  
ID, DRAIN CURRENT (A)  
DS  
Figure 1. On-Region Characteristics.  
Figure 2. On-Resistance Variation with  
Drain Current and Gate Voltage.  
8
7
6
5
4
3
2
1
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
I
= 3.0A  
D
ID = 6.3A  
VGS =10V  
o
TA = 125 C  
25oC  
2
4
6
8
10  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
V
,GATE-SOURCE VOLTAGE (V)  
TJ , JUNCTION TEMPERATURE (°C)  
GS  
Figure 3. On-Resistance Variation  
withTemperature.  
Figure 4. On-Resistance Variation with  
Gate-to-Source Voltage.  
20  
100  
VDS = 5V  
VGS = 0V  
25°C  
125°C  
TJ = -55°C  
10  
TA = 125oC  
15  
10  
5
1
25oC  
0.1  
-55oC  
0.01  
0.001  
0.0001  
0
0.4  
0.8  
1.2  
1.6  
0
1
2
3
4
5
VSD, BODY DIODE FORWARD VOLTAGE (V)  
VGS , GATE TO SOURCE VOLTAGE (V)  
Figure 5. Transfer Characteristics.  
Figure 6. Body Diode Forward Voltage Variation  
with Source Current and Temperature.  
FDS6912 Rev E (W)  
Typical Characteristics (continued)  
10  
2000  
ID = 6.3A  
VDS = 5V  
10V  
8
6
4
2
0
C
15V  
iss  
1000  
500  
C
C
oss  
rss  
f = 1 MHz  
VGS = 0V  
200  
80  
0.1  
0.3  
1
3
10  
30  
0
4
8
12  
16  
Qg, GATE CHARGE (nC)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
Figure 7. Gate Charge Characteristics.  
Figure 8. Capacitance Characteristics.  
30  
25  
20  
15  
10  
100  
SINGLE PULSE  
RθJA= 135°C/W  
TA = 25°  
20  
10  
2
0.5  
VGS = 10V  
SINGLE PULSE  
RθJA = 135 °C/W  
TA = 25°C  
0.05  
0.01  
5
0
0.1  
0.2  
0.5  
1
2
5
10  
20  
0.01  
0.1  
1
10  
100  
1000  
V DS , DRAIN-SOURCE VOLTAGE (V)  
SINGLE PULSE TIME (SEC)  
Figure 9. Maximum Safe Operating Area.  
Figure 10. Single Pulse Maximum  
Power Dissipation.  
1
D = 0.5  
0.2  
0.5  
0.2  
0.1  
R
(t) = r(t) * R  
θJA  
R
θJA  
= 135°C/W  
0.1  
0.05  
θJA  
0.05  
0.02  
0.01  
Single Pulse  
P(pk)  
0.02  
0.01  
t1  
t2  
0.005  
T
- T = P * R  
(t)  
θJA  
J
A
Duty Cycle, D = t1 /t2  
0.002  
0.001  
0.0001  
0.001  
0.01  
0.1  
, TIME (sec)  
1
10  
100  
300  
t
1
Figure 11. Transient Thermal Response Curve.  
Thermal characterization performed using the conditions described in Note 1c.  
Transient thermal response will change depending on the circuit board design.  
FDS6912 Rev E (W)  
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â
SMART START™  
STAR*POWER™  
Stealth™  
VCX™  
FAST  
ACEx™  
Bottomless™  
CoolFET™  
OPTOLOGIC™  
OPTOPLANAR™  
PACMAN™  
FASTr™  
FRFET™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
GlobalOptoisolator™  
GTO™  
HiSeC™  
ISOPLANAR™  
LittleFET™  
MicroFET™  
MicroPak™  
MICROWIRE™  
CROSSVOLT™  
DenseTrench™  
DOME™  
POP™  
Power247™  
PowerTrenchâ  
QFET™  
EcoSPARK™  
E2CMOSTM  
TinyLogic™  
QS™  
EnSignaTM  
TruTranslation™  
UHC™  
QT Optoelectronics™  
Quiet Series™  
SILENTSWITCHERâ  
FACT™  
FACT Quiet Series™  
UltraFETâ  
STAR*POWER is used under license  
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