FDS8876-F40 [ONSEMI]
N 沟道，PowerTrench® MOSFET，30V，12.5A，8.5mΩ;
| 型号： | FDS8876-F40 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，PowerTrench® MOSFET，30V，12.5A，8.5mΩ |
| 文件： | 总15页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – N-Channel,
POWERTRENCH)
V
MAX
r
MAX
I MAX
D
DSS
DS(on)
30 V
8.2 mW @ 10 V
12.5 A
10.2 mW @ 4.5 V
30 V, 12.5 A, 8.2 mW
FDS8876, FDS8876-F40
5
6
7
8
General Description
4
3
2
1
This N−Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using either
synchronous or conventional switching PWM controllers. It has been
SOIC8
(SO−8)
CASE 751EB
optimized for low gate charge, low r
and fast switching speed.
DS(on)
Features
• r
• r
= 8.2 mW, V = 10 V, I = 12.5 A
GS D
DS(on)
DS(on)
MARKING DIAGRAM
= 10.2 mW, V = 4.5 V, I = 11.4 A
GS
D
• High Performance Trench Technology for Extremely Low r
• Low Gate Charge
DS(on)
$Y&Z&2&K
FDS
FDS8876
ALYW
• High Power and Current Handling Capability
• These Devices are Pb−Free and are RoHS Compliant
8876
Applications
FDS8876
FDS8878−F40
• DC/DC Converters
FDS8876 = Device Code
A
= Assembly Site
L
= Wafer Lot Number
= Assembly Start Week
= onsemi Logo
= Assembly Plant Code
= 2−Digit Code Format
= 2−Digits Lot Run Traceability Code
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
YW
$Y
&Z
&2
&K
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Ratings
30
Unit
V
V
DSS
V
GSS
20
V
I
D
Drain
Current
Continuous (T = 25°C,
12.5
A
A
V
= 10 V, R
= 50°C/W)
JA
q
GS
Continuous (T = 25°C,
11.4
A
PIN CONNECTIONS
A
V
= 4.5 V, R
= 50°C/W)
JA
q
GS
Pulsed
91
105
A
mJ
5
6
7
8
4
3
2
1
E
AS
Single Pulse Avalanche Energy (Note 1)
Power Dissipation
P
D
2.5
W
Derate above 25°C
20
mW/°C
°C
T , T
Operating and Storage Temperature
–55 to 150
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Starting T = 25°C, L = 1 mH, I = 14.5 A, V = 30 V, V = 10 V.
J
AS
DD
GS
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
© Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
February, 2022 − Rev. 3
FDS8876/D
FDS8876, FDS8876−F40
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
25
Unit
°C/W
°C/W
°C/W
R
q
JC
R
q
JA
R
q
JA
Thermal Resistance, Junction−to−Case (Note 2)
Thermal Resistance, Junction−to−Ambient (Note 2a)
Thermal Resistance, Junction−to−Ambient (Note 2b)
50
125
2. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
q
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design.
q
q
JC
JA
2
a. 50°C/W when mounted on a 1in pad of 2 oz copper.
b. 125°C/W when mounted on a minimum pad.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
I
= 250 mA, V = 0 V
30
−
−
−
−
−
−
V
VDSS
D
GS
I
V
V
V
= 24 V, V = 0 V
1
mA
DSS
DS
DS
GS
GS
= 24 V, V = 0 V, T = 150°C
−
250
100
GS
J
I
Gate to Source Leakage Current
=
20 V
−
nA
GSS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
= V , I = 250 mA
1.2
−
−
2.5
8.2
V
GS(TH)
DS(on)
GS
DS
D
r
I
D
I
D
I
D
= 12.5 A, V = 10 V
6.8
8.3
10.9
mW
GS
= 11.4 A, V = 4.5 V
−
10.2
14.1
GS
= 12.5 A, V = 10 V, T = 150°C
−
GS
J
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 15 V, V = 0 V, f = 1 MHz
−
−
1650
330
180
2.3
−
−
pF
pF
pF
W
ISS
DS
GS
C
OSS
C
RSS
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
−
−
R
V
V
= 0.5 V, f = 1 MHz
0.6
−
4.0
36
G
GS
Q
Total Gate Charge at 10 V
= 0 V to 10 V, V = 15 V,
28
nC
g(TOT)
GS
DD
I
= 12.5 A, I = 1.0 mA
D
g
Q
Total Gate Charge at 5 V
Threshold Gate Charge
V
D
= 0 V to 5 V,V = 15 V,
−
−
15
20
nC
nC
g(5)
GS
DD
I
= 12.5 A, I = 1.0 mA
g
Q
V
D
= 0 V to 1 V, V = 15 V,
1.5
2.0
g(TH)
GS
DD
I
= 12.5 A, I = 1.0 mA
g
Q
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V
DD
= 15 V, I = 12.5 A, I = 1.0 mA
−
−
−
4.3
2.8
5.0
−
−
−
nC
nC
nC
gs
D
g
Q
gs2
Q
gd
SWITCHING CHARACTERISTICS (V = 10 V)
GS
t
Turn−On Time
Turn−On Delay Time
Rise Time
V
= 15 V, I = 12.5 A, V = 10 V,
−
−
−
−
−
−
−
8
63
−
ns
ns
ns
ns
ns
ns
ON
DD
GS
D
GS
R
= 10 W
t
d(ON)
t
r
34
53
19
−
−
t
Turn−Off Delay Time
Fall Time
−
d(OFF)
t
f
−
t
Turn−Off Time
108
OFF
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
V
Source to Drain Diode Voltage
I
I
I
I
= 12.5 A
= 2.1 A
−
−
−
−
−
−
−
−
1.25
1.0
29
V
V
SD
SD
SD
SD
SD
t
Reverse Recovery Time
= 12.5 A, dI /dt = 100 A/ms
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 12.5 A, dI /dt = 100 A/ms
15
RR
SD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDS8876, FDS8876−F40
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
J
1.2
1.0
0.8
0.6
0.4
0.2
0
16
12
8
V
= 10 V
GS
V
= 4.5 V
GS
4
R
= 50°C/W
q
JA
0
0
25
50
75
100
125
150
25
50
75
100
125
150
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 1. Normalized Power Dissipation vs.
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs.
Ambient Temperature
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
R
= 125°C/W
q
JA
0.001
0.0005
10−4
10−3
10−2
10−1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
1000
SINGLE PULSE
V
GS
= 10 V
R
= 125°C/W
q
JA
T = 25°C
A
100
10
1
0.5
10−4
10−3
10−2
10−1
100
101
102
103
t, PULSE WIDTH (s)
Figure 4. Single Pulse Maximum Power Dissipation
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3
FDS8876, FDS8876−F40
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted) (continued)
J
50
100
10
If R = 0
= (L) (I ) / (1.3 * RATED BV
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
= 15 V
t
AV
− V
)
AS
DSS
DD
If R ≠ 0
= (L / R) ln [(I x R) / (1.3 x RATED BV
40
30
20
10
0
V
DD
t
AV
− V ) +1]
DD
AS
DSS
T = 25°C
J
STARTING T = 25°C
J
T = 150°C
J
T = −55°C
J
STARTING T = 150°C
J
1
0.01
0.1
1
10
100
2.0
2.5
3.0
3.5
t , TIME IN AVALANCHE (ms)
AV
V
GS
, GATE TO SOURCE VOLTAGE (V)
NOTE: Refer to onsemi Application Notes AN−7514 and AN−7515
Figure 6. Transfer Characteristics
Figure 5. Unclamped Inductive Switching Capability
50
50
40
30
20
10
0
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
GS
= 10 V
V
= 5 V
GS
40
30
20
10
0
V
= 3.5 V
I
= 12.5 A
GS
D
V
= 3 V
GS
T = 25°C
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
A
I
D
= 1 A
0
0.2
0.4
0.6
0.8
2
4
6
8
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs.
Gate Voltage and Drain Current
1.6
1.4
1.2
1.0
0.8
0.6
1.2
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
= V , I = 250 mA
GS DS D
1.0
0.8
0.6
0.4
V
GS
= 10 V, I = 12.5 A
D
−80
−40
0
40
80
120
160
−80
−40
0
40
80
120
160
200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Normalized Drain to Source
On Resistance vs. Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs.
Junction Temperature
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4
FDS8876, FDS8876−F40
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted) (continued)
J
10
3000
1000
C
= C + C
GD
ISS
GS
V
DD
= 15 V
8
6
4
2
0
C
≅ C + C
DS GD
OSS
C
= C
GD
RSS
WAVEFORMS IN
DESCENDING ORDER:
I
D
I
D
= 12.5 A
= 1 A
V
= 0 V, f = 1 MHz
1
GS
100
0.1
10
30
0
5
10
15
20
25
30
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 11. Capacitance vs. Drain to Source Voltage
Figure 12. Gate Charge Waveforms for
Constant Gate Currents
200
100
100 ms
10
1 ms
10 ms
1
0.1
THIS AREA IS
LIMITED BY r
100 ms
1 s
DS(on)
SINGLE PULSE
T = MAX RATED
J
10 s
DC
R
= 125°C/W
q
JA
T = 25°C
A
0.01
0.01
0.1
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Forward Bis Safe Operating Area
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5
FDS8876, FDS8876−F40
TEST CIRCUITS AND WAVEFORMS
VDS
BVDSS
tP
VDS
L
IAS
VDD
VARY t TO OBTAIN
P
+
VDD
−
REQUIRED PEAK I
RG
AS
VGS
DUT
t P
IAS
0.01 W
0 V
0
tAV
Figure 14. Unclamped Inductive Load Test Circuit
Figure 15. Unclamped Inductive Waveforms
VDS
VDD
Qg(TOT)
VDS
VGS
L
VGS = 10 V
Qg(5)
VGS
Qgs2
+
VGS = 5 V
VDD
−
DUT
VGS = 1 V
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
tON
td(ON)
tOFF
td(OFF)
VDS
t
t
f
r
RL
VDS
90%
90%
+
VGS
VDD
−
10%
10%
0
90%
50%
DUT
RGS
VGS
50%
PULSE WIDTH
10%
0
VGS
Figure 18. Switching Time Test Circuit
Figure 19. Switching Time Waveforms
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FDS8876, FDS8876−F40
THERMAL RESISTANCE VS. MOUNTING PAD AREA
The maximum rated junction temperature, T , and the
Thermal resistances corresponding to other copper areas
JM
thermal resistance of the heat dissipating path determines
can be obtained from Figure 20 or by calculation using
Equation 2. The area, in square inches is the top copper area
including the gate and source pads.
the maximum allowable device power dissipation, P , in
DM
an application. Therefore the application’s ambient
temperature, T (°C), and thermal resistance R
(°C/W)
A
qJA
26
RqJA + 64 )
must be reviewed to ensure that T is never exceeded.
(eq. 2)
JM
0.23 ) Area
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
The transient thermal impedance (Z ) is also effected
qJA
by varied top copper board area. Figure 21 shows the effect
of copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100 ms. For
pulse widths less than 100 ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models.
A listing of the model component values is available in
Table 1.
(TJM * TA)
PDM
+
(eq. 1)
RqJA
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is
attached and whether there is copper on one side
or both sides of the board.
2. The number of copper layers and the thickness of
the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
200
R
= 64 + 26 / (0.23 + Area)
q
JA
6. For non steady state applications, the pulse width,
the duty cycle and the transient thermal response of
the part, the board and the environment they are in.
onsemi provides thermal information to assist the
designer’s preliminary application evaluation. Figure 20
150
100
50
defines the R for the device as a function of the top copper
qJA
(component side) area. This is for a horizontally positioned
FR−4 board with 1 oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the onsemi device Spice
thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
0.001
0.01
0.1
1
10
2
AREA, TOP COPPER AREA (in )
Figure 20. Thermal Resistance vs. Mounting Pad Area
150
COPPER BOARD AREA − DESCENDING ORDER
2
0.04 in
120
90
60
30
0
2
2
2
2
0.28 in
0.52 in
0.76 in
1.00 in
10−1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
Figure 21. Thermal Impedance vs. Mounting Pad Area
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7
FDS8876, FDS8876−F40
PSPICE ELECTRICAL MODEL
.SUBCKT FDS8876 2 1 3 ; rev January 2005
Ca 12 8 10.3e−10
Cb 15 14 10.3e−10
Cin 6 8 1.6e−9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 33.7
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.29e−9
Ldrain 2 5 1.0e−9
Lsource 3 7 0.18e−10
RLgate 1 9 52.9
RLdrain 2 5 10
RLsource 3 7 1.8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.6e−3
Rgate 9 20 2.3
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3.8e−3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*170),5))}
.MODEL DbodyMOD D (IS=2.0E−12 IKF=10 N=1.01 RS=5.6e−3 TRS1=8e−4 TRS2=2e−7
+CJO=5.7e−10 M=0.52 TT=7e−11 XTI=2)
.MODEL DbreakMOD D (RS=0.2 TRS1=1e−3 TRS2=−8.9e−6)
.MODEL DplcapMOD D (CJO=5.3e−10 IS=1e−30 N=10 M=0.37)
.MODEL MmedMOD NMOS (VTO=1.9 KP=5 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=2.3)
.MODEL MstroMOD NMOS (VTO=2.42 KP=150 IS=1e−30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.62 KP=0.02 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1)
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FDS8876, FDS8876−F40
.MODEL RbreakMOD RES (TC1=8.3e−4 TC2=−8e−7)
.MODEL RdrainMOD RES (TC1=8.0e−3 TC2=1.0e−6)
.MODEL RSLCMOD RES (TC1=1e−4 TC2=1e−6)
.MODEL RsourceMOD RES (TC1=1e−3 TC2=3e−6)
.MODEL RvthresMOD RES (TC1=−2.0e−3 TC2=−6e−6)
.MODEL RvtempMOD RES (TC1=−1.8e−3 TC2=2e−7)
.MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4 VOFF=−3.5)
.MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−3.5 VOFF=−4)
.MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.5 VOFF=−1.0)
.MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.0 VOFF=−1.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written
by William J. Hepp and C. Frank Wheatley.
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
DBODY
RSLC1
DBREAK
11
51
+
RSLC2
5
51
ESLC
−
+
50
−
17
RDRAIN
6
8
18
EBREAK
MWEAK
ESG
−
EVTHRES
+
16
21
+
−
19
8
LGATE
EVTEMP
RGATE
GATE
1
+
6
−
18
22
MMED
9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
S1B
S2B
13
CB
19
−
CA
IT
14
+
+
VBAT
+
6
8
5
8
EGS
EDS
−
−
8
22
RVTHRES
Figure 22.
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9
FDS8876, FDS8876−F40
SABER ELECTRICAL MODEL
REV January 2005
template FDS8876 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.0e−12,ikf=10,nl=1.01,rs=5.6e−3,trs1=8e−4,trs2=2e−7,cjo=5.7e−10,m=0.52,tt=7e−11,xti=2)
dp..model dbreakmod = (rs=0.2,trs1=1e−3,trs2=−8.9e−6)
dp..model dplcapmod = (cjo=5.3e−10,isl=10e−30,nl=10,m=0.37)
m..model mmedmod = (type=_n,vto=1.9,kp=5,is=1e−30, tox=1)
m..model mstrongmod = (type=_n,vto=2.42,kp=150,is=1e−30, tox=1)
m..model mweakmod = (type=_n,vto=1.62,kp=0.02,is=1e−30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−4,voff=−3.5)
sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−3.5,voff=−4)
sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−1.5,voff=−1.0)
sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=−1.0,voff=−1.5)
c.ca n12 n8 = 10.3e−10
c.cb n15 n14 = 10.3e−10
c.cin n6 n8 = 1.6e−9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 33.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.29e−9
l.ldrain n2 n5 = 1.0e−9
l.lsource n3 n7 = 0.18e−9
res.rlgate n1 n9 = 52.9
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 1.8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=8.3e−4,tc2=−8e−7
res.rdrain n50 n16 = 2.6e−3, tc1=8.0e−3,tc2=1.0e−6
res.rgate n9 n20 = 2.3
res.rslc1 n5 n51 = 1e−6, tc1=1e−4,tc2=1e−6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.8e−3, tc1=1e−3,tc2=3e−6
res.rvthres n22 n8 = 1, tc1=−2.0e−3,tc2=−6e−6
res.rvtemp n18 n19 = 1, tc1=−1.8e−3,tc2=2e−7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
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10
FDS8876, FDS8876−F40
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5))
}
}
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
DBREAK
50
−
RDRAIN
6
8
11
ESG
DBODY
EVTHRES
+
16
21
+
−
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
+
6
−
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
−
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
S1B
S2B
13
CB
19
−
CA
IT
14
+
+
VBAT
+
6
8
5
8
EGS
EDS
−
−
8
22
RVTHRES
Figure 23.
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11
FDS8876, FDS8876−F40
JUNCTION
th
SPICE THERMAL MODEL
REV January 2005
FDS8876
Copper Area =1.0 in
2
RTHERM1
CTHERM1
CTHERM1 TH 8 2.0e−3
CTHERM2 8 7 5.0e−3
CTHERM3 7 6 1.0e−2
CTHERM4 6 5 4.0e−2
CTHERM5 5 4 9.0e−2
CTHERM6 4 3 2e−1
CTHERM7 3 2 1
8
7
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
CTHERM8 2 TL 3
RTHERM1 TH 8 1e−1
RTHERM2 8 7 5e−1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
6
5
4
3
2
SABER THERMAL MODEL
SABER thermal model FDS8876
2
Copper Area = 1.0 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e−3
ctherm.ctherm2 8 7 =5.0e−3
ctherm.ctherm3 7 6 =1.0e−2
ctherm.ctherm4 6 5 =4.0e−2
ctherm.ctherm5 5 4 =9.0e−2
ctherm.ctherm6 4 3 =2e−1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
rtherm.rtherm1 th 8 =1e−1
rtherm.rtherm2 8 7 =5e−1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
tl
CASE
Figure 24.
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12
FDS8876, FDS8876−F40
Table 1. THERMAL MODES
2
2
2
2
2
COMPONANT
CTHERM6
CTHERM7
CTHERM8
RTHERM6
RTHERM7
RTHERM8
0.04 in
1.2e−1
0.28 in
0.52 in
0.76 in
1.0 in
1.5e−1
1.0
2.0e−1
1.0
2.0e−1
1.0
2.0e−1
1.0
3.0
12
0.5
1.3
26
39
55
2.8
3.0
3.0
20
15
13
24
21
19
18
38.7
31.3
29.7
25
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
FDS8876
Device Marking
Package Type
Reel Size
Tape Width
Shipping
FDS8876
SOIC8 (SO−8)
(Pb−Free)
13”
12 mm
2500 / Tape & Reel
2500 / Tape & Reel
FDS8876−F40
FDS8876
SOIC8 (SO−8)
(Pb−Free)
13”
12 mm
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
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DESCRIPTION:
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SOIC8
PAGE 1 OF 1
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