FDV303N [ONSEMI]
N 沟道，数字 FET，25V，0.68A，0.45Ω;
| 型号： | FDV303N |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，数字 FET，25V，0.68A，0.45Ω PC 开关 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Digital FET, N-Channel
FDV303N
General Description
These N−Channel enhancement mode field effect transistors are
produced using ON Semiconductor’s proprietary, high cell density,
DMOS technology. This very high density process is tailored to
minimize on−state resistance at low gate drive conditions. This device
is designed especially for application in battery circuits using either
one lithium or three cadmium or NMH cells. It can be used as an
inverter or for high−efficiency miniature discrete DC/DC conversion
in compact portable electronic devices like cellular phones and pagers.
This device has excellent on−state resistance even at gate drive
voltages as low as 2.5 V.
www.onsemi.com
SOT−23 (TO−236)
CASE 318−08
STYLE 21
Features
• 25 V, 0.68 A Continuous, 2 A Peak
♦ R
♦ R
= 0.45 Ω @ V = 4.5 V
MARKING DIAGRAM
DS(ON)
GS
Drain
3
= 0.6 Ω @ V = 2.7 V
DS(ON)
GS
• Very Low Level Gate Drive Requirements Allowing Direct Operation
in 3 V Circuits, V < 1 V
A303MG
GS(th)
G
• Gate−Source Zener for ESD Ruggedness, > 6 kV Human Body
1
Gate
2
Model
Source
• Compact Industry Standard SOT−23 Surface Mount Package
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Aor blank = One/two character Loacation Code
303
M
= Specific Device Code
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
* Location code can be blank or with characters
indicating manufacturing location
* Date Code orientation and overbar may vary
depending upon manufacturing location.
PIN ASSIGNMENT
D
S
G
SOT−23
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 1997
1
Publication Order Number:
March, 2020 − Rev. 5
FDV303N/D
FDV303N
MOSFET MAXIMUM RATINGS TA = 25°C unless otherwise noted
Symbol Parameter
FDV303N
Units
Drain−Source Voltage, Power Supply Voltage
25
8
V
V
DSS
GSS
Gate−Source Voltage, V
V
A
V
IN
I
D
Drain/Output Current
− Continuous
− Pulsed
0.68
2
Maximum Power Dissipation
0.35
−55 to 150
6.0
W
°C
kV
P
D
Operating and Storage Temperature Range
T , T
J
STG
Electrostatic Discharge Rating MIL−STD−883D Human Body Model
(100 pf / 1500 W)
ESD
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
Units
Thermal Resistance, Junction−to−Ambient
357
°C/W
R
θ
JA
ORDERING INFORMATION
†
Device
Package
Shipping
FDV303N
SOT−23
Case 318−08
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
FDV303N
ELECTRICAL CHARACTERISTICS T = 25°C unless otherwise noted
J
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
Drain−Source Breakdown Voltage
V
I
= 0 V, I = 250 mA
25
V
DSS
GS
D
= 250 mA, Referenced to 25°C
mV/°C
ΔBV
ΔT
/ Breakdown Voltage Temp. Coefficient
26
D
DSS
J
1
mA
mA
nA
V
V
I
= 20 V, V = 0 V
Zero Gate Voltage Drain Current
I
DS
GS
DSS
10
T = 55°C
J
I
Gate − Body Leakage Current
= 8 V, V = 0 V
100
GSS
GS
DS
ON CHARACTERISTICS (Note 1)
= 250 mA, Referenced to 25°C
mV/°C
ΔV
ΔT
/ Gate Threshold Voltage Temperature
Coefficient
−2.6
D
GS(th)
J
Gate Threshold Voltage
0.65
0.5
0.8
1
V
V
V
V
= V , I = 250 mA
GS D
GS(th)
DS
= 4.5 V, I = 0.5 A
0.33
0.52
0.44
0.45
0.8
0.6
Ω
R
Static Drain−Source On−Resistance
GS
D
DS(ON)
T =125°C
J
V
V
V
= 2.7 V, I = 0.2 A
D
GS
On−State Drain Current
A
S
I
= 2.7 V, V = 5 V
D(ON)
GS
DS
DS
Forward Transconductance
= 5 V, I = 0.5 A
1.45
g
FS
D
DYNAMIC CHARACTERISTICS
V
DS
= 10 V, V = 0 V, f = 1.0 MHz
Input Capacitance
50
28
9
pF
pF
pF
C
GS
iss
Output Capacitance
C
oss
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (Note 1)
V
V
= 6 V, I = 0.5 A, V = 4.5 V, R
= 50 Ω
Turn − On Delay Time
Turn − On Rise Time
Turn − Off Delay Time
Turn − Off Fall Time
Total Gate Charge
3
6
ns
ns
t
DD
D
GS
GEN
D(on)
8.5
17
18
30
25
2.3
t
r
ns
t
D(off)
13
ns
t
f
= 5 V, I = 0.5 A, V = 4.5 V
Q
1.64
0.38
0.45
nC
nC
nC
DS
D
GS
g
Gate−Source Charge
Gate−Drain Charge
Q
gs
Q
gd
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain−Source Diode Forward Current
0.3
1.2
A
V
I
S
Drain−Source Diode Forward Voltage
0.83
V
GS
= 0 V, I = 0.5 A (Note 1)
V
SD
S
1. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%.
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3
FDV303N
TYPICAL CHARACTERISTICS
1.5
1.2
0.9
0.6
0.3
0
2
VGS = 4.5 V
2.5
3.5
3.0
V
GS
= 2.0 V
2.0
2.7
1.5
2.5
2.7
3.0
3.5
4.5
1
1.5
0.5
0
0.2
0.4
0.6
0.8
1
1.2
0
0.5
1
1.5
2
I
, DRAIN CURRENT (A)
V DS, DRAIN−SOURCE VOLTAGE (V)
D
Figure 1. On−Region Characteristics
Figure 2. On−Resistance Variation with
Drain Current and Gate Voltage
1.6
1.4
1.2
1
2
I=0.5A
D
I
=0.5 A
D
V
= 4.5 V
GS
1.6
1.2
0.8
0.4
0
125°C
25°C
0.8
0.6
−50
−25
0
25
50
75
100
125
150
1
1.5
2
2.5
3
3.5
4
4.5
5
T , JUNCTION TEMPERATURE (°C)
J
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On−Resistance Variation
Figure 4. On Resistance Variation with
with Temperature
Gate−To− Source Voltage
1
1
T
= −55°C
J
V
= 5.0 V
DS
25°C
125°C
T
= 125°C
V
GS
= 0 V
J
0.8
0.6
0.4
0.2
0
0.1
25°C
−55°C
0.01
0.001
0.0001
0
0.5
1
1.5
2
2.5
0
0.2
0.4
0.6
0.8
1
1.2
V
, GATE TO SOURCE VOLTAGE (V)
GS
V
, BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 6. Body Diode Forward Voltage
Variation with Source Current and Temperature
Figure 5. Transfer Characteristics
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4
FDV303N
TYPICAL CHARACTERISTICS T = 25°C Unless Otherwise Noted (continued)
J
5
4
3
2
1
0
150
VDS = 5 V
ID = 0.5 A
100
10 V
15 V
C
50
iss
C
oss
20
f = 1 MHz
V
= 0 V
GS
10
C
rss
5
0.1
0
0.4
0.8
1.2
1.6
2
0.5
1
2
5
10
25
Q g , GATE CHARGE (nC)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance Characteristics
5
3
5
4
3
2
1
SINGLE PULSE
R
= 357° C/W
θ
JA
1
TA = 25°C
0.3
0.1
VGS = 4.5 V
SINGLE PULSE
RθJA= 357°C/W
TA= 25°C
0.03
0.01
0
0.1
0.2
0.5
1
2
5
10
20
40
0.001
0.01
0.1
1
10
301000
V
, DRAI N−SOURCE VOLTAGE (V)
DS
SINGLE PULSE TIME (s)
Figure 9. Maximum Safe Operating Area
Figure 10. Single Pulse Maximum Power
Dissipation
1
D = 0.5
0.5
0.2
0.1
0.2
0.1
R
R
(t)= r(t) * R
θJA
= 357°C/W
θJA
θJA
0.05
0.05
P(pk)
0.02
0.01
0.02
0.01
t
1
t
2
Single Pulse
0.005
T
− T = P * R
(t)
J
A
θ
JA
Duty Cycle, D = t /t
0.002
0.001
1
2
0.0001
0.001
0.01
0.1
, TIME (sec)
1
10
100
300
t
1
Figure 11. Transient Thermal Response Curve
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318
ISSUE AT
DATE 01 MAR 2023
SCALE 4:1
GENERIC
MARKING DIAGRAM*
XXXMG
G
1
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318
ISSUE AT
DATE 01 MAR 2023
STYLE 1 THRU 5:
CANCELLED
STYLE 6:
STYLE 7:
PIN 1. EMITTER
2. BASE
STYLE 8:
PIN 1. BASE
PIN 1. ANODE
2. EMITTER
3. COLLECTOR
2. NO CONNECTION
3. CATHODE
3. COLLECTOR
STYLE 9:
PIN 1. ANODE
2. ANODE
STYLE 10:
STYLE 11:
PIN 1. ANODE
2. CATHODE
STYLE 12:
STYLE 13:
PIN 1. SOURCE
2. DRAIN
STYLE 14:
PIN 1. CATHODE
2. GATE
PIN 1. DRAIN
2. SOURCE
3. GATE
PIN 1. CATHODE
2. CATHODE
3. ANODE
3. CATHODE
3. CATHODE−ANODE
3. GATE
3. ANODE
STYLE 15:
STYLE 16:
STYLE 17:
PIN 1. NO CONNECTION
2. ANODE
STYLE 18:
STYLE 19:
STYLE 20:
PIN 1. CATHODE
2. ANODE
PIN 1. GATE
2. CATHODE
3. ANODE
PIN 1. ANODE
2. CATHODE
3. CATHODE
PIN 1. NO CONNECTION PIN 1. CATHODE
2. CATHODE
3. ANODE
2. ANODE
3. CATHODE−ANODE
3. CATHODE
3. GATE
STYLE 21:
STYLE 22:
STYLE 23:
PIN 1. ANODE
2. ANODE
STYLE 24:
STYLE 25:
STYLE 26:
PIN 1. GATE
2. SOURCE
3. DRAIN
PIN 1. RETURN
2. OUTPUT
3. INPUT
PIN 1. GATE
2. DRAIN
PIN 1. ANODE
2. CATHODE
3. GATE
PIN 1. CATHODE
2. ANODE
3. SOURCE
3. NO CONNECTION
3. CATHODE
STYLE 27:
STYLE 28:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
PIN 1. ANODE
2. ANODE
3. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
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