FMS6364AMTC14X [ONSEMI]
VoltagePlus™ 视频滤波器驱动器，四沟道，SD 和 HD;
| 型号： | FMS6364AMTC14X |
| 厂家： | 
ONSEMI |
| 描述： | VoltagePlus™ 视频滤波器驱动器，四沟道，SD 和 HD 驱动 光电二极管 商用集成电路 驱动器 |
| 文件： | 总13页 (文件大小：815K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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October 2014
FMS6364A
Four-Channel Standard- & High-Definition (SD & HD)
VoltagePlus™ Video Filter Driver
Features
Description
The FMS6364A VoltagePlus™ video filter is intended to
replace passive LC filters and drivers with a cost-
effective integrated device. Three 7th-order filters
provide HD quality and a single 6th-order SD channel
provides compatibility. The FMS6364A may be directly
driven by a DC-coupled DAC output or an AC-coupled
signal. Internal diode clamps and bias circuitry may be
used if AC-coupled inputs are required (see the
Application Information section for details).
.
.
.
Three 7th-Order 32 MHz (HD) Filters
One 6th-Order 8 MHz (SD) Filter
Drives Single AC- or DC-Coupled Video Loads
(150 Ω)
.
.
.
.
.
Drives Dual AC- or DC-Coupled video Loads (75 Ω)
Transparent Input Clamping
Single Supply: 3.3 V – 5.0 V
AC- or DC-Coupled Inputs and Outputs
The outputs can drive AC- or DC-coupled single (150 Ω)
or dual (75 Ω) video loads. DC coupling the outputs
removes the need for large output coupling capacitors.
The input DC levels are offset approximately +280 mV
at the output (see the Application Information section).
DC-Coupled Output Eliminates AC-Coupling
Capacitor
.
.
Robust 9kV ESD Protection
Lead-Free TSSOP-14 Package
Applications
Related Resources
.
.
.
.
.
.
Cable Set-Top Boxes
AN-6024 – FMS6xxx Product Series; Understanding
Analog Video Signal Clamps, Bias, DC Restore, and
AC- or DC-Coupling Methods
Satellite Set-Top Boxes
DVD Players
AN-6041 – PCB Layout Considerations for Video
Filter/Drivers
HDTV
Personal Video Recorders (PVR)
Video On Demand (VOD)
Ordering Information
Operating
Temperature Range
Part Number
Package
Packing Method
14-Lead TSSOP, JEDEC MO-153,
4.4 mm Wide
FMS6364AMTC14X
-40°C to +85°C
2500 Units per Reel
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
Block Diagram
Clamp
6d
6d
B
B
IN1
IN2
OUT1
OUT2
SD
HD
Bias
Bias
6d
6d
B
B
IN3
IN4
OUT3
OUT4
HD
HD
Clamp
Figure 1. Block Diagram
Pin Configuration
Figure 2. Pin Configuration
Pin Definitions
Pin#
Name
Type
Description
1
2
IN1
GND
IN2
Input
Input
Input
Input
Input
Video Input Channel SD
Device Ground Connection
Video Input Channel HD (Pr)
Video Input Channel HD (Pb)
Video Input Channel HD (Y)
No Connection
3
4
IN3
5
IN4
6
NC
7
VCC
Power
Positive Power Supply
8
GND
NC
Ground Device Ground Connection
No Connection
9
Filtered Output Channel HD (Y)
Filtered Output Channel HD (Pb)
Filtered Output Channel HD (Pr)
10
11
12
13
14
OUT4
OUT3
OUT2
GND
OUT1
Output
Output
Output
Ground Device Ground Connection
Output
Filtered Output Channel SD
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VS
Parameter
Min.
-0.3
-0.3
Max.
6.0
Unit
V
DC Supply Voltage
VIO
Analog and Digital I/O
VCC+0.3
50
V
IOUT
Maximum Output Current, Do Not Exceed
mA
Reliability Information
Symbol
Parameter
Junction Temperature
Min.
Typ.
Max.
150
Unit
°C
TJ
TSTG
TL
Storage Temperature Range
-65
150
°C
Lead Temperature (Soldering, 10 Seconds)
300
°C
Thermal Resistance, JEDEC Standard,
Multilayer Test Boards, Still Air
115
°C/W
JA
Electrostatic Discharge Protection (ESD)
Symbol
HBM
Parameter
Human Body Model ESD
Charged Device Model ESD
Condition
Minimum Level
Unit
kV
IEC61340-3-1:2002 Level II
JESD22-C101-A Level III
9
2
CDM
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Temperature Range
Supply Voltage Range
Min.
-40
Typ.
Max.
85
Unit
°C
VCC
3.135
3.300
5.250
V
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
3
DC Electrical Characteristics
Unless otherwise noted, TA=25°C, VCC=3.3 V, RS=37.5 Ω, all inputs are AC coupled with 0.1 µF, and all output
AC coupled with 220 µF into 150 Ω load.
Symbol
Supply
VS
Parameter
Conditions
Min.
Typ.
Max. Units
Supply Voltage Range
VS Range
3.135
3.300
50
5.250
65
V
VS=+3.3 V, No Load, EN=LOW
VS=+5.25 V, No Load, EN=LOW
Referenced to GND if DC Coupled
mA
mA
VPP
dB
ICC
Quiescent Supply Current(1)
55
76
VIN
PSRR
Note:
Video Input Voltage Range
1.4
-50
Power Supply Rejection Ratio DC (All Channels)
1. 100% tested at TA=25°C.
Standard-Definition Electrical Characteristics
Unless otherwise noted, TA=25°C, VIN=1 VPP, VCC=5 V, RSOURCE=37.5 , all inputs AC coupled with 0.1 µF, all outputs
AC coupled with 220 µF into 150 loads, and referenced to 400 kHz.
Symbol
Parameter
Channel Gain(2)
Conditions
All SD Channels
Min.
Typ.
Max. Units
AVSD
f01dBSD
f1dBSD
fcSD
5.8
6.0
5
6.2
dB
MHz
MHz
MHz
dB
-0.1 dB Flatness
-1 dB Flatness(2)
-3 dB Bandwidth(2)
Attenuation (Stopband Reject)(2)
Differential Gain
All SD Channels
All SD Channels
7
8
8
All SD Channels
9
fSBSD
DG
All SD Channels at f=27 MHz
All SD Channels
45
60
0.3
0.6
0.35
-74
%
DP
Differential Phase
All SD Channels
°
THD
XTALKSD
Total Harmonic Distortion, Output VOUT=1.4VPP, 3.58 MHz
%
Crosstalk (Channel-to-Channel)
Signal-to-Noise Ratio(3)
1 MHz
dB
NTC-7 Weighting, 100 kHz to
4.2 MHz
SNR
tpdSD
76
90
dB
ns
%
Delay from Input to Output,
4.5 MHz
Propagation Delay
Chroma Luma Gain(2)
Chroma Luma Delay
f=3.58 MHz (Ref to SDIN at
400 kHz)
CLGSD
CLDSD
95
100
5.5
105
f=3.58 MHz (Ref to SDIN at
400 kHz)
ns
tON
tOFF
Enable Time
Disable Time
1
1
µs
µs
Notes:
2. 100% tested at TA=25°C.
3. SNR=20 • log (714 mV / rms noise).
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
4
High-Definition Electrical Characteristics
Unless otherwise noted, TA=25°C, VCC=3.3 V, RS=37.5 Ω, all inputs are AC coupled with 0.1 µF, and all outputs
AC coupled with 220 µF into 150 Ω load.
Symbol
Parameter
Channel Gain(4)
Conditions
Min.
5.8
Typ. Max.
Unit
dB
AV
Active Video Input Range=1 VPP
RSOURCE=75 Ω, RL=150 Ω
RSOURCE=75 Ω, RL=150 Ω
RSOURCE=75 Ω, RL=150 Ω
RSOURCE=75 Ω, f=37.325 MHz
RSOURCE=75 Ω, f=44.25 MHz
RSOURCE=75 Ω, f=74.25 MHz
RSOURCE=75 Ω, f=78 MHz
f=10 MHz; VOUT=1.4 VPP
f=15 MHz; VOUT=1.4 VPP
f=22 MHz; VOUT=1.4 VPP
6.0
6.2
ΔAV24MHz Damping at 24 MHz
ΔAV28MHz Damping at 28 MHz
BW3.0dB -3.0 dB Bandwidth(4)
Att37.125M
-0.65
-1
dB
dB
32
34
6.5
14.5
44
MHz
dB
Att44.25M
Att74.25M
Att78M
dB
Normalized Stopband
Attenuation(4)
40
42
dB
46
dB
THD1
0.4
0.5
0.5
Output Distortion
(All Channels)
THD2
%
THD3
Crosstalk
(Channel-to-Channel)
Xtalk
SNR
tpd
f=1.00 MHz; VOUT=1.4 VPP
-70
70
25
dB
dB
ns
Unweighted: 30 MHz Lowpass,
100 kHz to 30 MHz
Peak Signal to RMS Noise
Propagation Delay
Delay from Input to Output;
100 kHz to 26 MHz
Note:
4. 100% tested at 25°C.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
5
Typical Performance Characteristics
Unless otherwise noted, TA = 25°C, VCC = 3.3 V, RS = 37.5 Ω, and AC-coupled output into 150 Ω load.
5.00
-5.00
1.00
0.00
-15.00
-25.00
-35.00
-45.00
-55.00
-65.00
-75.00
-1.00
-2.00
-3.00
-4.00
-5.00
-6.00
-7.00
Frequency
Figure 3. SD Frequency Response
Frequency
Figure 4. SD Flatness
5.00
2.00
0.00
-2.00
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
-16.00
-18.00
-20.00
-5.00
-15.00
-25.00
-35.00
-45.00
-55.00
-65.00
Frequency
Frequency
Figure 5. HD Frequency Response
Figure 6. HD Flatness
Figure 7. Differential Gain
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
6
Typical Performance Characteristics
Unless otherwise noted, TA = 25°C, VCC = 3.3 V, RS = 37.5 Ω, and AC-coupled output into 150 Ω load.
Figure 8. Differential Phase
Figure 9. SNR vs Frequency
Figure 10. Chroma / Luma Gain & Delay
Figure 11.Typical Application
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
7
Application Information
Application Circuits
The FMS6364A VoltagePlus™ video filter provides a
6 dB gain from input to output. In addition, the input is
slightly offset to optimize the output driver performance.
The offset is held to the minimum required value to
decrease the standing DC current into the load. Typical
voltage levels are shown in the diagram below:
1.0 -> 1.02V
0.65 -> 0.67V
0.3 -> 0.32V
Figure 13. Input Clamp Circuit
I/O Configurations
0.0 -> 0.02V
V
IN
For a DC-coupled DAC drive with DC-coupled outputs,
use the configuration in Figure 14.
2.28V
1.58V
Driven by:
DC-Coupled DAC Outputs
AC-Coupled and Clamped
Y, CV, R, G, B
0V - 1.4V
DVD or
STB
SoC
LCVF
Clamp
Inactive
75W
0.88V
0.28V
V
OUT
DAC
Output
There is a 280mV offset from the DC input level to the
DC output level. V
= 2 * V + 280mV.
IN
OUT
Figure 14. DC-Coupled Inputs and Outputs
0.85V
0.5V
Alternatively, if the DAC’s average DC output level
causes the signal to exceed the range of 0 V to 1.4 V, it
can be AC coupled as shown in Figure 15.
0.15V
V
IN
0V - 1.4V
1.98V
1.28V
0.58V
0.1μ
Driven by:
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
75Ω
AC-Coupled and Biased
U, V, Pb, Pr, C
V
OUT
Figure 12. Typical Voltage Levels
The FMS6364A provides an internal diode clamp to
support AC-coupled input signals. If the input signal
does not go below ground, the input clamp does not
operate. This allows DAC outputs to directly drive the
FMS6364A without an AC-coupling capacitor. When the
input is AC-coupled, the diode clamp sets the sync tip
(or lowest voltage) just below ground. The worst-case
sync tip compression due to the clamp cannot exceed
7mV. The input level set by the clamp, combined with
the internal DC offset, keeps the output within its
acceptable range.
Figure 15. AC-Coupled Inputs, DC-Coupled Outputs
When the FMS6364A is driven by an unknown external
source or a SCART switch with its own clamping
circuitry, the inputs should be AC coupled as shown in
Figure 16.
0V - 1.4V
0.1μ
LCVF
75Ω
External video
Clamp
source must
Active
For symmetric signals like Chroma, U, V, Pb, and Pr;
the average DC bias is fairly constant and the inputs
can be AC coupled. DAC outputs can also drive these
be AC coupled
75Ω
same signals without the AC-coupling capacitor.
A
conceptual illustration of the input clamp circuit is shown
in Figure 13:
Figure 16. SCART with DC-Coupled Outputs
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
8
The same method can be used for biased signals. The
Pb and Pr channels are biased to set the DC level to
500 mV.
Power Dissipation
The FMS6364A output drive configuration must be
considered when calculating overall power dissipation.
Care must be taken not to exceed the maximum die
junction temperature. The following equations can be
used to calculate the power dissipation and internal
temperature rise.
The same circuits can be used with AC-coupled outputs
if desired.
0V - 1.4V
0.1μ
220μ
DVD or
STB
SoC
LCVF
Clamp
Active
75Ω
TJ = TA + PD • ϴJA
where:
(1)
DAC
PD = PCH1 + PCH2 + PCH3 and
PCHx = VCC • ICH - (VO2/RL)
where:
(2)
(3)
Output
Figure 17. AC-Coupled Inputs and Outputs
External video
VO = 2 VIN + 0.280 V
ICH = (ICC/3) + (VO/RL)
VIN = RMS value of input signal
ICC = 50 mA
(4)
(5)
0V - 1.4V
source must
0.1μ
220μ
be AC coupled
LCVF
Clamp
Active
75Ω
VCC = 3.3 V
75Ω
RL = channel load resistance.
Board layout can also affect thermal characteristics.
Refer to the Layout Considerations section for details.
Figure 18. Biased SCART with AC-Coupled Outputs
The FMS6364A is specified to operate with output
currents typically less than 50 mA, more than sufficient
for a dual (75 Ω) video load. Internal amplifiers are
current limited to a maximum of 100 mA and should
withstand brief-duration short-circuit conditions. This
capability is not guaranteed.
Note:
5. The video tilt or line time distortion is dominated by
the AC-coupling capacitor. The value may need to
be increased beyond 220 μF to obtain satisfactory
operation in some applications.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
9
Layout Considerations
General layout and supply bypassing play a major role
The selection of the coupling capacitor is a function of
the subsequent circuit input impedance and the leakage
current of the input being driven. To obtain the highest
quality output video signal, the series termination
resistor must be placed as close to the device output pin
as possible. This greatly reduces the parasitic
capacitance and inductance effect on the output driver.
The distance from device pin to the series termination
resistor should be no greater than 12.7 mm (0.5 in).
in
high-frequency
performance
and
thermal
characteristics. Fairchild offers a demonstration board to
guide layout and aid device evaluation. The demo board
is a four-layer board with full power and ground planes.
Following this layout configuration provides optimum
performance and thermal characteristics for the device.
For the best results, follow the steps and recommended
routing rules listed below.
Pad
Recommended Routing/Layout Rules
Lead
.
.
Do not run analog and digital signals in parallel.
Use separate analog and digital power planes to
supply power.
75-Ohm Series
Termination Resistor
Lead
.
.
.
.
Do not run traces on top of the ground plane.
Run no traces over ground/power splits.
Avoid routing at 90-degree angles.
Routing Trace
Pad for
Resistor
≤ 12.7mm
Minimize clock and video data trace length
differences.
Figure 19. Recommended Resistor Placement
.
.
.
.
.
Include 0.01 μF and 0.1 μF ceramic power supply
bypass capacitors.
Thermal Considerations
Place the 0.1 μF capacitor within 2.54 mm (0.1 in)
of the device power pin.
Since the interior of systems such as set-top boxes,
TVs, and DVD players are at +70ºC; consideration must
be given to providing an adequate heat sink for the
device package for maximum heat dissipation. When
designing a system board, determine how much power
each device dissipates. Ensure that devices of high
power are not placed in the same location, such as
directly above (top plane) or below (bottom plane), each
other on the PCB.
Place the 0.01 μF capacitor within 19.05 mm
(0.75 in) of the device power pin.
For multi-layer boards, use a large ground plane to
help dissipate heat.
For two-layer boards, use a ground plane that
extends beyond the device body at least 12.7 mm
(0.5 in) on all sides. Include a metal paddle under
the device on the top layer.
.
.
Minimize all trace lengths to reduce series
inductance.
PCB Thermal Layout Considerations
.
Understand the system power requirements and
environmental conditions.
Place a 75 Ω series resistor within 12.7 mm (0.5 in)
of the output pin to isolate the output driver from
board parasitics.
.
.
Maximize thermal performance of the PCB.
Consider using 70 μm of copper for high-power
designs.
Output Considerations
The FMS6364A outputs are DC offset from the input by
150 mV; therefore VOUT = 2 • VIN DC+150 mV. This
offset is required to obtain optimal performance from the
output driver and is held at the minimum value to
decrease the standing DC current into the load. Since
the FMS6364A has a 2 x (6 dB) gain, the output is
typically connected via a 75 Ω-series back-matching
resistor followed by the 75 Ω video cable. Because of
the inherent divide by two of this configuration, the
blanking level at the load of the video signal is always
less than 1 V. When AC coupling the output, ensure that
the coupling capacitor of choice passes the lowest
frequency content in the video signal and that line time
distortion (video tilt) is kept as low as possible.
.
.
.
.
Make the PCB as thin as possible by reducing FR4
thickness.
Use vias in the power pad to tie adjacent layers
together.
Remember that baseline temperature is a function
of board area, not copper thickness.
Consider modeling techniques a first-order
approximation.
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6364A • Rev. 3.0.5
10
0.65
A
ꢀꢁꢂꢂꢂꢁꢃꢂ
0.43TYP
14
8
B
6.4
ꢄꢁꢄꢂꢂꢁꢃꢂ
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3.2
1.65
0.2 C B A
ALL LEAD TIPS
1
7
PIN#1 IDENT
TOP VIEW
0.45
RECOMMENDED LAND PATTERN
SEE DETAIL A
1.2 MAX
+0.15
-0.10
0.90
0.20
0.09
ꢂꢁꢃꢂꢂꢁꢂꢀ
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FRONT VIEW
0.09 MIN
NOTES:
GAGE PLANE
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
0.25
0.09 MIN
ꢂꢉꢆꢊ
ꢂꢁꢈꢂꢁꢃ
1.00
SEATING PLANE
DETAIL A
E. LANDPATTERN STANDARD: SOP65P640X110-14M.
F. DRAWING FILE NAME: MKT-MTC14rev7.
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