FMS6404CSX [ONSEMI]
带声频陷波器和群延迟补偿的精密复合视频输出;
| 型号： | FMS6404CSX |
| 厂家： | 
ONSEMI |
| 描述： | 带声频陷波器和群延迟补偿的精密复合视频输出 放大器 光电二极管 商用集成电路 |
| 文件： | 总11页 (文件大小：785K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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October 2011
FMS6404
Precision Composite Video Output with Sound Trap and
Group Delay Compensation
Description
Features
The FMS6404 is a single composite video 5th-order
Butterworth low-pass video filter optimized for minimum
overshoot and flat group delay. The device contains an
audio trap that removes video information in a spectral
location of the subsequent RF audio carrier. The group
delay compensation circuit pre-distorts the signal to
compensate for the inherent receiver intermediate
frequency (IF) filter’s group delay distortion.
.
.
7.6MHz 5th-Order Composite Video Filter
14dB Notch at 4.425MHz to 4.6MHz for Sound Trap
Capable of Handling Stereo
.
50dB Stopband Attenuation at 27MHz on
CV Output
.
.
> 0.5dB Flatness to 4.2MHz on CV Output
Equalizer and Notch Filter for Driving RF Modulator
with Group Delay of -180ns
In a typical application, the composite video from the
DAC is AC coupled into the filter. The CV input has DC-
restore circuitry to clamp the DC input levels during
video synchronization. The clamp pulse is derived from
the CV channel.
.
No External Frequency Selection Components
or Clocks
.
.
.
.
.
.
< 5ns Group Delay on CV Output
AC-Coupled Input
All outputs are capable of driving 2VPP, AC- or DC-
coupled, into either a single or dual video load. A single
video load consists of
a series 75Ω impedance
AC- or DC-Coupled Output
Capable of PAL Frequency for CV
Continuous Time Low-Pass Filters
matching resistor connected to a terminated 75Ω line.
This presents a total of 150Ω of loading to the part. A
dual load would be two of these in parallel, which
presents a total of 75Ω to the part. The gain of the CV
signal is 6dB with 1VPP input levels. All video channels
are clamped during synchronization to establish the
appropriate output voltage reference levels.
<1.4% Differential Gain with 0.7° Differential Phase
on CV Channel
.
Integrated DC Restore Circuitry with Low Tilt
Related Resources
Applications
.
AN-6024 – FMS6xxx Product Series Understanding
Analog Video Signal Clamps, Bias, DC Restore,
and AC or DC coupling Methods
.
.
.
Cable Set-Top Boxes
Satellite Set-Top Boxes
DVD Players
.
AN-6041 – PCB Layout Considerations for Video
Filter / Drivers
Ordering Information
Operating
Temperature Range
Part Number
Package
Packing Method
8-Lead, Small-Outline Integrated Circuit (SOIC),
JEDEC MS-012, .150" Narrow Body
2500 Units
per Reel
FMS6404CSX
-40°C to +70°C
© 2011 Fairchild Semiconductor Corporation
FMS6404 • Rev. 1.0.0
www.fairchildsemi.com
Block Diagram
Figure 1. Block Diagram
Pin Configuration
Figure 2. Pin Assignments (Top View)
Pin Definitions
Pin#
Name
CV In
EQ_Notch
GND
Type
Input
Output
Power
NA
Description
Composite video input
1
2
3
4
5
6
7
8
Composite video output to RF modulator
Device ground connection
No connection
NC
NC
NA
No connection
NC
NA
No connection
Vcc
Power
Output
Device power connection
Composite video output
CV Out
© 2011 Fairchild Semiconductor Corporation
FMS6404 • Rev. 1.0.0
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.3
-0.3
Max.
6.0
Unit
V
DC Supply Voltage
VIO
Analog and Digital I/O
VCC+0.3
100
V
VOUT
Maximum Output Current, Do Not Exceed
mA
Electrostatic Discharge Information
Symbol
Parameter
Min.
Unit
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
8
2
ESD
kV
Reliability Information
Symbol
Parameter
Min.
Typ.
Max.
+150
+150
+300
Unit
°C
TJ
TSTG
TL
Junction Temperature
Storage Temperature Range
-65
°C
Lead Temperature (Soldering, 10 Seconds)
°C
Thermal Resistance, JEDEC Standard, Multilayer Test Board, Still
Air
90
°C/W
JA
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Min.
0
Typ.
Max.
+70
Unit
°C
Operating Temperature Range
Supply Voltage Range
VCC
4.75
5.00
5.25
V
DC Electrical Characteristics
TA=25°C, VCC=5.0V, RS=37.5ꢀ, all inputs are AC-coupled with 0.1µF, and all outputs are AC coupled with 220µF into
150ꢀ load; unless otherwise noted.
Symbol
VCC
Parameter
Condition
Min.
4.75
50
Typ.
5.00
70
Max.
5.25
90
Unit
V
Supply Voltage Range
Quiescent Supply Current
Video Input Voltage Range
VS Range
ICC
VS=+5.0V, No Load
mA
VPP
dB
VIN
Referenced to GND if DC Coupled
1.4
PSRR
ISC
Power Supply Rejection Ratio DC
Output Short Circuit Current CV, EQ_NOTCH to GND
-50
85
mA
© 2011 Fairchild Semiconductor Corporation
FMS6404 • Rev. 1.0.0
www.fairchildsemi.com
3
AC Electrical Characteristics
TA=25°C, VCC=5.0V, RS=37.5ꢀ, all inputs are AC-coupled with 0.1µF, and all outputs are AC coupled with 220µF into
150ꢀ load, unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
AVCV
Low Frequency Gain CVOUT at 400kHz
5.8
6.0
6.2
dB
Low Frequency Gain
at 400kHz
AVEQ
CVsync
EQsync
tCLAMP
fFLAT
5.7
6.0
6.4
dB
(EQ_NOTCH)
CVOUT Output Level
(During Sync)
Sync Present on CVIN (After 6dB Gain)
Sync Present on CVIN (After 6dB Gain)
Settled to within 10mV
0.35
0.35
5
0.50
0.50
V
V
EQ_NOTCH Output Level
(During Sync)
Clamp Response Time
CVOUT
ms
dB
Gain Flatness to 4.2MHz
CVOUT
-0.5
0
0.5
fC
fSB
-3dB Bandwidth
CVOUT Channel
6.7
40
7.6
50
MHz
dB
%
Stopband Attenuation CVOUT at 27MHz
dG
Differential Gain
Differential Phase
Output Distortion
Crosstalk
CVOUT
1.4
0.7
0.3
-50
3.0
1.5
dq
CVOUT
°
THD
XTALK
VOUT=1.4Vpp at 3.58MHz
VOUT=1.4Vpp at 3.58MHz
%
dB
NTC-7 Weighting 4.2MHz Low-Pass
VIN=714mV, VOUT=1.428VPP/1.010Vrms
SNR
SNR CVOUT Channel
70
65
75
70
dB
dB
NTC-7 Weighting 4.2MHz Low-Pass VIN
=714mV VOUT=1.428Vpp/1.010Vrms
SNR EQ_NOTCH Channel
tpd
Propagation Delay
at 400kHz
112
0
ns
ns
%
GD
Group Delay CVOUT
at 3.58MHz (Reference to 400KHz)
f=3.58MHz (Reference to 400kHz)
-5
98
5
tCLGCV
tCLDCV
tGDEQ
Chroma-Luma Gain CVOUT
100
0
102
10
Chroma-Luma Delay CVOUT f=3.58MHz (Reference to 400kHz)
-10
-195
ns
ns
Group Delay EQ_NOTCH
f=3.58MHz (Reference to 400kHz)
-180
-165
Chroma-Luma Gain
EQ_NOTCH
tCLGEQ
tCLDEQ
f=3.58MHz (Reference to 400kHz)
95
100
105
%
Chroma-Luma Delay
EQ_NOTCH
f=3.58MHz (Reference to 400kHz)
-195
-180
-165
ns
dGEQ
dqEQ
Differential Gain
EQ_NOTCH Channel
EQ_NOTCH Channel
0.3
0.30
0
1.0
0.75
0.5
%
%
Differential Phase
MCF
Modulator Channel Flatness EQ_NOTCH from 400kHz to 3.75MHz
-0.5
-0.5
14
dB
dB
dB
dB
dB
AVPK
Gain Peaking
EQ_NOTCH from >3.75MHz to 4.2MHz
EQ_NOTCH at 4.425MHz
EQ_NOTCH at 4.5MHz
0
0.5
Atten1
Atten2
Atten3
Notch Attenuation 1
Notch Attenuation 2
Notch Attenuation 3
20
EQ_NOTCH at 4.6MHz
14
Passband Group Delay
EQ_NOTCH
tPASS
f=400kHz to f=3MHz
-35
35
ns
© 2011 Fairchild Semiconductor Corporation
FMS6404 • Rev. 1.0.0
www.fairchildsemi.com
4
Typical Performance Characteristics
Unless otherwise noted, TA = 25°C, VCC = 5.0V, Rs = 37.5ꢀ, and AC-coupled output into 150ꢀ load, CVOUT
.
Figure 3. Frequency Response
Figure 4. Group Delay vs. Frequency
Figure 5. Differential Gain
Figure 6. Differential Phase
Figure 7. Noise vs. Frequency
© 2011 Fairchild Semiconductor Corporation
FMS6404 • Rev. 1.0.0
www.fairchildsemi.com
5
Typical Performance Characteristics
Unless otherwise noted, TA = 25°C, VCC = 5.0V, Rs = 37.5ꢀ, and AC-coupled output into 150ꢀ load, CVOUT
.
Figure 8. Modulator vs. Frequency Response
Figure 9. Delay Modulator Output
Figure 10. Differential Gain, MODOUT
Figure 11. Differential Phase, MODOUT
Figure 12. Noise vs. Frequency Modulator Channel
Figure 13. Group Delay vs. Frequency
© 2011 Fairchild Semiconductor Corporation
FMS6404 • Rev. 1.0.0
www.fairchildsemi.com
6
Applications Information
The selection of the coupling capacitor is a function of
the subsequent circuit input impedance and the leakage
current of the input being driven. To obtain the highest
quality output video signal, the series termination
resistor must be placed as close to the device output pin
as possible. This greatly reduces the parasitic
capacitance and inductance effect on the output driver.
The distance from the device pin to the series termination
resistor should be no greater than 2.54mm (0.1in).
Layout Considerations
General layout and supply bypassing play a major role
in
high-frequency
performance
and
thermal
characteristics. Fairchild offers a four-layer board with
full power and ground planes board to guide layout and
aid device evaluation. Following this layout configuration
provides
optimum
performance
and
thermal
characteristics for the device. For best results, follow the
steps and recommended routing rules below.
Recommended Routing / Layout Rules
.
.
Do not run analog and digital signals in parallel.
Use separate analog and digital power planes to
supply power.
.
.
.
.
Traces must run on top of the ground plane.
No trace should run over ground/power splits.
Avoid routing at 90-degree angles.
Figure 14. Termination Resistor Placement
Minimize clock and video data trace length
differences.
Thermal Considerations
.
.
.
.
.
Include 10μF and 0.1μF ceramic power supply
bypass capacitors.
Since the interior of most systems, such as set-top
boxes, TVs, and DVD players; is at +70ºC;
consideration must be given to providing an adequate
heat sink for the device package for maximum heat
dissipation. When designing a system board, determine
how much power each device dissipates. Ensure that
devices of high power are not placed in the same
location, such as directly above (top plane) or below
(bottom plane) each other on the PCB.
Place the 0.1μF capacitor within 2.54mm (0.1in)
of the device power pin.
Place the 10μF capacitor within 19.05mm (0.75in)
of the device power pin.
For multi-layer boards, use a large ground plane to
help dissipate heat.
For two-layer boards, use a ground plane that
extends beyond the device body at least 12.7mm
(0.5in) on all sides. Include a metal paddle under
the device on the top layer.
PCB Thermal Layout Considerations
.
Understand the system power requirements and
environmental conditions.
.
Minimize all trace lengths to reduce series
inductance.
.
.
Maximize thermal performance of the PCB.
Consider using 70μm of copper for high-power
designs.
Output Considerations
.
.
.
.
Make the PCB as thin as possible by reducing
FR4 thickness.
The outputs are DC offset from the input by 150mV;
therefore, VOUT = 2 • VIN DC + 150mV. This offset is
required for optimal performance from the output driver
and is held at the minimum value to decrease the
standing DC current into the load. Since the FMS6404
has a 2 x (6dB) gain, the output is typically connected
via a 75ꢀ-series back-matching resistor, followed by the
75ꢀ video cable. Due to the inherent divide-by-two of
this configuration, the blanking level at the load of the
video signal is always less than 1V. When AC-coupling
the output, ensure that the coupling capacitor passes
the lowest frequency content in the video signal and that
line time distortion (video tilt) is kept as low as possible.
Use vias in power pad to tie adjacent layers
together.
Remember that baseline temperature is a function
of board area, not copper thickness.
Modeling techniques provide a first-order
approximation.
© 2011 Fairchild Semiconductor Corporation
FMS6404 • Rev. 1.0.0
www.fairchildsemi.com
7
Physical Dimensions
5.00
A
4.80
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.51
0.33
0.10 C
x 45°
OPTION A - BEVEL EDGE
0.50
0.25
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.40
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 15. 8-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, .150" Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FMS6404 • Rev. 1.0.0
www.fairchildsemi.com
8
© 2011 Fairchild Semiconductor Corporation
FMS6404 • Rev. 1.0.0
www.fairchildsemi.com
9
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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