FMS6410BCSX [ONSEMI]
视频驱动器，双沟道，带集成滤波器和复合视频加法器;
| 型号： | FMS6410BCSX |
| 厂家： | 
ONSEMI |
| 描述： | 视频驱动器，双沟道，带集成滤波器和复合视频加法器 驱动 光电二极管 商用集成电路 驱动器 |
| 文件： | 总10页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
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October 2006
FMS6410B
Dual-Channel Video Drivers with Integrated Filters and
Composite Video Summer
Features
Description
■ 7.1MHz fifth-order Y,C filters with composite summer
The FMS6410B is a dual Y/C fifth-order Butterworth low-
pass video filter optimized for minimum overshoot and
flat group delay. The device also contains a summing cir-
cuit to generate filtered composite video. In a typical
application, the Y and C input signals from DACs are AC
coupled into the filters. Both channels have DC restore
circuitry to clamp the DC input levels during video sync.
The Y and C channels use separate feedback clamps.
The clamp pulse is derived from the Y channel.
■ 50dB stopband attenuation at 27MHz on Y, C, and CV
outputs
■ Better than 0.1dB flatness to 4.5MHz on Y, C, and CV
outputs
■ No external frequency selection components or clocks
■ < 5ns group delay on Y, C, and CV outputs
■ AC-coupled inputs
■ AC- or DC-coupled outputs
All outputs are capable of driving 2Vpp, AC or DC cou-
pled, into either a single or dual video load. A single
video load consists of a series 75Ω impedance matching
resistor connected to a terminated 75Ω line. This pre-
sents a total of 150Ω of loading to the part. A dual load is
two of these in parallel, which presents a total of 75Ω to
the part. The gain of the Y, C, and CV signals is 6dB with
1Vpp input levels. All video channels are clamped during
sync to establish the appropriate output voltage refer-
ence levels.
■ Capable of PAL frequency selection components or
clocks
■ 0.3% differential gain with 0.2° differential phase on
Y, C, and CV channels
■ Integrated DC restore circuitry with low tilt
■ Lead-free SOIC-8 package
Applications
■ Cable and satellite set-top boxes
■ DVD players
■ Personal Video Recorders (PVR)
■ Video On Demand (VOD)
Block Diagrams
VCC
7
Sync Strip
Reference and
Timing
YIN
1
8
6
YOUT
6dB
gM
gM
250mV
+
Σ
CVOUT
+
250mV
CIN
4
5
COUT
6dB
3
GND
Figure 1. Block Diagram
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
www.fairchildsemi.com
Ordering Information
Pack
Qty.
Part Number
FMS6410BCS
FMS6410BCSX
Package
SOIC-8
Operating Temperature Range
0°C to 70°C
Pb-Free
Yes
Container
Rail
95
SOIC-8
0°C to 70°C
Yes
Reel
2500
Pin Configuration
FAIRCHILD
1
2
3
4
8
7
6
5
YIN
NC
YOUT
FMS6410B
8L SOIC
VCC
GND
CIN
CVOUT
COUT
Figure 2. Pin Configuration
Pin Assignments
Pin#
Pin
Type
Description
Luminance (luma) input: This pin is typically connected to the luma or composite
video output pin from the external video encoder.
1
YIN
Input
2
3
NC
No connect.
GND
Input
Input
Must be tied to ground.
Chrominance (chroma) Input: This pin is typically connected to the chroma output
pin from the external video encoder.
4
CIN
5
6
7
8
COUT
CVOUT
VCC
Output Filtered chrominance video output from the CIN channel.
Output Composite video output: This pin is the sum of YOUT and COUT
Input +5V supply.
Output Filtered luminance output from the YIN channel.
.
YOUT
Typical Application Diagram
FMS6410B may also
be DC-Coupled
0.1µF
1
75
75
75
75
220µF
220µF
220µF
220µF
8
6
YIN
YIN
YOUT
YOUT
75
FMS6410B
CVOUT
To TV
75
75
75
0.1µF
4
CIN
CIN
CVOUT
to VCR
COUT
GND
3
5
VCC
7
5V
COUT
0.1µF
10µF
Figure 3. AC- or DC-Coupled Application Diagram
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
www.fairchildsemi.com
2
Absolute Maximum Ratings
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables
are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the
conditions for actual device operation.
Parameter
Min.
-0.3
-0.3
Max.
6.0
Unit
V
DC Supply Voltage
Analog and Digital I/O
Vcc + 0.3
40
V
Output Current Any One Channel, Do Not Exceed
mA
Reliability Information
Symbol
TJ
Parameter
Min. Typ. Max. Unit
Junction Temperature
150
150
300
°C
°C
TSTG
TL
Storage Temperature Range
Lead Temperature (Soldering, 10s)
-65
°C
ΘJA
Thermal Resistance, JEDEC Standard Multi-Layer Test Boards, Still Air
115
°C/W
Recommended Operating Conditions
Symbol
TA
Parameter
Min. Typ. Max. Unit
Operating Temperature Range
Supply Voltage Range
0
70
°C
V
VCC
4.75
5.00
5.25
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
www.fairchildsemi.com
3
DC Electrical Characteristics
TA = 25°C, VCC = 5V, VIN = 1Vpp; all inputs are AC coupled with 0.1µF; all outputs are AC coupled with 220µF into
150Ω loads; referenced to 400kHz; unless otherwise noted.
Symbol
ICC
Parameter
Supply Current(1)
Input Voltage Maximum
Conditions
Min. Typ. Max. Unit
No Load
50
1.4
60
60
mA
Vpp
dB
VIN
PSRR Power Supply Rejection Ratio
All Channels, DC
Notes:
1. 100% tested at 25°C.
AC Electrical Characteristics
TA = 25°C, VCC = 5V, VIN = 1Vpp; all inputs are AC coupled with 0.1µF; all outputs are AC coupled with 220µF into
150Ω loads; referenced to 400kHz; unless otherwise noted.
Symbol
AV
Parameter
Channel Gain(1)
COUT Output Level (during sync)(1) Sync Present on YIN (after 6dB gain)
YOUT Output Level (during sync)(1) Sync Present on YIN (after 6dB gain)
Conditions
All Channels
Min. Typ. Max. Unit
5.75
6.00
1.0
6.25
1.3
dB
V
Csync
Ysync
0.35
0.50
V
CVOUT Output Level (during
Sync Present on YIN (after 6dB gain)
sync)(1)
CVsync
0.35
0.50
V
tCLAMP Clamp Response Time
Y Channel, Settled to within 10mV
All Channels
10
0
ms
dB
fFLAT
fC
Gain Flatness to 4.5MHz
-3dB Bandwidth(1)
Stopband Attenuation(1)
Differential Gain
All Channels
6.7
42
7.1
50
MHz
dB
fSB
All Channels at 27MHz
All Channels
dG
0.3
0.2
0.3
-50
%
dP
Differential Phase
All Channels
deg
%
THD
Output Distortion
VOUT = 1.4Vpp, 3.58MHz
at 3.58MHz
XTALK Crosstalk
dB
All Channels, NTC-7 weighting,
4.2MHz LP, 100kHz HP
SNR
Signal-to-Noise Ratio
82
dB
tpd
Propagation Delay
All Channels
115
4
ns
ns
ns
%
GD
Group Delay Deviation
All Channels at 3.58MHz
at 1MHz
tSKEW Skew Between YOUT and COUT
0
(1)
tCLGCV Chroma-Luma Gain CVOUT
f = 3.58MHz (Ref. to YIN at 400kHz)
f = 3.58MHz (Ref. to YIN at 400kHz)
96
100
4
104
tCLDCV Chroma-Luma Delay CVOUT
ns
Notes:
1. 100% tested at 25°C.
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
www.fairchildsemi.com
4
Applications Information
Functional Description
Layout Considerations
This product is a two-channel, monolithic, continuous-
time, video filter designed for reconstructing the lumi-
nance and chrominance signals from an S-Video D/A
source. Composite video output is generated by sum-
ming the Y and C outputs. The chip is designed to have
AC-coupled inputs and work with either AC- or DC-cou-
pled outputs.
General layout and supply bypassing play major roles in
high-frequency performance and thermal characteristics.
Fairchild
offers
a
demonstration
board,
FMS6410BDEMO, to guide layout and aid device testing
and characterization. The FMS6410BDEMO is a four-
layer board with a full power and ground plane. For opti-
mum results, follow the steps below as a basis for high-
frequency layout:
The reconstruction filters provide a fifth-order Butter-
worth response with group delay equalization. This pro-
vides a maximally flat response in terms of delay and
amplitude. Each of the three outputs is capable of driving
2Vpp into a 75Ω load.
■ Include 10μF and 0.1μF ceramic bypass capacitors.
■ Place the 10μF capacitor within 0.75 inches of the
power pin.
■ Place the 0.1μF capacitor within 0.1 inches of the
power pin.
All channels are clamped during the sync interval to set
the appropriate minimum output DC level. With this oper-
ation, the effective input time constant is greatly reduced,
which allows use of small, low-cost coupling capacitors.
The net effect is that the input settles to 10mV in 10ms
for any DC shifts present in the input video signal.
■ If using DC-coupled outputs, use a large ground plane
to help dissipate heat.
■ Minimize all trace lengths to reduce series induc-
tances.
Output Interface
In most applications, the input coupling capacitors are
0.1µF. The Y and C inputs typically sink 1µA of current
during active video, which normally tilts a horizontal line
by 2mV at the Y output. During sync, the clamp restores
this leakage current by sourcing an average of 20µA
over the clamp interval. Any change in the coupling
capacitor values affect the amount of tilt per line. Any
reduction in tilt comes with an increase in settling time.
To obtain the highest quality output signal, place the
series termination resistor as close to the device output
pin as possible. This greatly reduces the parasitic
capacitance and inductance effect on the output of the
driver. Place the series termination resistor less than 0.1
inches from the device pin, as shown in Figure 4.
Luminance (Y) I/O
The typical luma input is driven by either a low-imped-
ance source of 1Vpp or the output of a 75Ω terminated
line driven by the output of a current DAC. In either case,
the input must be capacitively coupled to allow the sync-
detect and DC-restore circuitry to operate properly.
All outputs are capable of driving 2Vpp, AC or DC cou-
pled, into either a single or dual video load. A single
video load consists of a series 75Ω impedance matching
resistor connected to a terminated 75Ω line, presenting a
total of 150Ω of loading to the part. A dual load is two of
these in parallel, which presents a total of 75Ω to the
part. The gain of the Y, C, and CV signals is 6dB with
1Vpp input levels.
Figure 4. 75Ω Series Resistor 0.1 Inches from Pin
Figure 5 is the schematic representation of a video filter/
driver used in a system as the output driver to a media
device. In this case, the composite video signal is termi-
nated by the media device and the S-video output termi-
nations are open. It is very critical to have the series
termination resistors close to the output pins of the
device to minimize the effects of parasitic capacitance on
the filter output driver which may show up as noise on
the CV output.
Chrominance (C) I/O
The chrominance input can be driven in the same man-
ner as the luminance input, but is typically only a 0.7Vpp
signal.
Since the chrominance signal doesn't contain any DC
content, the output signal can be AC coupled using a
capacitor as small as 0.1µF if DC coupling is not desired.
Composite Video (CV) Output
The composite video output driver is same as the other
outputs.
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
www.fairchildsemi.com
5
Applications Information (Continued)
Fairchild Filter Drive r
75 Ohm
Clamp/
Bias
Buf
LPF
Series
Termanatio n
Filter/Driver set for gain of 2 X
Resistor
S-Video
0.1 inche s
from DUT
pin
75 Ohm
Summer
RCA JACK
Coax
ADC
Series
75 Ohm
Termanatio n
Resistor
0.1 inche s
from DUT
pin
Media
Fairchild Filter Drive r
75 Ohm
Clamp/
Bias
Buf
LPF
Series
Termanatio n
Filter/Driver set for gain of 2 X
Resistor
0.1 inche s
from DUT
pin
Figure 5. Schematic Representation of a Video Filter / Driver
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
www.fairchildsemi.com
6
Physical Dimensions
Figure 6. 8-Lead Small Outline Integrated Circuit (SOIC) Package
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
www.fairchildsemi.com
7
© 2004 Fairchild Semiconductor Corporation
FMS6410B Rev. 1.0.2
www.fairchildsemi.com
8
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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