FQB12P20TM [ONSEMI]
功率 MOSFET，P 沟道，QFET®，-200 V，-11.5 A，470 mΩ，D2PAK;
| 型号： | FQB12P20TM |
| 厂家： | 
ONSEMI |
| 描述： | 功率 MOSFET，P 沟道，QFET®，-200 V，-11.5 A，470 mΩ，D2PAK 开关 脉冲 晶体管 |
| 文件： | 总8页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET – P-Channel, QFET)
-200 V, -11.5 A, 470 mW
FQB12P20
General Description
These P−Channel enhancement mode power field effect transistors
are produced using ON Semiconductor’s proprietary, planar stripe,
DMOS technology.
www.onsemi.com
This advanced technology has been especially tailored to minimize
on−state resistance, provide superior switching performance, and
withstand high energy pulse in the avalanche and commutation mode.
These devices are well suited for high efficiency switching DC/DC
converters.
V
R
MAX
I MAX
D
DSS
DS(ON)
−200 V
0.47 ꢀ @ −10 V
−11.5 A
S
Features
• −11.5 A, −200 V, R
G
= 0.47 ꢀ @ V = −10 V
GS
DS(on)
• Low Gate Charge (Typical 31 nC)
• Low Crss (typical 30 pF)
• Fast Switching
D
• 100% Avalanche Tested
P−CHANNEL MOSFET
• Improved dv/dt Capability
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Drain−Source Voltage
Drain Current − Continuous (T = 25°C)
FQB12P20
−200
−11.5
−7.27
−46
Unit
V
V
DSS
2
D PAK−3 (TO−263, 3−LEAD)
I
D
A
C
CASE 418AJ
− Continuous (T = 100°C)
C
A
I
Drain Current − Pulsed (Note 1)
A
MARKING DIAGRAM
DM
V
GSS
Gate−Source Voltage
+30
V
E
Single Pulsed Avalanche Energy (Note 2)
Avalanche Current (Note 1)
810
mJ
A
AS
$Y&Z&3&K
FQB
I
−11.5
12
AR
E
AR
Repetitive Avalanche Energy (Note 1)
Peak Diode Recovery dv/dt (Note 3)
mJ
V/ns
W
12P20
dv/dt
−5.5
P
Power Dissipation (T = 25°C) *
3.13
D
A
Power Dissipation (T = 25°C)
120
W
C
− Derate above 25°C
0.96
W/°C
°C
FQB12P20 = Specific Device Code
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Digit Date Code
T , T
Operating and Storage Temperature
Range
−55 to +150
J
STG
T
L
Maximum lead temperature for soldering
purposes, 1/8” from case for 5 seconds
300
°C
= Lot Run Traceability Code
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
*When mounted on the minimum pad size recommended (PCB Mount)
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 9.2 mH, I = −11.5 A, V = −50 V, R = 25 ꢀ, Starting T = 25°C
AS
DD
G
DSS,
J
3. I ≤ −11.5 A, di/dt ≤ 300 A/ꢁ s, V ≤ BV
Starting T = 25°C
J
SD
DD
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
December, 2019 − Rev. 2
FQB12P20/D
FQB12P20
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Parameter
Typ
−
Max
1.04
40
Unit
°C/W
°C/W
°C/W
R
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Ambient *
Thermal Resistance, Junction−to−Ambient
ꢂ
JC
R
−
ꢂ
JA
R
−
62.5
ꢂ
JA
*When mounted on the minimum pad size recommended (PCB Mount)
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
C
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain−Source Breakdown Voltage
V
I
= 0 V, I = −250 ꢁ A
−200
−
−
−
−
−
−
−
−
V
V/°C
ꢁ A
DSS
GS
D
ꢃ
B
V
/
ꢃ
T
B
r
e
a
k
d
o
w
n
V
o
l
t
a
g
e
T
e
m
p
e
r
a
t
u
r
e
C
o
e
f
f
i
c
i
e
n
t
= −250 ꢁ A, Referenced to 25°C
= −200 V, V = 0 V
−
−
−
−
−
DSS
J
D
I
Zero Gate Voltage Drain Current
V
V
V
V
−1
DSS
DS
GS
= −160 V, T = 125°C
−10
−100
100
ꢁ
A
DS
GS
GS
C
I
Gate−Body Leakage Current, Forward
Gate−Body Leakage Current, Reverse
= −30 V, V = 0 V
nA
GSSF
DS
I
= 30 V, V = 0 V
nA
GSSR
DS
ON CHARACTERISTICS
V
Gate Threshold Voltage
V
DS
V
GS
V
DS
= V , I = −250 ꢁ A
−3.0
−
−
−5.0
0.47
−
V
ꢀ
S
GS(th)
DS(on)
GS
D
R
Static Drain−Source On−Resistance
Forward Transconductance
= −10 V, I = −5.75 A
0.36
6.4
D
g
FS
= −40 V, I = −5.75 A (Note 4)
−
D
DYNAMIC CHARACTERISTICS
C
C
Input Capacitance
V
DS
= −25 V, V = 0 V, f = 1.0 MHz
−
−
−
920
190
30
1200
250
40
pF
pF
pF
iss
GS
Output Capacitance
oss
C
Reverse Transfer Capacitance
rss
SWITCHING CHARACTERISTICS
t
Turn−On Delay Time
Turn−On Rise Time
Turn−Off Delay Time
Turn−Off Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
V
= −100 V, I = −11.5 A,
−
−
−
−
−
−
−
20
195
40
50
400
90
130
40
−
ns
ns
d(on)
DD
G
D
R
= 25 ꢀ
t
r
(Note 4, 5)
t
ns
d(off)
t
f
60
ns
Q
V
DS
V
GS
= −160 V, I = −11.5 A,
31
nC
nC
nC
g
D
= −10 V
Q
8.1
16
gs
(Note 4, 5)
Qg
−
d
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUMUM RATINGS
I
Maximum Continuous Drain−Source Diode Forward Current
Maximum Pulsed Drain−Source Diode Forward Current
−
−
−
−
−
−
−
−11.5
−46
−5.0
−
A
A
S
I
SM
V
SD
Drain−Source Diode Forward Voltage
Reverse Recovery Time
V
V
= 0 V, I = −11.5 A
−
V
GS
S
t
= 0 V, I = −11.5 A,
180
1.44
ns
ꢁ C
rr
GS
S
dI / dt = 100 A/ꢁ s (Note 4)
F
Q
Reverse Recovery Charge
−
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: Pulse width ≤ 300 ꢁ s, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
www.onsemi.com
2
FQB12P20
TYPICAL CHARACTERISTICS
V
GS
Top:
−15.0 V
−10.0 V
−8.0 V
−7.0 V
−6.5 V
−6.0 V
1
0
1
10
10
10
Bottom: −5.5 V
150°C
−55°C
0
10
25°C
Notes:
1. 250 ꢁ s Pulse Test
Notes:
1. V = −40 V
DS
2. T = 25°C
2. 250 ꢁ s Pulse Test
C
−1
−1
10
10
−1
0
1
2
4
6
8
10
3.0
35
10
10
10
−V , Drain−Source Voltage (V)
DS
−V , Gate−Source Voltage (V)
GS
Figure 1. On Characteristics
Figure 2. Transfer Characteristics
2.0
1.5
1.0
0.5
0.0
1
10
V
= − 10 V
GS
0
10
V
= − 20 V
GS
Notes:
150°C
25°C
1. V = 0 V
GS
Note: T = 25°C
2. 250 ꢁ s Pulse Test
J
−1
10
0
10
20
30
40
0.0
0.5
1.0
1.5
2.0
2.5
−I , Drain Current (A)
D
−V , Source−Drain Voltage (V)
SD
Figure 3. On−Resistance Variation vs. Drain Current
Figure 4. Body Diode Forward Voltage
and Gate Voltage
Variation vs. Source Current and Temperature
12
2400
C
C
C
= C + C (C = shorted)
gs gd ds
iss
= C + C
oss
rss
ds
gd
V
= −40 V
DS
= C
gd
10
8
2000
1600
1200
800
400
0
V
= −100 V
DS
V
= −160 V
DS
C
6
iss
C
oss
4
C
rss
2
Note: I = 11.5 A
D
0
−1
0
1
10
0
5
10
15
20
25
30
10
10
−V , Drain−Source Voltage (V)
DS
Q , Total Gate Charge (nC)
G
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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3
FQB12P20
TYPICAL CHARACTERISTICS (continued)
2.5
2.0
1.5
1.0
1.2
1.1
1.0
0.9
0.8
0.5
Notes:
Notes:
1. V = −10 V
1. V = 0 V
GS
GS
2. I = 250 ꢁ A
D
2. I = −5.75 A
D
0.0
−100
−100
−50
0
50
100
150
200
−50
0
50
100
150
200
T , Junction Temperature (°C)
J
T , Junction Temperature (°C)
J
Figure 7. Breakdown Voltage Variation vs.
Temperature
Figure 8. On−Resistance Variation vs.
Temperature
12
10
8
Operation in This Area
2
10
is Limited by R
DS(on)
100 ꢁ s
1 ms
10 ms
1
10
6
DC
4
0
10
Notes:
2
1. TC = 25°C
2. TJ = 150°C
3. Single Pulse
−1
10
0
0
1
2
10
10
10
25
50
75
100
125
150
−V , Drain−Source Voltage (V)
DS
T , Case Temperature (°C)
C
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current vs.
Case Temperature
0
10
D = 0.5
0.2
Notes:
0.1
1. Z
(t) = 1.04°C/W Max.
ꢂ
JC
10−1
2. Duty Factor, D = t / t
1
* Z
2
JC
0.05
3. T − T = P
(t)
ꢂ
JM
C
DM
0.02
PDM
0.01
single pulse
t1
−2
t2
10
−5
−4
−3
−2
−1
0
1
10
10
10
10
10
10
10
t , Square Wave Pulse Duration (s)
1
Figure 11. Capacitance Characteristics
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4
FQB12P20
VGS
Same Type
as DUT
50 kꢀ
Qg
12 V
−10 V
200 nF
300 nF
VDS
VGS
Qgs
Qgd
DUT
−3 mA
Charge
Figure 12. Gate Charge Test Circuit & Waveform
RL
ton
toff
VDS
td(on)
t
td(off)
r
VDD
t
VGS
f
V
GS 10%
R
G
DUT
−10 V
90%
VDS
Figure 13. Resistive Switching Test Circuit & Waveforms
BVDSS
1
2
LI2AS
L
EAS
+
BVDSS * VDD
VDS
tp
Time
ID
VDD
VDS (t)
RG
VDD
ID (t)
DUT
−10 V
IAS
tp
BVDSS
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
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5
FQB12P20
+
VDS
_
DUT
ISD
L
Driver
RG
Compliment of DUT
VDD
(N−Channel)
VGS
S dv/dt controlled by R
G
S I controlled by pulse period
SD
Gate Pulse Width
Gate Pulse Period
VGS
D =
10 V
(Driver)
Body Diode Reverse Current
IRM
ISD
(DUT)
di/dt
IFM , Body Diode Forward Current
VSD
VDS
(DUT)
Body Diode
VDD
Forward Voltage Drop
Body Diode Recovery dv/dt
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
Marking
Package
Reel Size
Tape Width
Shipping
2
FQB12P20TM
FQB12P20
D PAK
330 mm
24 mm
800 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
QFET is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
DATE 11 MAR 2021
SCALE 1:1
XXXXXX = Specific Device Code
A
= Assembly Location
WL
Y
= Wafer Lot
= Year
GENERIC MARKING DIAGRAMS*
WW
W
M
G
AKA
= Work Week
= Week Code (SSG)
= Month Code (SSG)
= Pb−Free Package
= Polarity Indicator
XX
AYWW
XXXXXXXXG
AKA
XXXXXXXXG
AYWW
XXXXXX
XXYMW
XXXXXXXXX
AWLYWWG
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
IC
Standard
Rectifier
SSG
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON56370E
D2PAK−3 (TO−263, 3−LEAD)
PAGE 1 OF 1
DESCRIPTION:
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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