FQI7N60TU_技术文档

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FQB7N60 / FQI7N60

N-Channel QFET^®MOSFET

600 V, 7.4 A, 1.0 Ω

Features

•

7.4 A, 600 V, R_DS(on)= 1.0 Ω (Max.) @V_GS= 10 V,

I_D= 3.7 A

Description

This N-Channel enhancement mode power MOSFET is

produced using ON Semiconductor’s proprietary

planar stripe and DMOS technology. This advanced

MOSFET technology has been especially tailored to

reduce on-state resistance, and to provide superior

switching performance and high avalanche energy

strength. These devices are suitable for switched mode

power supplies, active power factor correction (PFC), and

electronic lamp ballasts.

•

Low Gate Charge (Typ. 29 nC)

Low Crss (Typ. 16 pF)

100% Avalanche Tested

D

G

I²-PAK

G

D

S

D²-PAK

S

Absolute Maximum Ratings T_C= 25^oC unless otherwise noted.

S

FQB7N60TM

FQB7N60TM-WS

FQI7N60TU

Symbol

Parameter

Unit

V

I

Drain-Source Voltage

600

7.4

V

A

DSS

- Continuous (T = 25°C)

Drain Current

D

C

- Continuous (T = 100°C)

4.7

A

C

I

(Note 1)

Drain Current

- Pulsed

29.6

±ꢀ30

580

A

DM

V

E

I

Gate-Source Voltage

V

GSS

AS

(Note 2)

(Note 1)

(Note 3)

Single Pulsed Avalanche Energy

Avalanche Current

mJ

A

7.4

AR

E

Repetitive Avalanche Energy

Peak Diode Recovery dv/dt

14.2

4.5

mJ

V/ns

W

AR

dv/dt

Power Dissipation (T = 25°C) *

3.13

142

P

A

D

Power Dissipation (T = 25°C)

W

C

- Derate above 25°C

1.14

-55 to +150

W/°C

°C

T , T

Operating and Storage Temperature Range

Maximum Lead Temperature for Soldering,

1/8ꢀ from Case for 5 Seconds

J

STG

T

300

°C

L

Thermal Characteristics

FQB7N60TM

Symbol

Parameter

Unit

FQB7N60TM-WS

FQI7N60TU

R_JC

R_JA

Thermal Resistance, Junction to Case, Max.

0.88

62.5

40

Thermal Resistance, Junction to Ambient (Minimum Pad of 2-oz Copper), Max.

Thermal Resistance, Junction to Ambient (*1 in²Pad of 2-oz Copper), Max.

^oC/W

Publication Order Number:

October-2017,Rev. 3

FQI7N60/D

Package Marking and Ordering Information

Part Number

Top Mark

Package

Packing Method Reel Size

Tape Width

Quantity

FQB7N60TM

FQB7N60

D²-PAK

330 mm

24 mm

800 units

Tape and Reel

FQB7N60TM-WS

FQI7N60TU

FQB7N60S

FQI7N60

D²-PAK

I²-PAK

330 mm

24 mm

800 units

50 units

Tape and Reel

Tube

N/A

Electrical Characteristics T_C= 25^oC unless otherwise noted.

Symbol

Parameter

Test Conditions

Min. Typ.

Max.

Unit

Off Characteristics

BV

V

I

= 0 V, I = 250 µA

Drain-Source Breakdown Voltage

600

--

V

DSS

GS

D

∆BV

Breakdown Voltage Temperature

Coefficient

DSS

J

= 250 µA, Referenced to 25°C

0.67

V/°C

D

/

I

∆T

V

= 600 V, V = 0 V

--

10

100

-100

µA

nA

DSS

DS

GS

Zero Gate Voltage Drain Current

= 480 V, T = 125°C

DS

GS

C

I

= 30 V, V = 0 V

Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

GSSF

DS

= -30 V, V = 0 V

GSSR

DS

On Characteristics

V

= V , I = 250 µA

Gate Threshold Voltage

3.0

--

5.0

1.0

--

V

Ω

S

GS(th)

DS

GS

DS

GS

D

R

Static Drain-Source

On-Resistance

DS(on)

=10V,I =3.7A

0.8

6.4

D

g

= 50 V, I = 3.7 A

Forward Transconductance

--

FS

D

Dynamic Characteristics

C

Input Capacitance

--

1100

135

16

1430

175

21

pF

iss

V

= 25 V, V = 0 V,

GS

DS

Output Capacitance

oss

rss

f = 1.0 MHz

Reverse Transfer Capacitance

Switching Characteristics

t

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

--

30

80

65

60

29

7

70

170

140

130

38

ns

d(on)

V

= 300 V, I = 7.4 A,

DD

D

r

R

= 25 Ω

G

ns

d(off)

f

(Note 4)

ns

Q

nC

g

V

= 480 V, I = 7.4 A,

DS

D

--

= 10 V

gs

gd

GS

14.5

--

Drain-Source Diode Characteristics and Maximum Ratings

I

Maximum Continuous Drain-Source Diode Forward Current

--

7.4

29.6

1.4

--

A

S

I

Maximum Pulsed Drain-Source Diode Forward Current

SM

V

t

V

= 0 V, I = 7.4 A

Drain-Source Diode Forward Voltage

Reverse Recovery Time

--

V

SD

GS

S

= 0 V, I = 7.4 A,

320

2.4

ns

µC

rr

GS

S

dI / dt = 100 A/µs

Q

Reverse Recovery Charge

--

F

rr

ꢀꢁꢂꢃꢄꢅ

1. Repetitive rating : pulse-width limited by maximum junction temperature.

2. L = 19.5 mH, I_AS= 7.4 A, V_DD= 50 V, R_G= 25 Ω, starting T_J= 25^oC.

3. I_SD≤ 7.4 A, di/dt ≤ 200 A/μs, V_DD≤ BV_DSS, starting T_J= 25^oC.

4. Essentially independent of operating temperature.

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2

ꢀ !ꢁꢂꢃꢄꢅꢆꢇꢃꢈꢃꢂꢉꢊꢈꢁꢋꢉꢁꢂꢋ

V

Top : 15.0^GV^S

10.0 V

8.0 V

7.5 V

7.0 V

6.5 V

10¹

6.0 V

Bottom: 5.5 V

10⁰

ꢀ

150

ꢀ

25

ꢀ

Notes :

ꢀ

Notes :

ꢁ

1. V_DS= 50V

2. 250 s Pulse Test

1. 250 s Pulse Test

2. T_C= 25

ꢀ

-55

ꢁ

ꢂ

-1

10

-1

10

-1

10

10⁰

10¹

2

4

6

8

10

V_GS, Gate-Source Voltage [V]

V_DS, Drain-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

2.5

2.0

1.5

1.0

0.5

0.0

10¹

V_GS= 10V

V_GS= 20V

10⁰

ꢀ

Notes :

ꢀ

25

150

1. V_GS= 0V

2. 250 s Pulse Test

ꢀ

ꢁ

Note : T_J= 25

ꢁ

-1

0

5

10

15

20

25

10

0.2

0.4

0.6

0.8

1.0

1.2

I_D, Drain Current [A]

V_SD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

2000

12

10

8

C

_iss= C_gs+ C_gd(C_ds= shorted)

C_oss= C_ds+ C

gd

V_DS= 120V

V_DS= 300V

V_DS= 480V

C_rss= C

gd

1600

1200

800

400

0

C

iss

C

oss

6

4

ꢀ

Notes :

1. V_GS= 0 V

2. f = 1 MHz

C

rss

2

ꢀ

Note : I_D= 7.4A

0

5

10

15

20

25

30

35

-1

10

10⁰

10¹

Q_G, Total Gate Charge [nC]

V_DS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

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3

ꢀ !ꢁꢂꢃꢄꢅꢆꢇꢃꢈꢃꢂꢉꢊꢈꢁꢋꢉꢁꢂꢋꢅꢀꢀꢀꢀꢁꢂꢃꢄꢅꢆꢄꢇꢈꢉꢊ

1.2

1.1

1.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

ꢀ

Notes :

0.9

1. V_GS= 0 V

2. I_D= 250

ꢀ

Notes :

ꢁ

A

1. V = 10 V

2. I_D^G=^S3.7 A

0.8

-100

-50

0

50

100

150

200

-50

0

50

100

150

200

T_J, Junction Temperature [^oC]

T, Junction Temperature [^oC]

J

Figure 7. Breakdown Voltage Variation

vs. Temperature

Figure 8. On-Resistance Variation

vs. Temperature

8

10²

10¹

10⁰

10^-1

Operation in This Area

is Limited by R_DS(on)

6

4

2

0

100

s

µ

1 ms

10 ms

DC

ꢀ

Notes :

1. T_C= 25 ^o

C

2. T_J= 150 ^o

C

3. Single Pulse

10⁰

10¹

10²

10³

25

50

75

100

125

150

ꢀ

T_C, Case Temperature [

]

V_DS, Drain-Source Voltage [V]

Figure 9. Maximum Safe Operating Area

Figure 10. Maximum Drain Current

vs. Case Temperature

1 0 ⁰

D = 0 . 5

0 .2

ꢀ

N o t e s

:

ꢁ

1 . _C(t )

Z

=

0 .8 8

/W M a x .

ꢀ

J

2 . D u t y F a c t o r , D = t ₁/t ₂

1 0 ^-1

0 .1

3 . T _J

-

T _C

=

P _D

*

Z

_C(t )

ꢀ

M

J

0 .0 5

P_DM

0 .0 2

0 .0 1

t₁

s in g l e p u ls e

t₂

1 0 ^-2

1 0 ^-5

1 0 ^-4

1 0 ^-3

1 0 ^-2

1 0 ^-1

1 0 ⁰

1 0 ¹

t ₁

, R e c t a n g u l a r P u l s e D u r a t i o n [ s e c ]

Figure 11. Transient Thermal Response Curve

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4

V_GS

10V

Same Type

as DUT

50KΩ

Q_g

12V

200nF

300nF

V_DS

V_GS

Q_gs

Q_gd

DUT

I

= const.

3mA

G

Charge

Figure 12. Gate Charge Test Circuit & Waveform

R_L

V_DS

90%

V_DS

V_DD

V_GS

R_G

10%

V_GS

DUT

V

10V

GS

t_d(on)

t_r

t_d(off)

t_f

t _on

t _off

Figure 13. Resistive Switching Test Circuit & Waveforms

BV_DSS

--------------------

BV_DSS- V_DD

L

1

2

----

E_AS

=

L I_AS

V_DS

I _D

BV_DSS

I_AS

R_G

V_DD

I_D(t)

V

V_DS(t)

V_DD

V

DUT

1_G0V_S

GS

t _p

Time

Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms

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5

+

DUT

V_DS

_

I _SD

L

Driver

R_G

Same Type

as DUT

V_DD

V_GS

• dv/dt controlled by R_G

• I_SDcontrolled by pulse period

Gate Pulse Width

--------------------------

V_GS

D =

Gate Pulse Period

10V

( Driver )

I_FM, Body Diode Forward Current

I _SD

di/dt

( DUT )

I_RM

Body Diode Reverse Current

Body Diode Recovery dv/dt

V_SD

V_DS

( DUT )

V_DD

Body Diode

Forward Voltage Drop

Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

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6

Mechanical Dimensions

2

Figure 16. TO263 (D PAK), Molded, 2-Lead, Surface Mount

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in

any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to

verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms

and conditions, specif-ically the warranty therein, which covers ON Semiconductor products.

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7

Mechanical Dimensions

2

Figure 17. TO262 (I PAK), Molded, 3-Lead, Jedec Variation AA

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in

any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to

verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms

and conditions, specif-ically the warranty therein, which covers ON Semiconductor products.

www.onsemi.com

8

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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型号：	FQI7N60TU
厂家：	ONSEMI
描述：	N 沟道 QFET® MOSFET 600V，7.4A，1Ω 开关脉冲晶体管
文件：	总10页 (文件大小：945K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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