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September 2014

FSA9591 — USB Accessory Detection Switch with Integrated

Linear Battery Charger

Features

Description

.

Detection:

The FSA9591 is a USB accessory detection switch with an

integrated lithium ion (Li+) linear battery charger. The FSA9591 is

capable of detecting factory test modes, car kit type 1 and travel

adapter charger, USB data port, and USB chargers. Compliant

with the USB battery charging rev. 1.1 specification, the

FSA9591 can detect USB Standard Downstream Ports (SDP),

Dedicated Charging Ports (DCP), and Charging Downstream

Ports (CDP).

-

USB Data Cable

UART Serial Link

Charger Detection (CDP, DCP)

Factory-Mode Cables

Teletype (TTY) Converter

The integrated linear charger uses constant current, constant

voltage, and thermal control loops to charge Li+ batteries and

provide protection. The FSA9591 also includes two

programmable LDOs, capable of supplying 300mA each, for

powering other devices in mobile phones. Battery presence

detection via DETBAT_N and charging current sensing through

VICHG are also provided. V_{BUS_IN}pin can tolerate up to 28 V.

.

Linear Charger with up to 950 mA Charging Current Full-

Speed and High-Speed 2.0 Compliant

.

Automatic Switching with Available Interrupt

UART: RxD & TxD

USB: FS and HS 2.0 Compliant

Switch Type: USB, UART

Applications

. Cell Phones, Smart Phones, PDAs

. Tablets, Portable Media Players

. Gaming Devices, Digital Cameras

Ordering Information

Operating

Temperature Range

Top

Mark

Part Number

Package

FSA9591UCX ⁽¹⁾

-40 to +85°C

NT

30-Lead WLCSP (2.38 mm x 1.98 mm x 0.625 mm, 0.4 mm Pitch)

Note:

1. Includes backside lamination.

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

Typical Application

USB Data

USB CHARGING

FACTORYTEST

OVT

PROTECTION

FSA9591

FSA9280A

Figure 1. Mobile Phone Example

Block Diagram

V_LDO1

1µF

Function 1

V_LDO2

2 LDOs

1µF

Function 2

Voltage

V_REF

Reference

1.0nF

V_BAT

Li+ Charger

4.7µF

DETBAT_N

V_DDIO

Power

Management

1µF

Micro

USB

CHG_CAP

FSA9591

1µF

0.1µF

VICHG

V_{BUS_IN}

TxD_HOST

RxD_HOST

DM_CON

DP_CON

ID_CON

HS/FS USB

or UART

2:1

MUX

DM_HOST

DP_HOST

HS/FS USB

or UART

GND

V_DDIO

BC1.1 Charger

Detection

4.7KW

INT_N

I2C_SCL

I2C_SDA

Interrupt

I²C

GPO1

GPO2

GPOs

V_DDIO

Control,

Registers,

and

Float

Detect

Baseband

Processor

10KW

I²C

JIG

COLMx

ROWx

ADC ID

Detect

Slave

V2_3

ON_BT_UP

ON_KEY_N

RESET_N

Figure 2. Block Diagram

FSA9591 • Rev. 1.0.2

www.fairchildsemi.com

2

Pin Configuration

ID_

CON

DP_

CON

DM_

CON

CHG_

CAP

V_BUS

A

B

C

_IN

DM_

HOST

TxD_

HOST

ON_

BT_UP

ROWx

V_BAT

VBAT

DP_

HOST

RxD_

HOST

Baseband

V2_3

V_ICHG

GPO1

GND

COLMx

V_BAT

VBAT

Connector

ON_

KEY

_N

DET

INT_N

JIG

D

E

F

BAT_N

ForChip Use

ToBattery

DET

BAT_N

I2C_

SDA

V_DDIO

GPO2

V_LDO1

VLDO1

ToKey Matrix

General Purpose

RES

ET_N

I2C_

SCL

V_REF

V_LDO2

VLDO2

1

2

3

4

5

Top-Through View

1.98mm

Figure 3. Pin Assignment (Top Through View)

Pin Descriptions

Default

State

Name

Ball

Type

Description

USB Interface

D+ signal switch path; dedicated USB port to be connected to the USB transceiver

on the phone

DP_HOST

C1

B1

Signal Path

Open

D- signal switch path; dedicated USB port to be connected to the USB transceiver

on the phone

DM_HOST

UART Interface

Transmitter (Tx) switch path from UART on the phone to the D- pin of the USB

connector

TxD_HOST

B2

Signal Path

Open

Receiver (Rx) switch path from UART on the phone to the D+ pin of the USB

connector

RxD_HOST C2

Connector Interface

GND

F3

A1

Ground

N/A

Ground

Pull-Up

Current

ID_CON

Signal Path

Connected to the USB connector ID pin and used for detecting accessories

Connected to the USB connector D+ pin; depending on the signaling mode, this pin

can be switched to DP_HOST or RxD_HOST pins

DP_CON

A2

Signal Path

Open

Connected to the USB connector D- pin; depending on the signaling mode, this pin

can switched to DM_HOST or TxD_HOST pins

DM_CON

V_{BUS_IN}

A3

A4

Signal Path

Power Path

Open

N/A

Input voltage supply pin to be connected to the VBUS pin of the USB connector

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

3

Default

State

Name

Ball

Type

Description

Power Interface

V_DDIO

V_BAT

E1

Power

Power Path

Power

N/A

Hi-Z

Factory and I²C interface I/O supply pin

B5,C5

E5

Battery charger output and chip supply pin to be connected to mobile phone battery

Programmable first LDO regulator output

V_LDO1

V_LDO2

F5

Power

Programmable second LDO regulator output

0.6 V voltage reference for internal use. Can output a maximum of 1 mA external

load. Needs to be enabled for LDO operation.

V_REF

F4

Power

Hi-Z

Bypass capacitor for charger that forms a low-voltage power supply for internal

circuitry (0.1 µF typical value)

CHG_CAP

V_ICHG

A5

D3

Power

Hi-Z

Analog signal proportional to the charging current flowing to battery from V_{BUS_IN}

Other Interface

Open-Drain

Output (V_DDIO

Output control signal driven by the FSA9591 and used by the processor for factory

test modes (active LOW open drain output)

JIG

D2

Hi-Z

N/A

)

Input

(Comparator)

ON_KEY_N D4

Input that indicates whether the phone ON key has been pressed (active LOW)

Switch connected to the V2_3 pin to boot up the processor during factory mode or

when the ON_KEY_N signal is asserted

VBUS

Valid VBUS

ON_KEY_N

X

JIG

ON_BT_UP =

V2_3

X

ON_BT_UP B3

Switched Path

Hi-Z

LOW

X

V2_3

HIGH

LOW

Hi-Z

V2_3

Hi-Z

Pin switched to ON_BT_UP for realizing ON_BT_UP functionality (see ON_BT_UP

description)

V2_3

C3

C4

Switched Path

Hi-Z

Used to translate the ON key signal from a high-voltage signal into a low-voltage

closed switch in the processor key matrix circuitry. Switches to ROWx.

V_BAT

LOW

ON_KEY_N

X

COLMx/ROWx

OPEN

COLMx

VALID

HIGH

LOW

OPEN

SHORT

Used to translate ON key signal from a high-voltage signal into a low-voltage closed

switch in the processor key matrix circuitry. Switches to COLMx.

V_BAT

LOW

ON_KEY_N

X

COLMx/ROWx

OPEN

ROWx

B4

Switched Path

Open-Drain

Hi-Z

VALID

HIGH

LOW

OPEN

SHORT

Output to synchronize the processor with detected accessories. The threshold is

1.4 V rising edge and 1.2 V falling edge and the pulse lasts for 250 ms.

RESET_N

GPO1

F1

E3

E4

N/A

Output (V_DDIO

)

General purpose; first output programmed from register bit GPO [GPO1]. This can

be push/pull or open drain based on the register bit GPO [GPO1_OD].

Output (V_DDIO

)

General purpose; second output programmed from register bit GPO [GPO2]. This

can be push/pull or open drain based on the register bit GPO [GPO2_OD].

GPO2

Output (V_DDIO

Input

)

Detect battery input to determine the battery presence in the phone;

DETBAT_N=HIGH when battery is not present.

DETBAT_N=LOW when battery is present or when charger is enabled, regardless

of battery presence. Internally pulled up.

DETBAT_N D5

N/A

(Comparator)

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

4

Default

State

Name

Ball

Type

Description

I²C Interface

I2C_SCL

F2

E2

Input (V_DDIO

)

N/A

I²C serial clock signal to be connected to the phone-based I²C master

I²C serial data signal to be connected to the phone-based I²C master

Open-Drain I/O

(V_DDIO

I2C_SDA

Hi-Z

)

Interrupt active LOW output used to prompt the phone baseband processor to read

the I²C register bits or indicate a change in ID_CON pin status or accessories‘

attach status

CMOS Output

(V_DDIO

INT_N

D1

Low

)

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

5

1. Functionality

The FSA9591 is USB port accessory detector and switch with

integrated 28 V over-voltage tolerance. Fully controlled using I²C,

FSA9591 enables high-speed USB 2.0 Standard Downstream

Port (SDP), USB Charging Downstream Port (CDP) battery

charger, USB Dedicated Charging Port (DCP) charger data

cables to use a common connector micro or mini USB 2.0 port.

Factory-mode cables can be detected and switched to use either

the UART or USB data path. The FSA9591 can be programmed

for manual switching or automatic switching of data paths.

1.1.

Functional Overview

The FSA9591 is designed for minimal software requirements for

proper operation. The flow diagram in Figure 4 walks through the

fundamental steps of operation and contains references to more

detailed information.

Datasheet

Description

Section

Flow Diagram

State

Power-Up & Reset

I²C

Applies power to the device and resets state of

the device

Section 2

Power-up &

Reset

Section 3

Section 4

Communication with device through I²C

Configures the device using I²C and the internal

registers (which can be bypassed during power-

up)

I²C

Configuration

Detection

Manages accessory detection, including

attachment and detachment

Section 5

Section 1

Configuration

Processor

Communication

How the detection of the accessory is indicated to

the processor

Accessory

Plug-in

Detection

Processor

Communication

Switch Configuration

Section 7

Configuration of switches based on detection

Switch

Configuration

Active Signals

Accessory

Detached

Active Signal

Section 11

Signal performance of selected configuration

Figure 4. Basic Operation Flow

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

6

2. Power-Up & Reset

The FSA9591 does not need special power sequencing for correct

operation. The main power for accessory detection is provided by

V_BATonly. V_DDIOis only used for I²C interface and interrupt

Table 1 summarizes the enabled features of each power state.

The valid voltages levels for each power supply can be found in

Section 12.2

processing. The linear charger power is provided by V_{BUS_IN}

.

Table 1. Power States Summary

Enabled Functionality

Valid Valid Valid

V_{BUS_IN}V_BATV_DDIO

Processor

Charging

LDO

Power State

(2)

Detection/

Switching

Communication

(I²C & Interrupts)

N

Y

N

Y

N

Y⁽³⁾

N

Power Down

Not Typical

NO

Illegal State

YES

N

Detection/Switching Active

Charging Only

NO

YES

NO

YES

NO

N

Y

YES

Y

N

Y⁽³⁾

NO

YES

Y

Not Typical

NO

N

Powered On State

NO

YES

Y

YES

Notes:

2. V_DDIOis expected to be the same supply used by the baseband I/Os.

3. Typically V_DDIOis only present when V_BATis valid.

4. X=Don‘t care.

2.1.

Reset

2.1.1. Hardware Reset

Power-On Reset (POR) is caused by the initial rising edge of

V_BATor V_{BUS_IN.}

When the device is reset, all the registers are initialized to the

default values shown in Section 12.14 and all switch paths are

open. After reset or power up, FSA9591 enters Standby Mode

and is ready to detect accessories sensed on the V_{BUS_IN}or

ID_CON pins.

2.1.2. Software Reset

The device can be reset through software by writing to the Reset

bit in the Register (1BH).

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

7

3. I²C

The FSA9591 integrates a full fast-mode I²C slave controller

compliant with the I²C specification version 2.1. The FSA9591 I²C

interface runs up to 400 kHz.

The slave address is shown in Table 2. Status information and

configuration occurs via the I²C interface. Please see Section

12.12 for more information.

Table 2. I²C Slave Address

Name

Size (Bits)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Slave Address

8

0

1

0

1

0

1

Read / Write

8bits

S

Slave Address WR A Register Address K A Write Data A Write Data K+1 A Write Data K+2 A

Write Data K+N-1

A P

Note: Asingle-byte write is initiated bythe master with P immediatelyfollowing first data byte.

Figure 5. I²C Write Sequence

8bits

S

Slave Address WR A Register Address K A S Slave Address RD A Read Data K A Read Data K+1 A Read Data K+N-1 NA P

Single- or multi-byte read executed from current register location (single-byte read initiated by

Register address to read specified

master with NAimmediatelyfollowing first data byte).

Note: If no register specified, master reads from the current register. In this case, onlysequence in red bracket is needed.

Figure 6. I²C Read Sequence

Legend

S

A

NA

RD

P

From Master to Slave

From Slave to Master

Start Condition

NOT Acknowledge (SDA HIGH)

Write=0

Read=1

WR

Acknowledge (SDA LOW)

Stop Condition

4. Configuration

FSA9591 requires minimal configuration for proper detection,

charging and reporting. Follow these steps for full configuration:

2. Write Control register (02h) to clear INT Mask bit.

This enables interrupts to the baseband.

1. Write Control register (02h) to configure manual or automatic

switching modes.

The linear charger defaults to automatic charging at either 90mA

or 450mA based on the accessory that was detected.

a. If using manual switching modes, write Manual SW 1

register (13h) to configure switches.

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

8

5. Detection

The FSA9591 monitors both V_{BUS_IN}and ID_CON to detect

accessories. The ID_CON detection is a ―resistive detection‖ that

reads the resistance to GND on the ID_CON pin to determine the

accessory attached. Table 3 shows assignment of accessories

based on resistor values. FSA9591 can also detect accessories

with ID resistances outside the specified ranges; these are

detected in the same manner as the defined accessories.

FSA9591 interrupts the baseband processor and provides the

correct ADC value, as shown in Table 3.

Table 3. ID_CON Accessory Detection

(6)

ADC Code

Equivalent R_ID

Description

Max.

4

1

3

0

1

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Min.

Target

121 kΩ

150 kΩ

200 kΩ⁽⁵⁾

255 kΩ

301 kΩ

365 kΩ

442 kΩ⁽⁵⁾

523 kΩ

619 kΩ

1000 kΩ

117.4 kΩ

145.5 kΩ

176.4 kΩ

247.3 kΩ

291.9 kΩ

354.0 kΩ

428.7 kΩ

507.3 kΩ

600.4 kΩ

750.0 kΩ

3 MΩ

124.6 kΩ

154.5 kΩ

206.0 kΩ

262.7 kΩ

310.1 kΩ

375.9 kΩ

455.3 kΩ

538.7 kΩ

637.6 kΩ

1030.0 kΩ

Unknown Accessory

Travel Adapter (TA) or Car Kit Type 1 Charger

Factory Mode Boot OFF-USB

Factory Mode Boot ON-USB

Unknown Accessory

Factory Mode Boot OFF-UART

Factory Mode Boot ON-UART

Unknown Accessory

Not ‗h1F or any code above

Note:

None of the above ranges

Unknown Accessory

5. These accessories need V_BUSto be valid to be detected since they are charger accessories.

6. For resistances between the defined regions, the FSA9591 detects the ADC value above OR below the given resistance.

Factory modes are initiated with the attachment of special test

hardware, called a ―JIG box,‖ for factory testing. The FSA9591

automatically configures switch paths to any of the factory-mode

accessories when the appropriate resistor is sensed on the

The different factory mode accessories with the associated

resistor values (1% standard resistors) on the ID_CON pin and

The switch paths for factory modes are listed in Table 4. The

FSA9591 allows HS USB, FS USB, and UART signals to be

passed on both ports with equal performance. This allows greater

flexibility when designing with the FSA9591.

ID_CON pin.

A change of resistor on the ID_CON pin

dynamically switches between factory modes and auto-

configures the appropriate switch paths without detaching and

attaching the cable.

Table 4. ID_CON Factory Cable Detection

Configuration Type

DP_CON

DM_CON

ID_CON

Boot_On

Boot_Off

Boot_On

Boot_Off

DP_HOST1

DP_Host

DM_HOST1

DM_Host

600 kΩ

507 kΩ

292 kΩ

247 kΩ

619 kΩ

523 kΩ

301 kΩ

255 kΩ

637 kΩ

538 kΩ

310 kΩ

262 kΩ

Factory Mode Jig: UART

Factory Mode Jig: USB

DP_Host

DM_Host

The FSA9591 detection algorithms monitor both the V_BUSand ID

pins of the USB interface. Based on the detection results,

multiple registers are updated and the INTB pin is asserted to

indicate to the baseband processor that an accessory was

detected and to read the registers for the complete information.

The detection algorithm allows the application to control the

timing of the detection algorithm and the configuration of the

internal switches. The flow diagram in Figure 8 shows the

operation of the detection algorithm.

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

9

FSA9591 Standby

Mode

Accessory Plug-in

USB or

Factory

Modes

YES

FSA9591 Detects

Accessory Type

NO

FSA9591 auto-

configures switch

paths ⁽⁷⁾

FSA9591 WritesDevice

Type rregisters and

Attach Interrupt

FSA9591 set INT_N Pin

LOW (INT MASK bit

must have been

cleared by µP)

µP reads FSA9591

Interrupt Registers

NO

Detach

?

YES

FSA9591 writes Detach

Interrupt and clears

Device Type registers

FSA9591 sets INT_N Pin

HIGH

Figure 7. Factory Cable Detection

Note:

7. Factory modes require V_DDIO=HIGH before configuring the switches. Refer to the factory mode flow diagram in Figure 8 for details.

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

10

FSA9591 Standby

Mode

Factory JIG Box Plug-in

FSA9591 detects attach, writes Device

Type registers, Attach interrupt and

asserts JIG

NO

V_DDIO

HIGH

YES

FSA9591 auto-configures

switch paths and asserts

INT_N pin

µP reads FSA9591

Interruptregisters

FSA9591 enters

Standby Mode

FSA9591 writes Detach

Interrupt, clears Device

Type registers and de-

asserts INT_N (Exits

Factory Mode Flow)

YES

ID Float

> 70ms

NO

ID

resistance

change?

YES

RID=

Factory

Mode?

NO

YES

Figure 8. Factory Cable Detection Flow Chart

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

11

5.1.

USB Port Detection

The types of USB 2.0 ports the FSA9591 can detect are summarized in Table 5.

Table 5. ID_CON and VBUS Detection Table for USB Devices

ID_CON Resistance to GND

V_{BUS_IN}

DP_CON

DM_CON

Accessory Detected⁽⁸⁾

Min.

Typ.

Max.

TA (Travel Adapter) Charger (180 kΩ) and

Car Kit Charger Type 1 only (200 kΩ)⁽⁹⁾

5V

Not Checked

174.6 kΩ

200 kΩ

206 kΩ

Shorted to

DM_CON

Shorted to

DP_CON

USB Dedicated Charging Port, Travel Adapter

or Dedicated Charger (DCP)⁽⁹⁾

3 MΩ

Open

5V

DP_HOST

DM_HOST

3 MΩ

Open

USB Charging Downstream Port (CDP)⁽⁹⁾

USB Standard Downstream Port (SDP)⁽⁹⁾

Notes:

8. The accessory type is reported in the Device Type 1 (0Ah) register for each valid accessory detected.

9. The FSA9591 follows the battery charging 1.1 specification, which uses DP_CON and DM_CON to determine the USB accessory

attached. Refer to Battery Charging 1.1 specification for further details.

For SDP and CDP USB accessories, the following pin mapping is automatically configured:

.

DP_HOST=DP_CON

DM_HOST=DM_CON

For DCP charger, the DP_HOST and DM_HOST switches are open. For all USB accessories, V_{BUS_IN}has Over-Voltage Tolerance

(OVT) up to 28 V.

6. Processor Communication

8. GPOs

Typical communication steps between the processor and the

FSA9591 during accessory detection are:

The FSA9591 has two general-purpose outputs (GPOs) that

typically turn on the functionality powered by the LDOs. The

default state for the GPOs is push-pull outputs with GPO1_OD

and GPO2_OD set LOW. If open-drain outputs are required,

GPO1_OD and GPO2_OD should be set HIGH.

1. INTB is asserted LOW, indicating a change in accessory

detection.

2. Processor reads the Interrupt 1 (03h) register to determine if

an attach or detach event was detected.

9. LDOs

3. Processor reads the Status registers to determine the exact

accessory detected.

The two Low Drop Out (LDO) regulators, which are powered from

V_BAT, are programmable from 1.8 V to 3.6 V in increments of

100 mV. A 0.6 V reference on VREF must be enabled by writing

the register bit GPO[REF_EN] to turn it on. This reference needs

to turn on at least 20ms prior to the LDOs turning on to allow time

to stabilize the reference if 0.1 nF bypass capacitance is used.

a. Device Type 1 (09h): Indicates which USB, Car Kit CDP,

or DCP accessory was detected.

b. Device Type 2 (0Ah): Indicates which factory mode or

unknown accessory was detected.

10. ON_KEY Keypad Functionality

The functionality of ON_BT_UP is described in Table 6.

Table 6. ON_KEY_N and ON_BT_UP Truth Table

7. Switch Configuration

FSA9591 devices have two methods of configuring the internal

switches: it can auto-configure the switches or the switches can

be configured manually by the processor. Typical applications

use Auto-Configuration Mode and do not require interaction with

the baseband to configure the switches correctly.

VBUS

ON_KEY_N

JIG

ON_BT_UP

Valid VBUS

LOW

X

V2_3

Hi-Z

LOW

HIGH

7.1.

Manual Switching

LOW

Hi-Z

Manual switching is enabled by writing the following registers:

LOW

.

Manual Switch (13h): Configures the switches for DM_CON

and DP_CON in addition to manual control of the JIG output.

How to translate ON_KEY_N to a position in the row and column

matrix of the processor keypad is shown in Figure 9.

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

12

Normallow-voltage

keypad buttons

To high-voltage

ONkey button

ON_KEY_N

KEYIN0

KEYIN1

FSA9591

COLMx

ROWx

BBk4

BBk5

BBk1

BBk3

KEYIN2

KEYIN3

KEYIN4

BBk6

BBk9

BBk10

BBk15

BBk20

BBk7

BBk8

BBk14

BBk19

BBk11

BBk16

BBk12

BBk17

BBk13

BBk18

KEYIN5

KEYOUT0

KEYOUT1

KEYOUT2

KEYOUT3

KEYOUT4

Figure 9. On Key to COLMx and ROWx Mappings

V_OREG

This is the way the FSA9591 translates the ON_KEY_N pin,

where the COLMx and ROWx create a virtual button that would

have occupied the missing BBk2 switch in the matrix above.

Internal to the FSA9591, there is an analog switch that connects

COLMx to ROWx based on ON_KEY_N as outlined in Table 7.

With ON_KEY_N pulled HIGH to V_BAT, a valid V_BATmust be

present for the keypad functionality to work properly.

I_CHARGE

I_OCHARGE

V_BAT

I_TERM

V_SHORT

I_SHORT

Table 7. COLMx/ROWx Truth Table

V_BAT

LOW

ON_KEY_N

COLMx/ROWx

OPEN

X

VALID

HIGH

LOW

OPEN

2.5V

PRE-

VOLTAGE

CURRENT REGULATION

CHARGE

REGULATION

SHORT

Figure 10. Default Charging Profile

11. Linear Charger

11.1. Charging

11.1.1. Pre-Qualification Charging Stage

A typical battery has a protection circuit within the battery pack to

disconnect the terminals below 2.7 V external to the FSA9591. If

it gets below 2.7 V, the battery pack terminals are disconnected

externally with the load switch within the battery pack, causing

battery voltage V_BATto decay quickly to ground since all that is

holding V_BATup is the decoupling capacitors externally. Another

way that V_BATcan get so low is if V_BATis shorted to ground

accidentally. Both of these occurrences are very rare in a typical

system since a dead battery is typically above 3 V and only goes

below 3V over a long period of time via leakage.

Figure 10 shows the different stages of the Li+ linear charger

when a charger is connected to the USB pins and a battery is

present and discharged below 2.5 V. Generally, the

prequalification (called ―PRE-CHARGE‖ in Figure 10) stage is

when the battery voltage is below 2.5 V when an I_SHORTcurrent of

90 mA charges the battery to V_SHORTvoltage of 2.5 V. Then the

Fast Charge stage starts if a battery charger is detected and the

current is increased considerably to a programmable I_OCHARGE

level (―CURRENT REGULATION‖ in Figure 10). The battery

voltage climbs quickly based on the drop caused by the current

across the load elements of the battery. Then the voltage climbs

linearly until the constant voltage stage is reached at the

programmable voltage of V_OREG. The current is monitored during

this stage (―VOLTAGE REGULATION‖ in the figure) and, when it

reaches the end of current I_TERM, charging either halts or

progresses to the top off charging if enabled.

When VBUS_IN is first detected as being within its valid range,

two timers are started, a 30-minute timer for the dead battery

provision (if that is enabled) via the Charger Ctrl1[DBP_EN] bit

(enabled by default since the processor is usually not operating

at this low battery voltage range) and a programmable timer for

total charging elapsed time enabled (enabled by default as a 5-

hour timer via the Charger Ctrl1 [TC_EN] and Charger Ctrl1

[TC_Time] bits).

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

13

The linear charger is expected to always take its power from

VBUS_IN while monitoring V_BATto determine the optimal

charging profile for the shortest charging cycle.

Beyond the weak-battery threshold, the processor is expected to

be up and controlling the charging process. The constant current

is expected to be increased to match the battery charge capacity

and the timers for total elapsed charging time can be changed

accordingly. The constant voltage threshold is also expected to

be set based on battery type and battery temperature, which

should be monitored by the processor via separate controls.

Thermal regulation within the FSA9591 may have little correlation

to the battery temperature since the heat dissipation of the PCB

that the FSA9591 is soldered to may be completely different from

the heat dissipation within the battery pack.

If VBUS_IN is detected when V_BATis below 2.5 V, a charging

current of 90mA is used to trickle charge the battery. If it is not a

short circuit, V_BATshould recover very quickly above 2.5 V since it

is only charging decoupling capacitors. V_DDIOand V_BATare below

the operational voltage of the detection portion, so detection is

not performed, nor does FSA9591 communicate over the I²C

lines as the linear charger charges the battery above the pre-

qualification stage.

When the programmed constant voltage threshold (programmed

by Charger Ctrl5[CV_Voltage] bits) is approached, the fast

charging current loop is gradually changed to a constant voltage

loop where the current is allowed to decay. Charging continues

until the end of charge current (set by Charger Ctrl4 [EC_Current]

bits) is crossed.

If there is a short circuit and the charger Ctrl1 [DBP_EN] bit is

enabled (default case), the timer continues up to 30 minutes and

expires, shutting down the charger. This limits the short-circuit

current of 90mA to be drawn only for 30 minutes. The only way to

recover from this fault condition is to remove the short circuit. If

the short circuit is not removed, detaching and re-attaching the

charger restarts the dead battery provision timer for another 30

minutes before shutting off again.

If the top-off timer (set by Charger Ctrl1 [TopOff_EN] bit) is

disabled and Charger Ctrl1 [AutoStop] bit is set, all charging

stops and the charger monitors V_BAT. If V_BATfalls 150 mV below

the programmed constant voltage, the fast charge charging cycle

starts again. A debounce time of 60 ms prior to restarting this

cycle prevents glitches or temporary GSM current load of up to

2 A for <1 ms. If the top-off timer is enabled and the AutoStop bit

is set; for 30 minutes after the end of charge current threshold

has been crossed, the constant voltage charge cycle continues.

After that, all charging is stopped and V_BATis monitored again for

a drop of 150 mV. If the Charger Ctrl1 [AutoStop] bit is not set,

the constant voltage state is never left and the charger keeps

trickle charging the battery to keep the voltage at the

programmed Charger Ctrl5 [CV_Voltage] voltage.

11.1.2. Constant Current/Constant Voltage Charging Stage

In this stage, V_BATis above the pre-qualification voltage of 2.5 V,

but below the programmed Charger Ctrl5 [CV_Voltage] value.

The charger detection interrogates the DP_CON, DM_CON, and

ID_CON lines to determine if a Dedicated Charger Port (DCP),

Charging Downstream Port (CDP), car kit charger (200 kΩ on

ID_CON), or a Travel Adapter (T_A, 180 kΩ on ID_CON) has been

detected. If a charger is detected, the default charging current

stays at the fast charge current of 450 mA (default) specified in

Charger Ctrl3 [FC_Current] bits. Soft-start techniques are used to

gradually increase current to minimize undesirable transients. If a

charger is not detected and a USB Standard Downstream Port

(SDP) is detected, the fast charge current drops to 90 mA like the

pre-qualification current and continues to charge up the battery.

This is summarized in Table 8.

The FSA9591 maintains this constant voltage with ±0.5% at room

temperature to ensure optimal battery performance. The timer

measuring the total charging elapsed time continues until the end

of charge current threshold is crossed and does not include the

top-off timer. If the total time exceeds the time in the Charger

Ctrl2 [TC_Time] bits, charging is stopped and the processor (if

the voltage is high enough for the processor to function) can

interrogate the source of the problem, correct it, then disables

and re-enables the charger again to restart charging. If the

voltage is not high enough for the processor to function, the

problem with the battery needs to be solved and the USB cable

needs to be unplugged and plugged back in again.

Table 8. Default Charging Currents

Accessory

Detected

Fast Charge

Current

FC_Override Auto_FC

1

0

X

0

X

FC_Current

90 mA

CDP / DCP/

Car Kit Type 1

0

1

FC_Current

90mA

11.1.3. Timers

SDP / Unknown /

Factory

The FSA9591 contains multiple timers to ensure that the battery

is safely charged under all conditions. These timers include the

dead-battery provision timer of 30 minutes, the total-charge timer

of 5 to 7 hours, and the top-off timer of 30 minutes. Each timer

can be enabled or disabled through I²C register accesses. The

total-charge timer value can be programmed through I²C also.

Thermal issues are also considered (see Thermal Regulation

section below) since this is the stage when there is the maximum

voltage difference between V_{BUS_IN}and V_BAT. Similar to the pre-

qualification stage, communication with the baseband is not

possible, at least initially, when V_BATis between 2.5 V and the

weak-battery threshold (Charger Ctrl2 [WB_Threshold]) so the

FSA9591 must be able to charge the battery properly without

interaction with the baseband. The 30-minute dead-battery

provision timer continues during this stage. When this timer

expires and V_BATdoes not exceed the weak battery threshold, the

charger is disabled in compliance with the Battery Charging USB

specifications for Dead Battery Provision (DBP). If the processor

wakes up prior to the weak-battery threshold, it can change the

weak-battery threshold via the Charger Ctrl2 [WB_Threshold] bits

to a value consistent with actual wake up voltage and/or disable

the dead battery timer via the Charger Ctrl1 [DBP_EN] bit.

The timers do not reset when an OVP event occurs. If V_BATis

above the weak-battery threshold and the baseband is active, the

FSA9591 causes an interrupt when the OVP occurs and when

the OVP event is disabled. This allows the baseband to control

the timers based on the system needs. When OVP is detected,

charging stops until the OVP event has recovered.

If V_BATis below the weak-battery threshold and the dead-battery

timer is active, FSA9591 takes the most conservative approach

and keeps the DBP timer running when OVP is detected.

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

14

11.1.4. Thermal Regulation

The FSA9591 contains a thermal regulation loop that is enabled

when the junction temperature exceeds 120°C. When this

temperature is exceeded, the FSA9591 starts to regulate the

current to lower the temperature. It does this by reducing the fast

charge current to 90 mA (it is most likely to be in the fast charge

cycle since that is when there‘s maximum power consumption by

the linear charger), waits 1 ms, increases the current to 200 mA,

waits 1ms, continues along the fast charge currents specified in

the Charger Ctrl3 [FC_Current] where the wait between fast

charge current steps is 1ms. This algorithm allows for the fastest

recovery from a thermal regulation event while still averaging a

current that keeps the temperature below 120°C.

V_{I_CHG}=Charging Current • 1.5

The FSA9591 also terminates charging completely if the junction

temperature exceeds 140°C. In both cases, the FSA9591

indicates which temperature event occurred via the Interrupt 1

[TREG_EN] and Interrupt 1 [TSD_EN] bits and indicates the

removal of these conditions via the Interrupt2 [TREG_DIS] and

Interrupt2 [TSD_DIS] bits. Temperature is continuously

monitored whenever the charger is enabled.

Figure 11. VI_CHG Characteristic

11.3. DETBAT_N

For a typical battery pack, there is an extra terminal with a

thermistor NTC resistor between this terminal and ground, which

is expected to be much less than 100 kΩ. This terminal is tied to

the DETBAT_N pin for a system to disable the charger whenever

a battery is not present. DETBAT_N internally has a current

source that detects the absence of any path to ground that is

>100 kΩ on the DETBAT_N pin. Once a HIGH is detected on

DETBAT_N, the charger is immediately disabled.

11.1.5. OVP, OCP, VBUS_IN Regulation

The FSA9591 contains programmable over-voltage protection

(OVP) on VBUS_IN, ranging from 6.5 V to 8.0 V, as specified in

the Charger Ctrl2 [OVP_Threshold] bits with the default setting of

7 V. If OVP is detected, the FSA9591 terminates charging

functionality if charging is active when OVP is detected. The

FSA9591 interrupts the processor when the OVP event via the

Interrupt 1[OVP_EN] bit is detected and when the OVP event is

removed via the Interrupt 1[OVP_DIS] bit. The FSA9591

VBUS_IN can tolerate voltages up to 28 V to handle the worst-

case automotive scenarios for USB VBUS voltage.

Some systems, for factory operation or other uses, may leave the

charger enabled regardless of whether the battery pack is

present or not. In these systems, it is expected that DETBAT_N

is tied LOW — always with a resistance to ground of 10 kΩ.

11.4. RESET_N

V_{BUS_IN}is typically 5 V ±5-10%, depending on the charging

current. If the FSA9591 linear charger is programmed to a higher

current than the charger can support, a V_{BUS_IN}control loop

actively regulates the charging current to maintain at least 4.3 V

(typical) on V_{BUS_IN}. The FSA9591 attempts to lower the charger

current to allow V_{BUS_IN}to recover to at least 4.3 V. In cases

where the charger V_{BUS_IN}is not limited by the charger current,

the FSA9591 attempts to lower the current until it reaches the

minimum current level and then disables the charger. This

V_{BUS_IN}regulation loop is enabled by default and controlled by the

Vbus_Reg_Dis bit in the Charger_Ctrl1 register.

RESET_N output is used as a system-level Power-On Reset

(POR) triggered when V_DDIOis above 1.4 V. This RESET_N

open-drain output is pulled-down upon FSA9591 power up and

released to HIGH after 250 ms (typically from when V_DDIO

crosses 1.4 V on its rising edge). RESET_N requires a valid V_BAT

for RESET_N to be actively pulled LOW after power up. This is a

tight threshold comparator of V_DDIOwith a hysteresis of 200 mV to

accommodate a slowly rising signal. When V_DDIOfalls below

1.2 V, RESET_N is pulled LOW again. This timing is shown in

Figure 12. RESET_N is not reset on a software reset and is not

intended to be a system-level reset, but a POR on VDDIO. The

250 ms timer is reset if V_DDIOtriggers the falling-edge reset.

If the V_{BUS_IN}regulation loop is disabled, the charging cycle is

stopped when V_{BUS_IN}falls below the V_{BUS_IN}valid falling

threshold of 3.5 V. Charging remains stopped until the V_{BUS_IN}

voltage rises above the rising V_{BUS_IN}valid threshold of 3.7 V and

stays above this threshold.

VBAT

1.4V

1.2V

VDDIO

11.2. VICHG

The VICHG is utilized by the host system to identify the amount

of current flowing through the charger FET. VICHG is enabled by

writing the VICHG_EN bit in the register. When disabled, VICHG

has an internal pull-down of 15 kΩ. V_ICHGshould not exceed

2.0 V when enabled.

RESET_N

t_{RST_N}

250ms(Typ)

Software Reset

Figure 12. RESET_N Timing

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

15

12. Product Specifications

12.1. Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the

recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses

above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Min.

Max.

Unit

V_BAT

V_{BUS_IN}

V_DDIO

Supply Voltage from Battery

-0.5

-1.0

-0.3

-50

6.0

28.0

V

Supply Voltage from USB Connector

Supply Voltage from Baseband

6.0

USB

6.0

V_SW

Switch I/O Voltage

V

UART

6.0

I2C_SDA, I2C_SCL, INT_N, GPO1, GPO2, RESET_N

JIG, DETBAT_N, ON_KEY_N

V_DDIO+ 0.3

V_BAT+ 0.3

V

V_IO

I_IK

I/O Voltage

Input Clamp Diode Current

mA

USB at T_A=85°C

UART at T_A=85°C

25

Switch I/O Current

(Continuous)

I_SW

mA

12

I_SWPEAK

T_STG

T_J

Peak Switch Current (Pulsed at 1ms Duration, <10% Duty Cycle)

Storage Temperature Range

150

mA

C

-65

+150

+260

Maximum Junction Temperature

T_L

Lead Temperature (Soldering, 10 Seconds)

USB Connector Pins

Air Gap

Contact

15.0

8.0

IEC 61000-4-2 System

(DP_CON, DM_CON, V_{BUS_IN}

ID_CON) to GND

,

ESD

kV

V

USB Pins

4.0

2.0

1.5

24

Human Body Model, JEDEC JESD22-A114

Charged Device Model, JEDEC JESD22-C101

IEC 61000-4-5 Surge Test⁽¹⁰⁾

All Others

All Pins

V_{BUS_IN}

Surge

DP_CON/DM_CON

10

Note:

10. Modified voltage requirements: voltage impulse into an open-circuit with a 1.2 µs ramp-up rate and a 50 µs ramp-down rate.

12.2. Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions

are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or

designing to Absolute Maximum Ratings.

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_BAT

Battery Supply Voltage

2.7

4.0

4.35

200

1.6

0

4.4

6.0

V

V_{BUSIN_DET}V_{BUS_IN}Voltage for Valid Detection

V_{BUSIN_CHG}V_{BUS_IN}Voltage for Valid Charging

V_BUS-V_BATV_{BUS_IN}– V_BATVoltage for Valid Charging

5.0

5.00

6.00

V

mV

V

V_DDIO

I/O Supply Voltage

1.8

3.6

USB Path Active

UART Path Active

V_SW

Switch I/O Voltage

V

0

3.6

ID_CAP

T_A

Capacitive Load on ID_CON Pin for Reliable Accessory Detection

Operating Temperature

1.0

nF

ºC

-40

+85

+125

T_J

Junction Temperature

ºC

Θ_JA

Thermal Resistance Junction-to-Ambient

60

ºC/W

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

16

12.3. Switch Path DC Electrical Characteristics

Unless otherwise specified, recommended T_Aand T_Jtemperature ranges (T_A=-40 to +85°C, T_J=-40 to +125°C). All typical values are at

T_A=25°C unless otherwise specified.

12.3.1. IO Specifications

Symbol

Parameter

Voltage Conditions

V_DDIO(V)

Min.

Typ.

Max. Unit

INT_N (Push-Pull)

V_OH

V_OL

Output High Voltage

Output Low Voltage

1.6 to 3.6

V_DDIO(V)

1.6 to 3.6

V_BAT(V)

I_OH=-3 mA

I_OL=3 mA

0.8•V_DDIO

V

0.2•V_DDIO

V

JIG, RESET_N (Open-Drain)

V_OLOutput Low Voltage

RESET_N Generation

I_OL=3 mA

V

V_RSTN

t_RSTN

V_DDIOThreshold for Generating RESET_N Output

3.0 to 4.4

0.2•V_BAT

V

RESET_N Active Timeout Period;

3.0 to 4.4

RST_TO=00

200

250

300

ms

from V_DDIO≥1.4V to RESET_N=HIGH⁽¹¹⁾

General-Purpose Outputs (GPO1 and GPO2)

V_DDIO(V)

1.6 to 3.6

V_BAT(V)

V_OH

V_OL

Output High Voltage, GPO [GPOx_OD]=0

Output Low Voltage, GPO [GPOx_OD]=X

I_OH=-3 mA

I_OL=3 mA

0.8•V_DDIO

V

0.2•V_DDIO

Comparator Input (ON_KEY_N)

V_IH

V_IL

High-Level Input Voltage

Low-Level Input Voltage

3.0 to 4.4

V_DDIO(V)

1.6 to 3.6

1.1

V

0.4

I²C Interface Pins – Fast Mode (I2C_SDA,I2C_SCL)

V_IL

V_IH

Low-Level Input Voltage

High-Level Input Voltage

0.3•V_DDIO

V

0.7•V_DDIO

0.05•V_DDIO

0.1•V_DDIO

V_DDIO>2 V

V_DDIO<2 V

V_HYS

Hysteresis of Schmitt Trigger Inputs

1.6 to 3.6

3.0 to 4.4

Input Voltage

0.26 V to

2.34 V

I_I2C

Input Current of I2C_SDA and I2C_SCL Pins

-10

0

10

µA

V_DDIO>2 V

V_DDIO<2 V

0.4

V

Low-Level Output Voltage at 3 mA Sink Current

(Open-Drain)

V_OL1

0.2V_DDIO

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

17

12.4. Switches

Symbol

T_A=-40 to +85°C,

T_J=-40 to +125°C

Parameter

V_BAT(V)

Conditions

Unit

Min.

Typ.

Max.

I_OFF

I_NO(OFF)Off Leakage Current

I_IDSHRT

Short Circuit Current⁽¹¹⁾

Power-Off Leakage Current

0

All Data Ports, V_SW=1 V to 4.4 V

I/O pins=0.3 V, 4.1 V, or Floating

10

µA

4.4

-0.100

0

0.006

20

0.100

3.0 to 4.4 Current Limit if ID_CON=0 V

USB Switch ON Path

USB Analog Signal Range

3.0 to 4.4

3.6

V

HS-USB V_D+/D-=0 V, 0.4 V,

I_ON=8 mA,

8.0

16.0

19.0

R_ONUSBUSB Switch On Resistance⁽¹²⁾

3.0 to 4.4

Ω

FS-USB V_SW=0 V, 3.6 V, I_ON=24 mA

11.5

UART Switch ON Paths

V_AR

Analog Signal Range

3.0 to 4.4

0

3.6

V

HS-USB V_D+/D-=0 V, 0.4 V, I_ON=8 mA

3.0 to 4.4

8.0

16.0

19.0

R_ONUARTUART Switch On Resistance⁽¹²⁾

Ω

FS-USB V_SW=0 V, 3.6 V, I_ON=24 mA

11.5

ON_BT_UP to V2_3 Switch and COLMx to ROWx Switch Characteristics

R_ONMISCSwitch On Resistance⁽¹²⁾

3.0 to 4.4 V_SW=0V to 4.4 V, I_ON=1 mA

36

Ω

Notes:

11. Limits based on electrical characterization data.

12. On resistance is the voltage drop between the two terminals at the indicated current through the switch.

12.5. LDOs

T_A=-40 to +85°C,

T_J=-40 to +125°C

Symbol

Parameter

V_BAT(V)

Conditions

Unit

Min.

Typ.

Max.

LDO Output Voltage

Programmable Range

V_LDO

3.0 to 4.4 I_LDO=300 mA

1.8

3.6

V

See LDOx_Ctrl [LDOx_Voltage] for

Exact Values

V_STEP

LDO Voltage Steps

3.0 to 4.4

100

250

mV

V_DROPDropout Voltage

3.0 to 4.4 I_LDO=300 mA

3.0 to 4.4

mV

mA

I_LDOMINMinimum Output Current

I_LDOMAXMaximum Output Current

0

3.0 to 4.4

300

Over Range of LDO Output Voltage

at T_A=25°C

d_VLDOROutput Voltage Accuracy

3.0 to 4.4

-2.0

-3.0

2.0

3.0

%

Output Voltage Accuracy Over

d_VLDOF

3.0 to 4.4 Over Range of LDO Output Voltage

Full Range

See

Conditions I_LDO=1 mA

V_BAT=V_LDO1(NOM(+0.5 V to 3.6 V,

d_LINE

Line Regulation⁽¹³⁾

Load Regulation⁽¹³⁾

0.15

12

3.00

70

%/V

µV/mA

mA

d_LOAD

3.8

I_LDO=1 mA to 300 mA

Short-Circuit Current Limit or Startup

Peak Current

I_{LDO_SC}Maximum Current Limit

3.0 to 4.4

620

900

PSRR Power Supply Rejection Ratio⁽¹³⁾

3.0 to 4.4 f=1 kHz

50

dB

e_N

Output Noise Voltage⁽¹³⁾

3.0 to 4.4 f=10 Hz to 100 kHz

100

µV_RMS

From LDOx_EN I²C Command to

Start Ramp, GPO[REF_EN]=1

t_ON

Turn-On Time

3.0 to 4.4

100

µs

Continued on the following page…

www.fairchildsemi.com

FSA9591 • Rev. 1.0.2

18

T_A=-40 to +85°C,

T_J=-40 to +125°C

Symbol

Parameter

V_BAT(V)

Conditions

Unit

Min.

Typ.

Max.

V_OST

Startup Overshoot⁽¹³⁾

3.0 to 4.4 I_LDO=1 mA

0

%

PkV_LINELine Transient Response⁽¹³⁾

3.0 to 4.4 600 mV, Rise=Fall=30 µs

±85

mV

I_LDO=1-300 mA-1 mA,

3.0 to 4.4

PkV_LOADLoad Transient Response⁽¹³⁾

±200

0.6

mV

V

Rise=Fall=1 µs

Reference Output Voltage for

V_REF

3.0 to 4.4 I_REF<1 µA

Internal Use

LDOx_ctrl [LDOx_DSCHG]=1

3.0 to 4.4

100

4.8

148

12

Ω

MΩ

°C

Discharge Programmable Turn-

On Resistor

R_DSCHG

LDOx_ctrl [LDOx_DSCHG]=0

3.4

Thermal Shutdown

T_SHTDN

3.0 to 4.4

Temperature⁽¹³⁾

Hysteresis

°C

Note:

13. Limits based on electrical characterization data.

12.6. Power Path

T_A=-40 to +85°C,

T_J=-40 to +125°C

Symbol

Parameter

Unit

Min.

Typ.

Max.

V_{BUS_REG}V_{BUS_IN}Threshold for Active V_{BUS_IN}Regulation

4.1

3.4

4.3

3.7

3.6

7.0

150

4.7

4.0

V

V_BUSVTRV_{BUS_IN}Valid Rising Threshold for Charging when V_{BUS_IN}Regulation is Disabled

V_BUSVTF

V_{BUS_IN}Valid Falling Threshold for Charging when V_{BUS_IN}Regulation is Disabled

V_{BUS_IN}Over-Voltage Protection (Programmable OVP = 7.0 V)

Hysteresis (Programmable OVP = 7.0 V)

V

6.5

7.6

V

V_BUSOVP

mV

V_BUS=5.5 V, Charger Ctrl1[ Charger_EN]=0,

V_{BUS_IN}Current

I_VBUS

1000

µA

LDO1_Ctrl[LDO1_EN]=0, LDO2_Ctrl[LDO2_EN]=0

12.7. Linear Charger

Symbol

T_A=-40 to +85°C,

T_J=-40 to +125°C

Parameter

Conditions

Unit

Min.

Typ.

Max.

T_A=25°C

T_A=-40°C to 85°C

-1.0

-2.0

4.00

-15

65

1.0

2.0

4.35

15

%

Constant Voltage Regulation Accuracy

V_OREG

Constant Voltage Regulation Range

Pre-Charge Accuracy

V

%

I_SHORT

Pre-Charge Current

98

mA

V

Pre-Charge Termination Voltage

Pre-Charge Hysteresis

V_BATRising

2.2

2.5

2.8

V_SHORT

t_OCHG

150

mV

Pre-qualified Current of 90 mA to

Fast Charge Current

Soft-Start Ramp Time

1.2

92

ms

Fast Charge Current at Low Current

Fast Charge Current Accuracy

Charger Ctrl3[Auto_FC]=0

80

108

10

mA

%

-10

I_OCHARGE

Charger Ctrl3[Auto_FC]=1

Charger Ctrl3[FC_Current] Bit‘s

Control Current

Fast Charge Current Range

200

950

mA

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FSA9591 • Rev. 1.0.2

19

T_A=-40 to +85°C,

T_J=-40 to +125°C

Symbol

Parameter

Conditions

Unit

Min.

Typ.

Max.

End of Charge Current Accuracy Based on

Fast Charge Current setting

I_TERM

EOC>120 mA

-1

1

%

V_TERM

t_TERM

t_ACC

Recharge Threshold, V_BAT– V_OREG

Recharge Debounce Time

Timer Tolerance

Charger Ctrl1[Recharge]=1

-150

60

mV

ms

%

-10

+10

45

t_TOPOFF

t_DBP

Top-Off Timer

Charger Ctrl2[TopOff_EN]=1

Charger Ctrl1[DBP_EN]=1

Charger Ctrl2[TC_Time]=00

TC_Time=01

30

min

hrs

Dead-Battery Provision Timer

30

5

6

7

t_ELAPSED

Total Elapsed Charging Time

TC_Time=10

TC_Time=11

Disabled

2.7

Charger Ctrl2[WB_Threshold]=001

Charger Ctrl2[WB_Threshold]=010

2.5

2.7

2.9

3.1

2.9

Charger Ctrl2[WB_Threshold]=011

(Default Setting)

2.9

3.1

3.3

V_WB

Weak-Battery Threshold

V

Charger Ctrl2[WB_Threshold]=100

Charger Ctrl2[WB_Threshold]=101

Charger Ctrl2[WB_Threshold]=110

3.1

3.3

3.5

3.3

3.5

3.7

145

5

3.5

3.7

3.9

Thermal Shutdown⁽¹⁴⁾

Hysteresis⁽¹⁴⁾

°C

T_SHUTDOWN

T_REG

Thermal Regulation⁽¹⁴⁾

120

15

°C

R_VICHG

VICHG Internal Resistance

kΩ

mV

I_BAT=50 mA

88

VBUS Current-to-Voltage Translation for

VICHG

I_VICHG

I_BAT=500 mA

875

Note:

14. Limits based on electrical characterization data.

12.8. Current Consumption

T_A=-40 to +85°C

Symbol

Parameter

V_BAT(V)

Conditions

Unit

Min.

Typ.

Max.

No Accessory Attached, V_BUS=0 V,

3.0 to 4.4 LDO1_EN=0, LDO2_EN=0,

REF_EN=0

Battery Supply Standby Mode

Current

I_BATS

15

25

µA

ID Not Floating, No VBUS, LDOs

Off, GPOs Off, All Switches Open,

Accessory Attached (Excluding

Factory Modes)

Battery Supply Standby Mode

Current with Accessory

Attached

I_BATSA

3.8

30

65

µA

ID Floating, No VBUS, One LDO On

(3.3 V), Other LDO Off, GPOs Off,

All Switches Open, No Accessory

Battery Supply Standby Mode

Current with One LDO On

I_BATSL

3.8

Attached

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FSA9591 • Rev. 1.0.2

20

12.9. Timing

Symbol

T_A=-40 to +85°C,

T_J=-40 to +125°C

Reference

Diagram

Parameter

Unit

Min. Typ. Max.

Time After INT Mask Cleared to ―0‖ until INT_N Goes LOW to Signal the

Interrupt after Interruptible Event while INT Mask Bit Set to 1

Figure 7,

Figure 8

t_SW

10

ms

Time from V_{BUS_IN}Valid to USB Switches Closed for USB Standard

Downstream Port

t_SDPDET

t_IDDET

Figure 13

130

5

ms

Time from ID Based Accessory Attached to INT_N Driven LOW

Time from V_{BUS_IN}Valid to USB Switches Closed for USB Charging

Downstream Port (CDP)

t_{CHRG_DET}

Figure 14

170

t_{VBUS_CHG}Time from V_{BUS_IN}Valid to Charger Active, Assuming Charger Enabled

150

20

ms

t_{CHG_EN}

t_DCD

Time from Charger_EN=1 to Charger Active with V_BUSValid

Time from V_{bus_valid}to DCD Detection Complete, Assuming Contact

Figure 14

20

t_{CHRG_FLOW}Time from DCD Complete to Charger Detection Complete

150

200

t_{ID_FLOW}

Time from DCD Complete to ID Detection Complete

Time from V_{BUS_IN}Valid to JIG LOW for Both Factory Mode Operation with

V_{BUS_IN}Present

t_JIGVBUS

Figure 15

Figure 16

200

ms

Time from ID Attach to JIG LOW for Factory Mode Operation without

V_{BUS_IN}Present

t_JIGNOVBUS

Charger Enabled

V_BUS>4.0V

USB Switches Closed

V_{BUS_IN}

V_BAT>2.7V

V_BATVoltage

XXXXFXLOXATXXXXXXXXXXXXXXXXXXXXXXXXXXXXXFXLOXAXT XXXXXXXXXXX

ID Resistance

t_{VBUS_CHG}

Charger Enabled

t_DCD

t_{CHRG_FLOW}

Open

USB Switch State

Closed

t_SDPDET

Figure 13. USB Standard Downstream Port Attach Timing

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FSA9591 • Rev. 1.0.2

21

V_BUS>4.0V

INTB asserted and

registers written

V_BUSVoltage

V_BAT>2.7V

V_BATVoltage

XXXXFXLOXATXXXXXXXXXXXXXXXXXXXXXXXXXXXXXFXLOXAXT XXXXXXXXXXX

ID Resistance

t_{VBUS_CHG}

Charger Enable

Switch State

Closed (CDP Only)

t_{CHRG_DET}

INT_N Pin

t_DCD

t_{CHRG_FLOW}

Figure 14. USB Charging Ports (DCP, CDP) Attach Timing

V_BUS>4.0V

V_{BUS_IN}

Charger Enable

ID Resistance

FLOAT

XXXXXXXX

JIG Pin

t_JIGVBUS

BB wake-up

time

V_DDIO

t_RSTN

RESET_N

Open

Switch State

Closed

Figure 15. Jig Box Attach Timing (V_{bus_IN}Valid)

ID Resistance

JIG Pin

FLOAT

XXXXXX

t_JIGNOVBUS

BB wake up

time

V_DDIO

t_RSTN

RESET_N

Open

Switch State

Closed

Figure 16. JIG Box Attach Timing without V_{BUS_IN}

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FSA9591 • Rev. 1.0.2

22

Accessory

Attached

INT_N Asserted

BB Reads INT_N

FLOAT

XXXXXX

ID Resistance

BB read

and

t_DCD

t_{ID_FLOW}

clear

INT_N Pin

Open

t_IDDET

Switch State

No switches

automatically closed

Figure 17. Unknown ID Timing

V_BUS>4.0V

V_BUSVoltage

FLOAT

ID Resistance

XXXXXXXX

V_BAT>2.7V

V_BATVoltage

t_VBUS

Charger Enabled

Open

Switch State

t_DCD

t_{ID_FLOW}

t_{ID_CHRG}

INT_N Pin

Figure 18. Car Kit Charger and TA Timing

12.10. AC Characteristics

Unless otherwise specified: recommended T_Aand T_Jtemperature ranges. All typical values are at T_A=25°C unless otherwise specified.

T_A=-40 to +85°C

Symbol

Parameter

Conditions

Unit

Min. Typ. Max.

f=1 MHz, R_T=50 Ω, C_L=0 pF

f=240 MHz, R_T=50 Ω, C_L=0 pF

f=1 MHz, R_T=50 Ω, C_L=0 pF

f=240 MHz, R_T=50 Ω, C_L=0 pF

-60

-30

-60

-30

Xtalk

Active Channel Crosstalk DP_CON to DM_CON⁽¹⁵⁾

dB

Off Isolation Rejection Ratio, DM_HOST to

DM_CON, DP_HOST to DP_CON⁽¹⁵⁾

O_IRR

Note:

15. Limits based on electrical characterization data.

12.11. Capacitance

T_A=-40 to +85°C

Symbol

Parameter

V_BAT(V)

Conditions

Unit

Min. Typ. Max.

3.8

V_BIAS=0.2 V, f=1 MHz

V_BIAS=0.2 V, f=240 MHz

f=1 MHz

8

5

pF

DP_CON, DM_CON ON Capacitance

(USB Mode) ⁽¹⁶⁾

C_ONUSB

C_I

Capacitance for Each I/O Pin⁽¹⁶⁾

Note:

16. Limits based on electrical characterization data.

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FSA9591 • Rev. 1.0.2

23

12.12. I²C AC Electrical Characteristics

Symbol

Fast Mode

Parameter

Unit

Min.

Max.

f_SCL

t_HD;STA

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

I2C_SCL Clock Frequency

0

0.6

400

kHz

µs

ns

µs

ns

Hold Time (Repeated) START Condition

LOW Period of I2C_SCL Clock

1.3

HIGH Period of I2C_SCL Clock

0.6

Set-up Time for Repeated START Condition

0.6

Data Hold Time

Data Set-up Time⁽¹⁷⁾

Rise Time of I2C_SDA and I2C_SCL Signals^(17,18)

Fall Time of I2C_SDA and I2C_SCL Signals^(17,18)

Set-up Time for STOP Condition

0

0.9

100

20+0.1C_b

0.6

300

t_f

t_SU;STO

t_BUF

BUS-Free Time between STOP and START Conditions

Pulse Width of Spikes that Must Be Suppressed by the Input Filter

1.3

t_SP

0

50

Notes:

17. A fast-mode I²C Bus^®device can be used in a Standard-Mode I²C Bus system, but the requirement t_SU;DAT≥ 250 ns must be met.

This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal. If a device does stretch the

LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line t_{r_max}+ t_SU;DAT=1000 + 250=1250 ns

(according to the Standard-Mode I²C bus specification) before the I2C_SCL line is released.

18. C_bequals the total capacitance of one bus line in pF. If mixed with high-speed devices, faster fall times are allowed by the I²C

specification.

Figure 19. Definition of Timing for Full-Speed Mode Devices on the I2C Bus®

Table 9. I²C Slave Address

Name

Size (Bits)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Slave Address

8

0

1

0

1

0

1

R/W

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FSA9591 • Rev. 1.0.2

24

12.13. USB Eye Compliance

Figure 20. HS Pass-Through Eye Compliance Testing

Input Signal

Figure 21. HS USB 2.0 Eye Compliance Test Results at

Output (T_A=85°C)

Figure 22. HS USB 2.0 Eye Compliance Test Results at

Output (T_A=25°C)

Figure 23. FS Pass-Through Eye Compliance Testing

Input Signal

Figure 24. FS USB 2.0 Eye Compliance Test Results at

Output (T_A=25°C)

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FSA9591 • Rev. 1.0.2

25

12.14. Programmability Tables

Register descriptions in BOLD reflect the default state of the register.

Table 10. Register Addresses

Register

Name

Reset

Value

Address

Type

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

01H

02H

Device ID

R

N/A

Revision Number

Vendor ID

Switch

Open

DCD TO

Disable

Control

R/W Xxxx_0101

R/C 0000_0000 TSD_EN

Auto Config

INT Mask

03H

04H

Interrupt 1

Interrupt 2

OVP_EN

TREG_EN

TC_TO

DBP_TO Bat_Charged

TRECOVER

Detach

Attach

R/C 000x_x0x0 TSD_DIS OVP_DIS TREG_DIS

R/W 0000_0000 TSD_EN OVP_EN TREG_EN

R/W 000x_x0x0 TSD_DIS OVP_DIS TREG_DIS

TSD_LDO

Interrupt

Mask 1

05H

06H

DBP_TO Bat_Charged

Detach

Attach

Interrupt

Mask 2

TRECOVER

ADC Value

TSD_LDO

07H

08H

ADC

R

Xxx1_1111

Status 1

1xxx_xx0x ON_KEY_N

V_{BUS_VALID}

Car Kit

Dedicated

Charger

(DCP)

Device

Type1

Jig UART Jig UART USB Charger

Off On (CDP)

Standard

USB (SDP)

09H

R

0000_0000 Type 1 and Jig USB Off Jig USB On

TA Charger

Device

Type2

Unknown

Accessory

0AH

0BH

0CH

Xxxx_xxx0

GPO

R/W Xxx0_0000

REF_EN GPO1_OD GPO2_OD

GPO1

GPO2

LDO1_

DSCHG

LDO1_Ctrl R/W 01xx_0100 LDO1_EN

LDO2_Ctrl R/W 01xx_0100 LDO2_EN

LDO1_Voltage

LDO2_Voltage

LDO2_

DSCHG

0DH

0EH

0FH

10H

11H

12H

13H

Charger

V_BUSReg

Dis

R/W X010_1111

Ctrl1

VICHG_EN AutoStop

TC_EN

TopOff_EN Charger_EN DBP_EN

WB_Threshold

FC_Current

Charger

R/W X001_0011

Ctrl2

TC_Time OVP_Threshold

Charger

FC_

Override

R/W 10xx_0101 Auto_FC

Ctrl3

Charger

R/W Xxxx_0000

Ctrl4

EC_Current

Charger

R/W Xxxx_1000

Ctrl5

CV_Voltage

Manual

R/W 0000_00x0

Switch

D- Switching

D+ Switching

JIG ON

14H

15H-26H

27H

Reset

R/W Xxxx_xx00

LC Reset

Reset

Reserved

Interrupt 3

Reserved

R/C

EOC

VBUS_CHG

Interrupt

Mask 3

28H

R/W

Notes:

19. Do not use registers that are blank.

20. Write 0 to undefined register bits.

21. Values read from undefined register bits are not defined and invalid.

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FSA9591 • Rev 1.0.2

26

Table 11. Device ID

Address: 01h

Type: Read Only

Bit #

Name

Size (Bits)

Description

7:3

2:0

Revision Number

Vendor ID

5

3

Rev 2.0=10100

000: Fairchild Semiconductor

Table 12. Switch Control

Address: 02h

Reset Value: xxxx_0101

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7:4

DoNotUse

4

N/A

1: Opens all switches

0: Does not open all switches

3

Switch Open

1

1: Automatic switching (also called auto-configuration)

0: Manual switching

2

1

Auto Config

1

1: Keeps checking DCD as long as V_{bus_valid}and id_float

DCD TO Disable

0: If DCD check times out (450ms typical), completes standard charger detection

1: Mask interrupt – does not interrupt baseband processor

0

INT Mask

1

0: Unmask interrupt – interrupts baseband processor on change of state in Interrupt

register

Table 13. Interrupt 1

Address: 03h

Reset Value: 0000_0000

Type: Read/Clear

Bit #

Name

Size (Bits)

Description

1: Thermal shutdown event has occurred and charger is disabled

0: No thermal shutdown event occurred

7

TSD_EN

1

1: OVP event

0: No OVP event

6

5

4

3

2

1

0

OVP_EN

TREG_EN

TC_TO

1

1: Thermal regulation causing current limiting to lower die temperature below threshold

0: No thermal regulation is occurring

1: Total charging timeout occurred

0: Total charging timeout has not occurred

1: Dead-battery provision timeout occurred

0: No dead-battery provision timeout occurred

DBP_TO

Bat_Charged

Detach

1: Battery fully charged with top-off timer expired if enabled

0: Battery not fully charged or linear charger is not active

1: Accessory detached

0: Accessory not detached

1: Accessory attached

0: Accessory not attached

Attach

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FSA9591 • Rev 1.0.2

27

Table 14. Interrupt 2

Address: 04h

Reset Value: 000x_x0x0

Type: Read/Clear

Bit #

Name

Size (Bits)

Description

1: Thermal Shutdown (TSD) event has recovered for linear charger

0: TSD event not recovered or never existed for linear charger

7

TSD_DIS

1

1: Over-Voltage Protection (OVP) event has recovered for linear charger

0: OVP event not recovered or never existed for linear charger

6

OVP _DIS

1

1: Thermal Regulation (TREG) event has recovered for linear charger

0: TREG event not recovered or never existed for linear charger

5

4:3

2

TREG_DIS

DoNotUse

TRECOVER

DoNotUse

TSD_LDO

1

2

1

N/A

1: Thermal Shutdown (TSD) event has recovered for LDO1 or LDO2

0: TSD event not recovered or never existed for LDO or LDO2

1

N/A

1: TSD event has occurred for either LDO and both LDOs are disabled

0: No TSD event has occurred for LDO1 or LDO2

0

Table 15. Interrupt Mask 1

Address: 05h

Reset Value: 0000_0000

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7

6

5

4

3

2

1

0

TSD_EN

OVP_EN

TREG_EN

TC_TO

1

1: Interrupt in Interrupt Register is masked and does not interrupt processor

0: Interrupt in Interrupt Register is not masked and, when active, interrupts processor

DBP_TO

Bat_Charged

Detach

Attach

Table 16. Interrupt Mask 2

Address: 06h

Reset Value: 000x_x0x0

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7

6

TSD_DIS

OVP_DIS

1

2

1

5

TREG_DIS

DoNotUse

TRECOVER

DoNotUse

TSD_LDO

1: Interrupt in Interrupt Register is masked and does not interrupt processor

4:3

2

0: Interrupt in Interrupt Register is not masked and when active interrupts processor

1

0

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FSA9591 • Rev 1.0.2

28

Table 17. ADC

Address: 07h

Reset Value: xxx1_1111

Type: Read Only

Bit #

Name

Size (Bits)

Description

7:5

DoNotUse

3

N/A

ADC value read from ID:

10101: Unknown Accessory

10110: Unknown Accessory

10111: Car Kit Type 1 Charger

11000: Factory Mode Boot OFF-USB

11001: Factory Mode Boot ON-USB

11010: Unknown Accessory

11011: Unknown Accessory

4:0

ADC Value

5

11100: Factory Mode Boot OFF-UART

11101: Factory Mode Boot ON-UART

11110: Unknown Accessory

11111: No Accessory or USB Accessory Detected

Table 18. Status 1

Address: 08h

Reset Value: 1xxx_xx0x

Type: Read

Bit #

Name

Size (Bits)

Description

1: ON_KEY_N is HIGH

0: ON_KEY_N is LOW

7

6:2

1

ON_KEY_N

DoNotUse

V_BUS_Valid

DoNotUse

1

5

1

N/A

1: Valid V_{BUS_IN}detected for accessory detection

0: No V_{BUS_IN}detected

0

N/A

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FSA9591 • Rev 1.0.2

29

Table 19. Device Type 1

Address: 09h

Reset Value: 0000_0000

Type: Read

Bit #

Name

Size (Bits)

Description

1: Car Kit Type 1 or Travel Adapter (TA) detected

0: Car Kit Type 1 or Travel Adapter (TA) not detected

7

Car kit Type 1 & TA Charger

1

1: Factory mode cable BOOT OFF – USB detected

0: Factory mode cable BOOT OFF – USB not detected

6

5

4

3

2

1

0

JIG_USB_OFF

JIG_USB_ON

1

1: Factory mode cable BOOT ON – USB detected

0: Factory mode cable BOOT ON - USB not detected

1: Factory mode cable BOOT OFF – UART detected

JIG_UART_OFF

0: Factory mode cable BOOT OFF - UART not detected

1: Factory mode cable BOOT ON – UART detected

JIG_UART_ON

0: Factory mode cable BOOT ON - UART not detected

1: USB Charging Downstream Port (CDP) charger detected

0: USB Charging Downstream Port (CDP) charger not detected

USB Charger (CDP)

Dedicated Charger (DCP)

Standard USB (SDP)

1: USB Dedicated Charging Port (DCP) charger detected

0: USB Dedicated Charging Port (DCP) charger not detected

1: USB Standard Downstream Port (SDP) detected

0: USB Standard Downstream Port (SDP) not detected

Table 20. Device Type 2

Address: 0Ah

Reset Value: xxxx_xxx0

Type: Read

Bit #

Name

Size (Bits)

Description

7:1

DoNotUse

6

N/A

1: Unknown accessory detected

0

Unknown Accessory

1

0: Unknown accessory not detected

Table 21. GPO

Address: 0Bh

Reset Value: xxx0_0000

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7:5

DoNotUse

3

N/A

1: Enable 0.6V reference voltage on V_REFpin

0: Disable 0.6V reference voltage on V_REFpin

4

3

2

1

0

REF_EN

1

1: GPO1 is an open-drain output

GPO1_OD

GPO2_OD

GPO1

0: GPO1 is a CMOS push-pull output

1: GPO2 is an open-drain output

0: GPO2 is a CMOS push-pull output

1: GPO1 output is a HIGH (Hi-Z if GPO1_OD is HIGH)

0: GPO1 output is a LOW

1: GPO2 output is a HIGH (Hi-Z if GPO2_OD is HIGH)

0: GPO2 output is a LOW

GPO2

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FSA9591 • Rev 1.0.2

30

Table 22. LDO1_Ctrl

Address: 0Ch

Reset Value: 01xx_0100

Type: Read/Write

Bit #

Name

Size (Bits)

Description

1: Enable LDO1 output with the voltage programmed by LDO1_Voltage

0: Disable LDO1 output

7

LDO1_EN

1

1: Enable discharge resistor to actively discharge LDO1 output⁽²²⁾

6

LDO1_DSCHG

Reserved

1

2

0: Disable discharge resistor

5:4

N/A

Voltage Programmed on the LDO1 Output⁽²³⁾

0000: Bypass

0001: 3.6

0010: 3.5

0011: 3.4

0100: 3.3

0101: 3.2

0110: 3.1

0111: 3.0

1000: 2.9

1001: 2.8

1010: 2.7

1011: 2.6

1100: 2.5

1101: 2.4

1110: 2.0

1111: 1.8

3:0

LDO1_Voltage

4

Notes:

22. The FSA9591 checks the status of LDO1_EN before enabling the discharge resistors. LDO1_EN is required to be LOW before the

discharge resistors are enabled.

23. It is possible to program the LDO output voltage above the V_BATlevel; in which case, the LDO is not regulated and the performance

of the LDO is compromised. This is not recommended.

Table 23. LDO2_Ctrl

Address: 0Dh

Reset Value: 01xx_0100

Type: Read/Write

Bit #

Name

Size (Bits)

Description

1: Enable LDO2 output with the voltage programmed by LDO2_Voltage

0: Disable LDO2 output

7

LDO2_EN

1

1: Enable discharge resistor to actively discharge LDO2 output⁽²⁴⁾

0: Disable discharge resistor

6

LDO2_DSCHG

Reserved

1

2

5:4

N/A

Voltage Programmed on the LDO1 Output⁽²⁵⁾

0000: Bypass

0001: 3.6

0010: 3.5

0011: 3.4

0100: 3.3

0101: 3.2

0110: 3.1

0111: 3.0

1000: 2.9

1001: 2.8

1010: 2.7

1011: 2.6

1100: 2.5

1101: 2.4

1110: 2.0

1111: 1.8

3:0

LDO1_Voltage

4

Notes:

24. The FSA9591 checks the status of LDO1_EN before enabling the discharge resistors. LDO1_EN is required to be LOW before the

discharge resistors are enabled.

25. It is possible to program the LDO output voltage above the V_BATlevel; in which case, the LDO is not regulated and the performance

of the LDO is compromised. This is not recommended.

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

31

Table 24. Charger Ctrl1

Address: 0Eh

Reset Value: x010_1111

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7

DoNotUse

1

N/A

1: V_{BUS_IN}regulation loop disabled

0: V_{BUS_IN}regulation loop enabled

6

5

4

3

V_BUS_Reg_Dis

VICHG_EN

AutoStop

1

1: VICHG reference output is enabled

0: VICHG reference output is not enabled

1: Stop charging after top-off timer expires

0: AutoStop must be enabled by writing this bit HIGH prior to charging occuring.

1: Enable timer for total charging elapsed time (default)

0: Disable timer for total charging elapsed time

TC_EN

1: Enable battery top-off timer for 30 minutes after end-of-charge termination current is

detected (default)

2

1

TopOff_EN⁽²⁶⁾

1

0: Disable top-off timer

1: Enable charger when V_{BUS_Valid}is detected (default)

Charger_EN

DBP_EN^(27,28)

1

0: Disable charger

1: Enable Dead-Battery Provision Mode (default until processor has a valid operating voltage)

0: Disable Dead-Battery Provision Mode (not USB compliant)

0

Notes:

26. The top-off timer is reset if an OVP event occurs. The top-off timer is not reset if I_BATincreases above EOC threshold after started.

27. Dead-battery timer starts when a charger is attached and the battery is below the weak-battery threshold. A dead-battery timeout

occurs when the timer expires and V_BATis still below the weak-battery threshold.

28. The dead battery timer is not reset if an OVP event occurs.

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

32

Table 25. Charger Ctrl2

Address: 0Fh

Reset Value: x000_1011

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7

DoNotUse

1

N/A

Total elapsed charging time threshold:

00: 5 hours (default setting)

01: 6 hours

10: 7 hours

11: No time limit

6:5

4:3

TC_Time^(29,30)

2

V_BUSOver-Voltage Protection threshold:

00: 6.5 V

01: 7.0 V (default setting)

10: 7.5 V

OVP_Threshold

11: 8.0 V

Weak battery threshold⁽³¹⁾

000: Reserved

001: 2.7 V

010: 2.9 V

2:0

WB_Threshold

3

011: 3.1 V (default setting)

100: 3.3 V

101: 3.5 V

110: 3.7 V

111: Reserved

Notes:

29. Changing the TC_TIME while the charger is active does not restart the timer and can cause an immediate timeout, depending on

the current state of the timer. For example, if the timer is programmed to 7 hours (0x10) and the timer is at 6 hourrs, programming

the timer to 5 hours (0x00) causes a timeout to occur.

30. The TC_TIME timer is not reset if an OVP event is detected or Vbus_in falls below the Vbus_valid threshold.

31. This threshold is checked at the completion of the dead-battery timer. If DBP_EN=1 and V_BATis below the threshold, then a

DBP_TO occurs.

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

33

Table 26. Charger Ctrl3

Address: 10h

Reset Value: 11xx_0101

Type: Read/Write

Bit #

Name

Size (Bits)

Description

1: Automatically detect charger and increase fast charge current to the default FC_Current in

Charger Ctrl2[FC_Current] if charger detected

7

Auto_FC

1

0: Use 90mA fast charge current to continue charging after the pre-qualification stage

1: Always use programmed FC_Current regardless of Auto_FC programming

0: Follow USB current requirements based on accessory detection and Auto_FC

6

FC_Override

DoNotUse

1

2

5:4

N/A

Fast charge current level if Charger_Ctrl3[Auto_FC]=1 and charger is attached or if

Charger_Ctrl3 [FC_Override]=1:

0000: 200 mA

0001: 250 mA

0010: 300 mA

0011: 350 mA

0100: 400 mA

0101: 450 mA (default)

0110: 500 mA

0111: 550 mA

1000: 600 mA

1001: 650 mA

1010: 700 mA

1011: 750 mA

1100: 800 mA

1101: 850 mA

1110: 900 mA

1111: 950 mA

3:0

FC_Current

4

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

34

Table 27. Charger Ctrl4

Address: 11h

Reset Value: xxxx_0000

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7:4

DoNotUse

4

N/A

End-of-charge current level⁽³³⁾. If the current is below this level in the constant voltage stage

of charging, the charger progresses to top off if enabled or is disabled.

0000: 20 mA (default setting)

0001: 30 mA

0010: 40 mA

0011: 50 mA

0100: 60 mA

0101: 70 mA

0110: 80 mA

3:0

EC_Current⁽³²⁾

4

0111: 90 mA

1000: 100 mA

1001: 110 mA

1010: 120 mA

1011: 130 mA

1100: 140 mA

1101: 150 mA

1110: 160 mA

1111: 170 mA

Notes:

32. Setting EC_Current below 120 mA is not recommended.

33. The end-of-charge current can be set above the fast charge current. This is not recommended.

Table 28. Charger Ctrl5

Address: 12h

Reset Value: xxxx_1000

Type: Read/Write

Bit #

Name

Size(Bits)

Description

7:4

DoNotUse

4

N/A

Constant voltage level. Charger maintains constant voltage when V_BATis this level:

0000: 4.00 V

0001: 4.04 V

0010: 4.08 V

0011: 4.10 V

0100: 4.12 V

0101: 4.14 V

0110: 4.16 V

0111: 4.18 V

1000: 4.20 V (default setting)

1001: 4.22 V

1010: 4.24 V

1011: 4.26 V

1100: 4.28 V

1101: 4.30 V

1110: 4.32 V

1111: 4.35 V

3:0

CV_Voltage

4

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

35

Table 29. Manual S/W⁽³⁴⁾

Address: 13h

Reset Value: 000000x0

Type: Read/Write

Bit #

Name

Size(Bits)

Description

000: Open switch

001: DM_CON connected to DM_HOST of USB port

011: DM_CON connected to TxD_HOST of UART port

DM_CON

Switching

7:5

3

All other values: DoNotUse

000: Open switch

001: DP_CON connected to DP_HOST of USB port

011: DP_CON connected to RxD_HOST of UART port

DP_CON

Switching

4:2

3

All other values: DoNotUse

1

0

DoNotUse

JIG_ON⁽³⁵⁾

1

N/A

1: JIG output=GND

0: JIG output=High Impedance

Notes:

34. When switching between manual switch configurations on a single attach, the accessory must pass through an ―000: Open Switch‖

state between configurations. Manual Modes must have an accessory attached prior to operation. The FSA9591 does not

configure per the Manual Modes register if an accessory has not been previously attached.

35. In normal operation, the JIG pin is used in the logic to drive the ON_BT_UP pin. When in Manual Mode, the JIG pin is not used in

the logic to drive the ON_BT_UP pin.

Table 30. Reset

Address: 14h

Reset Value: xxxx_xx00

Type: Write/Clear

Bit #

Name

Size (Bits)

Description

7:2

DoNotUse

6

N/A

1: Resets the linear charger (upon reset, this bit clears itself)

0: Does not reset

1

0

LC_Reset

Reset

1

1: Resets the detection logic (upon reset, this bit clears itself)

0: Does not reset

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

36

Table 31. Interrupt 3

Address: 27h

Reset Value: xxxx_xx00

Type: Read/Clear

Bit #

Name

Size (Bits)

Description

7:2

DoNotUse

6

N/A

1: EOC threshold has been reached

0: EOC threshold not reached (default)

1

EOC(1)

1

1: VBUS status changed. Read Status 1 register to determine the current status of VBUS

0: VBUS status has not changed (default)

0

VBUS_CHG(2)

Notes:

36. VBUS_CHG interrupt is triggered every time the V_BUS_Valid status bit in Status 1 changes state. Typical applications have this

interrupt masked prior to attach to prevent both VBUS_CHG and attach interrupt on attach. After an attach and the given accessory

is detected, the application can unmask this interrupt to allow detection of powered accessories where V_BUSis applied after attach.

37. EOC interrupt is triggered when the EOC threshold is reached. In cases where the top-off timer is disabled, there is both a

battery_charged and EOC interrupt that occur. If the top-off timer is enabled, the EOC interrupt is triggered when the top-off timer is

enabled and internally masked until the top-off timer expires. This prevents multiple EOC interrupts if I_BATis oscillating during the

top-off time.

Table 32. Interrupt Mask 3

Address: 28h

Reset Value: xxxx_xx11

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7:2

1

DoNotUse

EOC

6

1

N/A

1: Interrupt in Interrupt Register is masked and does not interrupt processor

0: Interrupt in Interrupt Register is not masked and, when active, interrupts processor

(default)

0

VBUS_CHG

1

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

37

13. Layout Guidelines

13.2. Layout for GSM / TDMA Buzz Reduction

13.1. PCB Layout Guidelines for High-Speed

USB Signal Integrity

1. Place FSA9591 as close to the USB controller as possible.

Shorter traces mean less loss, less chance of picking up

stray noise, and less radiated EMI.

There are two possible mechanisms for TDMA / GSM noise to

negatively impact performance. The first is the result of large

current draw by the phone transmitter during active signaling

when the transmitter is at full or almost-full power. With the

phone transmitter dumping large amounts of current in the phone

GND plane; it is possible for there to be temporary voltage

excursions in the GND plane if not properly designed. This noise

can be coupled back through the GND plane into the FSA9591

device and, although the FSA9591 has very good isolation; if the

GND noise amplitude is large enough, it can result in noise

coupling to the FSA9591. The second path for GSM noise is

through electromagnetic coupling onto the signal lines.

a) Keep the distance between the USB controller and the

device less than one inch (< 25 mm).

b) For best results, this distance should be <18 mm. This

keeps it less than one quarter (¼) of the transmission

electrical length.

2. Use an impedance calculator to ensure 90 Ω differential

impedance for DP_CON and DM_CON lines.

In most cases, the noise introduced as a result is on the V_BAT

and/or GND supply rails. Following are recommendations for

PCB board design that help address these two sources of TDMA

/ GSM noise.

3. Select the best transmission line for the application.

a) For example, for a densely populated board, select an

edge-coupled differential stripline.

1. Provide a wide, low-impedance GND return path to both the

FSA9591 and to the power amplifier that sources the phone

transmit block.

4. Minimize the use of vias and keep HS USB lines on same

plane in the stack.

a) Vias are an interruption in the impedance of the

transmission line and should be avoided.

2. Provide separate GND connections to PCB GND plane for

each device. Do not share GND return paths.

b) Try to avoid routing schemes that generally force the

use of at least two vias: one on each end to get the

signal to and from the surface.

3. Add as large a decoupling capacitor as possible (1µF)

between the V_BATpin and GND to shunt any power supply

noise away from the FSA9591. Also add decoupling

capacitance at the power amplifier (see reference application

in Figure 1 for recommended decoupling capacitor values).

5. Cross lines, only if necessary, orthogonally to avoid noise

coupling (traces running in parallel couple).

4. Add 33pF shunt capacitors on any PCB nodes with the

potential to collect radiated energy from the phone

transmitter.

6. If possible, separate HS USB lines with GND to improve

isolation.

a) Routing GND, power, or components close to the

transmission lines can create impedance discontinuities.

5. Add a series R_BATresistor prior to the decoupling capacitor

on the V_BATpin to attenuate noise prior to reaching the

FSA9591.

7. Match transmission line pairs as much as possible to

improve skew performance.

8. Avoid sharp bends in PCB traces; a chamfer or rounding is

generally preferred.

9. Place decoupling for power pins as close to the device as

possible.

a) Use low-ESR capacitors for decoupling if possible.

b) Use a tuned PI filter to negate the effects of switching

power supplies and other noise sources, if needed.

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

38

14. Reference Schematic

R_{ID_CON}

DM_HOST

TxD_HOST

RxD_HOST

V_REF

FSA9591

ID_CON

R_{DM_CON}

DM_CON

DP_CON

R_{DP_CON}

TVS₁

C_VREF

TVS₁

V_{BUS_IN}

V_LDO1

V_LDO2

C_{VBUS_IN}

TVS₂

C_VLDO2

C_VLDO1

VDDIO

CHG_CAP

V_DDIO

Open-Drain Only

(2)

R_PU

GPO1

GPO2

V_BAT

TVS₃

C_VBAT2

C_VBAT1

C_{CHG_CAP}

C_VDDIO

V2_3

ON_KEY_N

COLMx

ROWx

VDDIO

VICHG

INT_N

(2)

R_PU

I2C_SCL

I2C_SDA

JIG

ON_BT_UP

R_PD

RESET_N

DETBAT_N⁽³⁾

GND⁽¹⁾

R_LEAK

C_LOAD

R_LOAD

Notes

1) For best performance, provide clean ground path for FSA9591

2) Pull-up resistor values for these pins are application specific. Please contact

Fairchild for best recommendations for exact application.

3) For proper detection on DETBAT_N the following guidelines must be met:

A) C_LOADmust be kept under 500pF for the FSA9591 to properly detect a battery

is not present.

B) R_LEAKmust be at least 1G? to limit the leakage current on DETBAT_N for the

FSA9591 to properly detect a battery is not present.

C) R_LOADmust be 100K? or less for the FSA9591 to detect a battery.

Figure 25. Reference Schematic Diagram

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

39

Table 33. Recommended Component Values for Reference Schematic

Recommended Value

Symbol

Parameter

Unit

Notes

Min.

Typ. Max.

This capacitance can affect the startup

timing of V_REF

C_VREF

V_REFDecoupling

1

10

100

nF

µF

C_VLDO1

,

V_VLDOxDecoupling

1

C_VLDO2

C_{CHG_CAP}

C_VDDIO

C_VBAT1

C_VBAT2

R_PU

CHG_CAP Decoupling

V_DDIODecoupling

0.1

2.2

µF

kΩ

1.0

V_BATDecoupling

4.7

10.0

Pull-up Values

These values are application specific.

R_{ID_CON},R_{DM_}ID_CON, DP_CON and DM_CON

_CON,R_{DP_CON}Series Resistance

Series resistance to improve surge

performance of high-speed USB path.

2.2

1

Ω

Recommended high-speed TVS diodes

to improve ESD performance.

C_TVS1

High-Speed TVS Diodes

pF

V_TVS2

R_TVS2

V_TVS3

R_TVS3

High-Speed TVS Diode

TVS Diode

32

1.4

6

V

Ω

V_BRfor TVS on the V_{BUS_IN}line.

R_ONfor TVS on the V_{BUS_IN}line.

V_BRfor TVS on the CHG_CAP line.

R_ONfor TVS on the CHG_CAP line.

V

TVS Diode

50

mΩ

This is the recommended capacitance in

the USB standard (for the downstream

port V_BUScapacitance specification).

C_{VBUS_IN}

V_{BUS_IN}Decoupling

1.0

4.7

10.0

µF

This is the maximum leakage on

DETBAT_N pin to ensure proper

detection of no battery.

DETBAT_N Maximum Leakage

Specification

R_LEAK

C_LOAD

R_LOAD

1

GΩ

pF

DETBAT_N Maximum Capacitance

Specification

This is the maximum capacitance for

proper detection of the battery.

500

100

This is the maximum resistance for

detection of battery present on

DETBAT_N.

DETBAT_N Detection Threshold

ON_BT_UP Pull-Down Resistance

kΩ

These values are application specific

based on disable timing required for

ON_BT_UP.

R_PD

100

kΩ

Product-Specific Dimensions

Product

D

E

X

Y

FSA9591UCX

2.38

1.98

0.19

www.fairchildsemi.com

FSA9591 • Rev 1.0.2

40

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1


型号：	FSA9591UCX
厂家：	ONSEMI
描述：	USB 配件检测开关，带集成式线性电池充电器电池开关
文件：	总43页 (文件大小：2079K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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