FSAM10SH60A [ONSEMI]
智能功率模块，600V，10A;
| 型号： | FSAM10SH60A |
| 厂家： | 
ONSEMI |
| 描述： | 智能功率模块，600V，10A 电动机控制 |
| 文件： | 总17页 (文件大小：805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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January 2014
FSAM10SH60A
Motion SPM® 2 Series
Features
General Description
• UL Certified No. E209204 (UL1557)
FSAM10SH60A is a Motion SPM® 2 module
providing a fully-featured, high-performance inverter
stage for AC Induction, BLDC, and PMSM motors.
These modules integrate optimized gate drive of
the built-in IGBTs to minimize EMI and losses, while
• 600 V - 10 A 3-Phase IGBT Inverter with Integral
Gate Drivers and Protection
• Low-Loss, Short-Circuit Rated IGBTs
• Low Thermal Resistance Using Ceramic
Substrate
also
providing multiple on-module
protection
features including under-voltage lockouts, over-
current shutdown, thermal monitoring, and fault
reporting. The built-in, high-speed HVIC requires
only a single supply voltage and translates the
incoming logic-level gate inputs to the high-voltage,
high-current drive signals required to properly drive
the module's internal IGBTs. Separate negative
IGBT terminals are available for each phase to
support the widest variety of control algorithms.
• Separate Open-Emitter Pins from Low Side IGBTs
for Three-Phase Current Sensing
• Single-Grounded Power Supply
• Optimized for 15 kHz Switching Frequency
• Built-in NTC Thermistor for Temperature
Monitoring
• Inverter Power Rating of 0.5 kW / 100~253 VAC
• Adjustable Current Protection Level via Selection
of Sense-IGBT Emitter's External Rs
• Isolation Rating: 2500 Vrms / min.
Applications
• Motion Control - Home Appliance / Industrial Motor
Resource
• AN-9043 - Motion SPM® 2 Series User's Guide
Figure 1. Package Overview
Package Marking and Ordering Information
Device
Device Marking
Package
Packing Type
Quantity
FSAM10SH60A
FSAM10SH60A
S32AA-032
Rail
8
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
1
www.fairchildsemi.com
Integrated Power Functions
•
600V - 10 A IGBT inverter for three-phase DC / AC power conversion (please refer to Figure 3)
Integrated Drive, Protection and System Control Functions
•
For inverter high-side IGBTs: gate drive circuit, high-voltage isolated high-speed level shifting
control circuit Under-Voltage Lock-Out (UVLO) Protection
Note) Available bootstrap circuit example is given in Figures 13 and 14.
For inverter low-side IGBTs: gate drive circuit, Short-Circuit Protection (SCP)
control supply circuit Under-Voltage Lock-Out (UVLO) Protection
Temperature Monitoring: system temperature monitoring using built-in thermistor
Note) Available temperature monitoring circuit is given in Figure 14.
•
•
•
•
Fault signaling: corresponding to a SC fault (low-side IGBTs) and UV fault (low-side control supply)
Input interface: active-LOW Interface, works with 3.3 / 5 V logic, Schmitt-trigger input
Pin Configuration
(1) VCC(L)
(24) VTH
(25) RTH
(2) com(L)
(3) IN(UL)
(4) IN(VL)
(5) IN(WL)
(6) com(L)
(7) FO
(26) NU
(27) NV
(28) NW
(8) CFOD
(9) CSC
(10) RSC
(29) U
(30) V
(31) W
(11) IN(UH)
(12) VCC(UH)
Case Temperature (TC)
Detecting Point
(13) VB(U)
(14) VS(U)
(15) IN(VH)
(16) com(H)
(17) VCC(VH)
(18) VB(V)
(19) VS(V)
Ceramic Substrate
(20) IN(WH)
(21) VCC(WH)
(32) P
(22) VB(W)
(23) VS(W)
Figure 2. Top View
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
2
www.fairchildsemi.com
Pin Descriptions
Pin Number
Pin Name
VCC(L)
COM(L)
IN(UL)
IN(VL)
IN(WL)
COM(L)
VFO
Pin Description
Low-Side Common Bias Voltage for IC and IGBTs Driving
Low-Side Common Supply Ground
1
2
3
Signal Input Terminal for Low-Side U-Phase
Signal Input Terminal for Low-Side V-Phase
Signal Input Terminal for Low-Side W-Phase
Low-Side Common Supply Ground
4
5
6
7
Fault Output
8
CFOD
CSC
Capacitor for Fault Output Duration Selection
Capacitor (Low-Pass Filter) for Short-Circuit Current Detection Input
Resistor for Short-Circuit Current Detection
Signal Input for High-Side U-Phase
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RSC
IN(UH)
VCC(UH)
VB(U)
VS(U)
IN(VH)
COM(H)
VCC(VH)
VB(V)
VS(V)
IN(WH)
VCC(WH)
VB(W)
VS(W)
VTH
High-Side Bias Voltage for U-Phase IC
High-Side Bias Voltage for U-Phase IGBT Driving
High-SideBias Voltage Ground for U-Phase IGBT Driving
Signal Input for High-Side V-Phase
High-Side Common Supply Ground
High-Side Bias Voltage for V-Phase IC
High-Side Bias Voltage for V-Phase IGBT Driving
High-Side Bias Voltage Ground for V-Phase IGBT Driving
Signal Input for High-side W-Phase
High-Side Bias Voltage for W-Phase IC
High-Side Bias Voltage for W-Phase IGBT Driving
High-Side Bias Voltage Ground for W-Phase IGBT Driving
Thermistor Bias Voltage
RTH
Series Resistor for the Use of Thermistor (Temperature Detection)
Negative DC-Link Input Terminal for U-Phase
Negative DC-Link Input Terminal for V-Phase
Negative DC-Link Input Terminal for W-Phase
Output for U-Phase
NU
NV
NW
U
V
Output for V-Phase
W
Output for W-Phase
P
Positive DC-Link Input
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
3
www.fairchildsemi.com
Internal Equivalent Circuit and Input/Output Pins
P (32)
W (31)
(22) VB(W)
VB
(21) VCC(WH)
VCC
OUT
COM
(20) IN(WH)
IN
VS
(23) VS(W)
(18) VB(V)
VB
(17) VCC(VH)
VCC
(16) COM(H)
(15) IN(VH)
OUT
VS
COM
IN
V (30)
(19) VS(V)
(13) VB(U)
VB
(12) VCC(UH)
VCC
OUT
VS
COM
IN
(11) IN(UH)
(14) VS(U)
U (29)
(10) RSC
(9) CSC
OUT(WL)
OUT(VL)
OUT(UL)
C(SC)
C(FOD)
VFO
(8) CFOD
NW (28)
(7) VFO
(6) COM(L)
(5) IN(WL)
(4) IN(VL)
(3) IN(UL)
IN(WL)
IN(VL)
IN(UL)
NV (27)
(2) COM(L)
(1) VCC(L)
COM(L)
VCC
NU (26)
RTH (25)
THERMISTOR
VTH (24)
Figure 3. Internal Block Diagram
1st Notes:
1. Inverter low-side is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving, current-sensing and
protection functions.
2. Inverter power side is composed of four inverter DC-link input pins and three inverter output pins.
3. Inverter high-side is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT.
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
4
www.fairchildsemi.com
Absolute Maximum Ratings (TJ = 25°C, unless otherwise specified.)
Inverter Part
Item
Symbol
Condition
Applied to DC-Link
Rating
450
Unit
V
Supply Voltage
VDC
Supply Voltage (Surge)
VPN(Surge) Applied between P and N
VCES
500
V
Collector - Emitter Voltage
Each IGBT Collector Current
Each IGBT Collector Current
Each IGBT Collector Current (Peak)
Collector Dissipation
600
V
± IC
± IC
± ICP
PC
TC = 25°C
10
A
TC = 100°C
9
A
TC = 25°C , Under 1ms Pulse Width
TC = 25°C per Chip
(2nd Note 1)
20
A
43
W
°C
Operating Junction Temperature
TJ
-20 ~ 125
2nd Notes:
1. It would be recommended that the average junction temperature should be limited to T 125C (at T 100C) in order to guarantee safe operation.
J
C
Control Part
Item
Symbol
Condition
Rating
Unit
Control Supply Voltage
High-Side Control Bias Voltage
Input Signal Voltage
VCC
Applied between VCC(UH), VCC(VH), VCC(WH)
COM(H), VCC(L) - COM(L)
-
20
V
V
V
VBS
VIN
Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W)
VS(W)
-
20
Applied between IN(UH), IN(VH), IN(WH) - COM(H)
IN(UL), IN(VL), IN(WL) - COM(L)
-0.3 ~ VCC+0.3
Fault Output Supply Voltage
Fault Output Current
VFO
IFO
Applied between VFO - COM(L)
Sink Current at VFO Pin
-0.3 ~ VCC+0.3
5
V
mA
V
Current-Sensing Input Voltage
VSC
Applied between CSC - COM(L)
-0.3 ~ VCC+0.3
Total System
Item
Symbol
Condition
Rating
Unit
Self-Protection Supply Voltage Limit
(Short-Circuit Protection Capability)
VPN(PROT) Applied to DC-Link,
400
V
V
CC = VBS = 13.5 ~ 16.5 V
TJ = 125°C, Non-Repetitive, < 6 s
Module Case Operation Temperature
Storage Temperature
TC
See Figure 2
-20 ~ 100
-20 ~ 125
2500
°C
°C
TSTG
VISO
Isolation Voltage
60Hz, Sinusoidal, AC 1 Minute, Connect
Pins to Heat Sink Plate
Vrms
Thermal Resistance
Item
Symbol
Condition
Min. Typ. Max. Unit
Junction to Case Thermal
Resistance
Rth(j-c)Q Inverter IGBT Part (per 1/6 module)
Rth(j-c)F Inverter FWDi Part (per 1/6 module)
-
-
-
-
-
-
2.90 °C/W
3.60 °C/W
0.06 °C/W
Contact Thermal
Resistance
Rth(c-f) Ceramic Substrate (per 1 Module)
Thermal Grease Applied (2nd Note 3)
2nd Notes:
2. For the measurement point of case temperature(T ), please refer to Figure 2.
C
3. The thickness of thermal grease should not be more than 100 m.
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
5
www.fairchildsemi.com
Electrical Characteristics
Inverter Part (TJ = 25°C, unless otherwise specified.)
Item
Symbol
Condition
IC = 10 A, TJ = 25°C
Min.
Typ.
Max. Unit
Collector - Emitter
Saturation Voltage
VCE(SAT) VCC = VBS = 15 V
-
-
-
-
-
-
-
-
-
-
-
-
2.50
V
V
V
IN = 0 V
IC = 10 A, TJ = 125°C
IC = 10 A, TJ = 25°C
IC = 10 A, TJ = 125°C
2.60
FWDi Forward Voltage
VFM
VIN = 5 V
-
2.30
V
-
2.10
V
Switching Times
tON
tC(ON)
tOFF
VPN = 300 V, VCC = VBS = 15 V
C = 10 A, TJ = 25°C
IN = 5 V 0V, Inductive Load
0.27
0.12
0.60
0.23
0.13
-
-
s
s
s
s
s
A
I
V
-
-
(High, Low-side)
tC(OFF)
trr
-
-
(2nd Note 4)
Collector - Emitter
Leakage Current
ICES
VCE = VCES, TJ = 25°C
250
2nd Notes:
4.
t
and t
include the propagation delay time of the internal drive IC. t
and t
are the switching time of IGBT itself under the given gate driving condition
C(OFF)
ON
OFF
C(ON)
internally. For the detailed information, please see Figure 4.
100% IC
trr
IC
VCE
VCE
IC
VIN
tON
VIN
tOFF
t C(ON)
tC(OFF)
VIN(ON)
90% IC
10% IC 10% VCE
VIN(OFF)
10% VCE 10% IC
(a) Turn-on
(b) Turn-off
Figure 4. Switching Time Definition
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
6
www.fairchildsemi.com
Electrical Characteristics (TJ = 25°C, unless otherwise specified.)
Control Part
Item
Symbol
Condition
VCC(L) - COM(L)
Min. Typ. Max. Unit
Quiescent VCC
Supply Current
IQCCL VCC = 15 V
-
-
-
-
-
-
26
mA
A
A
IN(UL, VL, WL) = 5V
IQCCH VCC = 15 V
IN(UH, VH, WH) = 5V
VBS = 15 V
IN(UH, VH, WH) = 5V
VFOH VSC = 0 V, VFO Circuit: 4.7 k to 5 V Pull-up
VFOL VSC = 1 V, VFO Circuit: 4.7 k to 5 V Pull-up
VSC(ref) VCC = 15 V (2nd Note 5)
VCC(UH), VCC(VH), VCC(WH)
COM(H)
VB(U) - VS(U), VB(V) -VS(V)
B(W) - VS(W)
-
130
420
Quiescent VBS
Supply Current
IQBS
,
V
Fault Output Voltage
4.5
-
-
-
-
V
V
V
V
1.1
Short-Circuit Trip Level
0.45 0.51 0.56
0.45 0.51 0.56
Sensing Voltage
of IGBT Current
VSEN RSC = 50 , RSU = RSV = RSW = 0 and IC = 15 A
(See a Figure 6)
Supply Circuit Under-
Voltage Protection
UVCCD Detection Level
UVCCR Reset Level
UVBSD Detection Level
UVBSR Reset Level
11.5 12.0 12.5
12.0 12.5 13.0
V
V
7.3
8.6
1.4
-
9.0 10.8
10.3 12.0
V
V
Fault Output Pulse Width
ON Threshold Voltage
OFF Threshold Voltage
ON Threshold Voltage
OFF Threshold Voltage
Resistance of Thermistor
tFOD
CFOD = 33 nF (2nd Note 6)
1.8
2.0
ms
V
VIN(ON) High-Side
VIN(OFF)
Applied between IN(UH)
IN(VH), IN(WH) - COM(H)
,
-
-
0.8
3.0
-
-
V
VIN(ON) Low-Side
VIN(OFF)
Applied between IN(UL)
,
-
0.8
V
IN(VL), IN(WL) - COM(L)
3.0
-
-
-
-
-
V
RTH
@ TTH = 25°C (2nd Note 7, Figure 5)
@ TTH = 100°C (2nd Note 7, Figure 5)
50
3.4
k
k
-
2nd Notes:
5. Short-circuit protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (R ) should be selected
SC
around 50 in order to make the SC trip-level of about 15A at the shunt resistors (R , R , R ) of 0. For the detailed information about the relationship
SU
SV
SW
between the external sensing resistor (R ) and the shunt resistors (R , R , R ), please see Figure 6.
SC
SU
SV
SW
-6
6. The fault-out pulse width t
depends on the capacitance value of C
according to the following approximate equation: C
= 18.3 x 10 x t
[F]
FOD
FOD
FOD
FOD
7.
T
is the temperature of thermistor itself. To know case temperature (T ), please make the experiment considering your application.
TH
C
R-T Curve
70k
60k
50k
40k
30k
20k
10k
0
20
30
40
50
60
70
80
90
100
110
120
Temperature TTH[℃]
Figure 5. R-T Curve of The Built-in Thermistor
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
7
www.fairchildsemi.com
100
80
60
40
20
0
(1)
(2)
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
RSU,RSV,RSW []
Figure 6. RSC Variation by Change of Shunt Resistors ( RSU, RSV, RSW) for Short-Circuit Protection
(1) @ Current Trip Level ≒ 10 A
(2) @ Current Trip Level ≒ 15 A
Recommended Operating Conditions
Item
Symbol
Condition
Min. Typ. Max. Unit
Supply Voltage
VPN
Applied between P - NU, NV, NW
-
300
400
V
V
Control Supply Voltage
High-side Bias Voltage
VCC
Applied between VCC(UH), VCC(VH), VCC(WH)
COM(H), VCC(L) - COM(L)
-
13.5 15.0 16.5
VBS
tdead
fPWM
Applied between VB(U) - VS(U), VB(V) - VS(V)
B(W) - VS(W)
,
13.0 15.0 18.5
V
V
Blanking Time for Preventing
Arm-short
For Each Input Signal
1.0
-
-
s
PWM Input Signal
TC 100°C, TJ 125°C
-
15
-
-
-
kHz
Minimum Input Pulse Width
PWIN(OFF) 200 VPN 400 V, 13.5 VCC 16.5 V,
13.0 VBS 18.5 V, IC 20 A,
-20 TJ 125°C
3
s
V
IN = 5 V 0 V, Inductive Load (2nd Note 8)
Input ON Threshold Voltage
Input OFF Threshold Voltage
VIN(ON) Applied between IN(UH), IN(VH), IN(WH)
COM(H), IN(UL), IN(VL), IN(WL) - COM(L)
-
-
0 ~ 0.65
4 ~ 5.5
V
V
VIN(OFF) Applied between IN(UH), IN(VH), IN(WH)
COM(H), IN(UL), IN(VL), IN(WL) - COM(L)
2nd Notes:
®
8. Motion SPM 2 product might not make response if the PW
is less than the recommended minimum value.
IN(OFF)
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
8
www.fairchildsemi.com
Mechanical Characteristics and Ratings
Item
Condition
Recommended 10 kg•cm
Min.
Typ.
10
Max.
12
Units
kg•cm
N•m
m
Mounting Torque
Mounting Screw: M4
(2nd Note 9 and 10)
8
0.78
0
Recommended 0.98 N•m
See Figure 7
0.98
-
1.17
+120
-
Ceramic Flatness
Weight
-
35
g
(+)
(+)
(+)
Datum Line
Figure 7. Flatness Measurement Position of The Ceramic Substrate
2nd Notes:
9. Do not make over torque or mounting screws. Much mounting torque may cause ceramic substrate cracks and bolts and Al heat-sink destruction.
10.Avoid one side tightening stress. Figure 8 shows the recommended torque order for mounting screws. Uneven mounting can cause the Motion SPM® 2 package
ceramic substrate to be damaged.
2
1
Figure 8. Mounting Screws Torque Order (1 2)
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
9
www.fairchildsemi.com
Time Charts of Protective Function
Input Signal
Internal IGBT
Gate-Emitter Voltage
P3
P2
UV
reset
P5
Control Supply Voltage
UV
detect
P6
P1
Output Current
P4
Fault Output Signal
P1 : Normal operation: IGBT ON and conducting current .
P2 : Under-voltage detection.
P3 : IGBT gate interrupt.
P4 : Fault signal generation.
P5 : Under-voltage reset.
P6 : Normal operation: IGBT ON and conducting current.
Figure 9. Under-Voltage Protection (Low-Side)
Input Signal
Internal IGBT
Gate-Emitter Voltage
P3
P2
UV
reset
P5
Control Supply Voltage
VBS
UV
detect
P6
P1
Output Current
Fault Output Signal
P4
P1 : Normal operation: IGBT ON and conducting current.
P2 : Under-voltage detection.
P3 : IGBT gate interrupt.
P4 : No fault signal.
P5 : Under-voltage reset.
P6 : Normal operation: IGBT ON and conducting current.
Figure 10. Under-Voltage Protection (High-Side)
©2003 Fairchild Semiconductor Corporation
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FSAM10SH60A Rev. C8
P5
Input Signal
P6
Internal IGBT
Gate-Emitter Voltage
SC Detection
P1
P4
P7
Output Current
P2
SC Reference
Voltage (0.5V)
Sensing Voltage
RC Filter Delay
P8
Fault Output Signal
P3
P1 : Normal operation: IGBT ON and conducting current.
P2 : Short-circuit current detection.
P3 : IGBT gate interrupt / fault signal generation.
P4 : IGBT is slowly turned off.
P5 : IGBT OFF signal.
P6 : IGBT ON signal: but IGBT cannot be turned on during the fault-output activation.
P7 : IGBT OFF state.
P8 : Fault-output reset and normal operation start.
Figure 11. Short-Circuit Protection (Low-Side Operation Only)
5 V
RPF
4.7 k
=
RPL
2 k
=
RPH
=
SPM
4.7 k
100
100
100
,
,
,
IN(UH) IN(VH)
IN(WH)
IN(WL)
,
IN(UL) IN(VL)
MCU
VFO
CPF
1 nF
=
CPL
0.47 nF
=
CPH
1.2 nF
=
1 nF
COM
Figure 12. Recommended MCU I/O Interface Circuit
3rd Notes:
1. It would be recommended that by-pass capacitors for the gating input signals, IN(UL), IN(VL), IN(WL), IN(UH), IN(VH) and IN(WH) should be placed on the Motion
SPM® 2 product pins and on the both sides of MCU and Motion SPM 2 Product for the fault output signal, VFO, as close as possible.
2. The logic input works with standard CMOS or LSTTL outputs.
3. RPLCPL/RPHCPH/RPFCPF coupling at each Motion SPM 2 product input is recommended in order to prevent input/output signals’ oscillation and it should be as
close as possible to each of Motion SPM 2 Product pins.
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
11
www.fairchildsemi.com
These values depend on PWM control algorithm
15 V
One-Leg Diagram of
Motion SPM® 2 Product
P
RBS
DBS
0.1 µF
Vcc VB
IN
HO
22 µF
COM VS
Inverter
Output
Vcc
IN
OUT
470 µF
0.1 µF
COM
N
Figure 13. Recommended Bootstrap Operation Circuit and Parameters
3rd Notes:
4. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
5. The ceramic capacitor placed between VCC - COM should be over 0.1 F and mounted as close to the pins of the Motion SPM® 2 product as possible.
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
12
www.fairchildsemi.com
15 V
5 V
RBS
DBS
P (32)
(22) VB(W)
VB
(21) VCC(WH)
VCC
RPH
OUT
VS
COM
IN
RS
RS
RS
CBS
(20) IN(WH)
(23) VS(W)
CBSC
CBSC
CBSC
W (31)
Gating WH
CPH
RBS
DBS
(18) VB(V)
VB
(17) VCC(VH)
VCC
(16) COM(H)
(15) IN(VH)
RPH
OUT
VS
COM
IN
CBS
Gating VH
V (30)
(19) VS(V)
M
CPH
DBS
RBS
(13) VB(U)
VB
M
C
U
(12) VCC(UH)
VCC
CDCS
Vdc
OUT
VS
RPH
COM
IN
CBS
(11) IN(UH)
(14) VS(U)
U (29)
Gating UH
CPH
RSC
RF
5 V
(10) RSC
RCSC
(9) CSC
OUT(WL)
OUT(VL)
OUT(UL)
C(SC)
C(FOD)
VFO
(8) CFOD
RPL RPL RPL RPF
CSC
RSW
N
W (28)
RS
RS
CFOD
(7) VFO
Fault
(6) COM(L)
(5) IN(WL)
(4) IN(VL)
(3) IN(UL)
Gating WH
Gating VH
Gating UH
IN(WL)
IN(VL)
IN(UL)
RS
RS
RSV
NV (27)
(2) COM(L)
(1) VCC(L)
COM(L)
VCC
CBPF
CPL CPL CPL CPF
RSU
NU (26)
5 V
CSPC15
VTH (24)
CSP15
THERMISTOR
R
TH (25)
RTH
CSPC05
CSP05
Temp. Monitoring
RFW
RFV
RFU
W-Phase Current
V-Phase Current
U-Phase Current
CFW
CFU
CFV
Figure 14. Application Circuit
4th Notes:
1. RPLCPL/RPHCPH /RPFCPF coupling at each Motion SPM® 2 product input is recommended in order to prevent input signals’ oscillation and it should be as close as
possible to each Motion SPM 2 product input pin.
2. By virtue of integrating an application specific type HVIC inside the Motion SPM 2 product, direct coupling to MCU terminals without any optocoupler or transformer
isolation is possible.
3. VFO output is open-collector type. This signal line should be pulled up to the positive side of the 5 V power supply with approximately 4.7 k resistance. Please
refer to Figure 12.
4. CSP15 of around seven times larger than bootstrap capacitor CBS is recommended.
5. VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin 8) and COM(L)(pin 2). (Example : if CFOD = 33 nF, then
tFO = 1.8 ms (typ.)) Please refer to the 2nd note 6 for calculation method.
6. Each input signal line should be pulled up to the 5 V power supply with approximately 4.7 k (at high side input) or 2 kat low side input) resistance (other RC
coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board).
Approximately a 0.22 ~ 2 nF by-pass capacitor should be used across each power supply connection terminals.
7. To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible.
8. In the short-circuit protection circuit, please select the RFCSC time constant in the range 3 ~ 4 s.
9. Each capacitor should be mounted as close to the pins of the Motion SPM 2 product as possible.
10. To prevent surge destruction, the wiring between the smoothing capacitor and the P & N pins should be as short as possible. The use of a high frequency non-
inductive capacitor of around 0.1 ~ 0.22 F between the P&N pins is recommended.
11. Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the MCU and
the relays. It is recommended that the distance be 5 cm at least.
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
13
www.fairchildsemi.com
Detailed Package Outline Drawings
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manner without notice. Please note the revision and/or data on the drawing and contact a FairchildSemiconductor
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worldwide therm and conditions, specifically the the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/MO/MOD32AA.pdf
©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
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©2003 Fairchild Semiconductor Corporation
FSAM10SH60A Rev. C8
15
www.fairchildsemi.com
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