FSDM07652RWDTU [ONSEMI]

用于 70W 离线反激转换器的 650V 集成电源开关;


型号：	FSDM07652RWDTU
厂家：	ONSEMI
描述：	用于 70W 离线反激转换器的 650V 集成电源开关开关电源开关转换器
文件：	总22页 (文件大小：380K)
中文：	中文翻译
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FSDM07652R

Green Mode Fairchild Power Switch (FPS )

Features

• Internal Avalanche Rugged Sense FET

• Advanced Burst-Mode operation consumes under 1 W at

240VAC & 0.5W load

• Precision Fixed Operating Frequency (66kHz)

• Internal Start-up Circuit

• Pulse by Pulse Current Limiting

• Abnormal Over Current Protection (AOCP)

• Over Voltage Protection (OVP)

OUTPUT POWER TABLE

(3)

230VAC ±15%

85-265VAC

PRODUCT

Adapt-

Open

Frame

Adapt- Open

(1)

(2)

(1)

(2)

Frame

FSDM0565R

FSDM07652R

60W

70W

80W

50W

60W

70W

• Over Load Protection (OLP)

• Internal Thermal Shutdown Function (TSD)

• Auto-Restart Mode

• Under Voltage Lock Out (UVLO) with hysteresis

• Low Operating Current (2.5mA)

Table 1. Notes: 1. Typical continuous power in a non-ven-

tilated enclosed adapter measured at 50°C ambient. 2.

Maximum practical continuous power in an open frame

design at 50°C ambient. 3. 230 VAC or 100/115 VAC with

doubler.

•

Built-in Soft Start

Application

• SMPS for LCD monitor and STB

• Adaptor

Typical Circuit

Description

The FSDM07652R is an integrated Pulse Width Modulator

(PWM) and Sense FET specifically designed for high

performance offline Switch Mode Power Supplies (SMPS)

with minimal external components. This device is an

integrated high voltage power switching regulator which

combine an avalanche rugged Sense FET with a current mode

PWM control block. The PWM controller includes integrated

fixed frequency oscillator, under voltage lockout, leading

edge blanking (LEB), optimized gate driver, internal soft

start, temperature compensated precise current sources for a

loop compensation and self protection circuitry. Compared

with discrete MOSFET and PWM controller solution, it can

reduce total cost, component count, size and weight simulta-

neously increasing efficiency, productivity, and system

reliability. This device is a basic platform well suited for cost

effective designs of flyback converters.

OUT

Vstr

PWM

Drain

Vfb

Vcc

Source

Figure 1. Typical Flyback Application

Rev.1.0.6

FSDM07652R

Internal Block Diagram

Vcc

Vstr

Drain

N.C 5

I_start

0.5/0.7V

Internal

Bias

Vref

8V/12V

Vcc good

Vcc

I_delay

Vref

Switching disable

OSC

I_FB

Vfb

PWM

Gate

driver

2.5R

Soft start

LEB

V_SD

Vcc

Vovp

TSD

GND

Vcc good

AOCP

Vocp

Figure 2. Functional Block Diagram of FSDM07652R

FSDM07652R

Pin Definitions

Pin Number

Pin Name

Pin Function Description

This pin is the high voltage power Sense FET drain. It is designed to drive the

transformer directly.

Drain

GND

This pin is the control ground and the Sense FET source.

This pin is the positive supply voltage input. During start up, the power is sup-

plied by an internal high voltage current source that is connected to the Vstr pin.

When Vcc reaches 12V, the internal high voltage current source is disabled and

the power is supplied from the auxiliary transformer winding.

Vcc

This pin is internally connected to the inverting input of the PWM comparator.

The collector of an opto-coupler is typically tied to this pin. For stable operation,

a capacitor should be placed between this pin and GND. If the voltage of this pin

reaches 6.0V, the over load protection is activated resulting in shutdown of the

Vfb

FPS^TM

N.C

Vstr

This pin is connected directly to the high voltage DC link. At startup, the internal

high voltage current source supplies internal bias and charges the external ca-

pacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal cur-

rent source is disabled.

Pin Configuration

TO-220F-6L

6.Vstr

5.N.C.

4.Vfb

3.Vcc

2.GND

1.Drain

Figure 3. Pin Configuration (Top View)

FSDM07652R

Absolute Maximum Ratings

(Ta=25°C, unless otherwise specified)

Parameter

Symbol

Value

650

Unit

Drain-source voltage

Vstr Max Voltage

DSS

STR

(1)

Pulsed Drain current (Tc=25°C)

Continuous Drain Current(Tc=25°C)

Continuous Drain Current(Tc=100°C)

Single pulsed avalanche energy ⁽²⁾

Single pulsed avalanche current ⁽³⁾

Supply voltage

3.8

2.4

370

Input voltage range

-0.3 to V

Total power dissipation(Tc=25°C)

Operating junction temperature

Operating ambient temperature

Storage temperature range

P (Watt H/S)

°C

Internally limited

-25 to +85

STG

-55 to +150

ESD Capability, HBM Model (All pins

excepts for Vstr and Vfb)

2.0

(GND-Vstr/Vfb=1.5kV)

ESD Capability, Machine Model (All pins

excepts for Vstr and Vfb)

300

(GND-Vstr/Vfb=225V)

Notes:

1. Repetitive rating: Pulse width limited by maximum junction temperature

2. L=14mH, starting Tj=25°C

3. L=13uH, starting Tj=25°C

Thermal Impedance

Parameter

Symbol

Value

49.90

2.78

Unit

°C/W

(1)

Junction-to-Ambient Thermal

Junction-to-Case Thermal

θ_JA

(2)

θ_JC

Notes:

1. Free standing with no heat-sink under natural convection.

2. Infinite cooling condition - Refer to the SEMI G30-88.

FSDM07652R

Electrical Characteristics

(Ta = 25°C unless otherwise specified)

Parameter

Sense FET SECTION

Symbol

Condition

Min. Typ. Max. Unit

Drain source breakdown voltage

DSS

= 0V, I = 250µA

650

= 650V, V

= 520V

= 0V

µA

Zero gate voltage drain current

DSS

200

1.6

µA

= 0V, T = 125°C

Static drain source on resistance ⁽¹⁾

Output capacitance

= 10V, I = 2.5A

1.4

Ω

DS(ON)

= 0V, V = 25V,

f = 1MHz

100

OSS

Turn on delay time

Rise time

= 325V, I = 5A

D(ON)

(MOSFET switching

time is essentially

independent of

Turn off delay time

Fall time

115

D(OFF)

operating temperature)

CONTROL SECTION

Initial frequency

= 3V

kHz

OSC

Voltage stability

13V ≤ Vcc ≤ 18V

STABLE

Temperature stability ⁽²⁾

Maximum duty cycle

Minimum duty cycle

Start threshold voltage

Stop threshold voltage

Feedback source current

Soft-start time

∆F

-25°C ≤ Ta ≤ 85°C

±5

±10

OSC

MAX

MIN

=GND

START

STOP

0.7

0.9

250

1.1

Leading Edge Blanking time

BURST MODE SECTION

LEB

Vcc=14V

0.7

0.5

BURH

Burst Mode Voltages ⁽²⁾

BURL

PROTECTION SECTION

Peak current limit ⁽⁴⁾

=5V, V =14V

FB CC

2.2

2.5

2.8

OVER

Over voltage protection

OVP

Abnormal Over current protection

current ⁽³⁾

5.54 6.15

6.77

AOCP

Thermal shutdown temperature ⁽²⁾

Shutdown feedback voltage

130

5.5

145

6.0

160

6.5

°C

V ≥ 5.5V

FSDM07652R

Shutdown delay current

=5V

2.8

3.5

2.5

4.2

µA

DELAY

TOTAL DEVICE SECTION

=GND, V =14V

Operating supply current ⁽⁵⁾

=GND, V =10V

OP(MIN)

=GND, V =18V

OP(MAX)

Notes:

1. Pulse test : Pulse width ≤ 300µS, duty ≤ 2%

2. These parameters, although guaranteed at the design, are not tested in mass production.

3. These parameters, although guaranteed, are tested in EDS(wafer test) process.

4. These parameters indicate the inductor current.

5. This parameter is the current flowing into the control IC.

FSDM07652R

Comparison Between FS6M07652RTC and FSDM07652R

Function

FS6M07652RTC

FSDM07652R

FSDM07652R Advantages

Soft-Start

Adjustable soft-start Internal soft-start with • Gradually increasing current limit

time using an

external capacitor

typically 10ms (fixed)

during soft-start further reduces peak

current and voltage component

stresses

• Eliminates external components used

for soft-start in most applications

• Reduces or eliminates output

overshoot

Burst Mode Operation • Built into controller • Built into controller • Improve light load efficiency

• Output voltage

drops to around

half

• Output voltage fixed • Reduces no-load consumption

FSDM07652R

Typical Performance Characteristics

(These Characteristic Graphs are Normalized at Ta= 25°C)

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-50 -25

75 100 125

-50 -25

75 100 125

Junction Temperature(℃)

Operating Current vs. Temp

Start Threshold Voltage vs. Temp

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-50 -25

100 125

-50 -25

75 100 125

Junction Temperature(℃)

Stop Threshold Voltage vs. Temp

Operating Freqency vs. Temp

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.0

0.8

0.6

0.4

0.2

0.0

-50 -25

75 100 125

-50 -25

75 100 125

Junction Temperature(℃)

Maximum Duty vs. Temp

Feedback Source Current vs. Temp

FSDM07652R

Typical Performance Characteristics (Continued)

(These Characteristic Graphs are Normalized at Ta= 25°C)

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-50 -25

100 125

-50 -25

75 100 125

Junction Temperature(℃)

ShutDown Feedback Voltage vs. Temp

ShutDown Delay Current vs. Temp

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-50 -25

75 100 125

-50 -25

100 125

Junction Temperature(℃)

Over Voltage Protection vs. Temp

Burst Mode Enable Voltage vs. Temp

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.0

0.8

0.6

0.4

0.2

0.0

-50 -25

100 125

-50 -25

75 100 125

Junction Temperature(℃)

Burst Mode Disable Voltage vs. Temp

Current Limit vs. Temp

FSDM07652R

Typical Performance Characteristics (Continued)

(These Characteristic Graphs are Normalized at Ta= 25°C)

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-50 -25

75 100 125

Junction Temperature(℃)

Soft Start Time vs. Temp

FSDM07652R

2.1 Pulse-by-pulse current limit: Because current mode

control is employed, the peak current through the Sense FET

is limited by the inverting input of PWM comparator (Vfb*)

as shown in figure 5. Assuming that the 0.9mA current

source flows only through the internal resistor (2.5R +R= 2.8

kΩ), the cathode voltage of diode D2 is about 2.5V. Since D1

is blocked when the feedback voltage (Vfb) exceeds 2.5V,

the maximum voltage of the cathode of D2 is clamped at this

voltage, thus clamping Vfb*. Therefore, the peak value of

the current through the Sense FET is limited.

Functional Description

1. Startup : In previous generations of Fairchild Power

Switches (FPS^TM) the Vcc pin had an external start-up

resistor to the DC input voltage line. In this generation the

startup resistor is replaced by an internal high voltage current

source. At startup, an internal high voltage current source

supplies the internal bias and charges the external capacitor

(C ) that is connected to the Vcc pin as illustrated in figure

vcc

4. When Vcc reaches 12V, the FPS^TMbegins switching and

the internal high voltage current source is disabled. Then, the

FPS^TMcontinues its normal switching operation and the

power is supplied from the auxiliary transformer winding

unless Vcc goes below the stop voltage of 8V.

2.2 Leading edge blanking (LEB) : At the instant the

internal Sense FET is turned on, there usually exists a high

current spike through the Sense FET, caused by primary-side

capacitance and secondary-side rectifier reverse recovery.

Excessive voltage across the Rsense resistor would lead to

incorrect feedback operation in the current mode PWM

control. To counter this effect, the FPS^TMemploys a leading

edge blanking (LEB) circuit. This circuit inhibits the PWM

V_DC

C_Vcc

comparator for a short time (T

turned on.

) after the Sense FET is

LEB

Vcc

Vstr

Vcc

I_delay

Vref

I_FB

I_start

Vfb

SenseFET

OSC

Vref

H11A817A

8V/12V

Vcc good

C_B

2.5R

Gate

driver

V *

Internal

Bias

KA431

OLP

R_sense

V_SD

Figure 4. Internal startup circuit

Figure 5. Pulse width modulation (PWM) circuit

3. Protection Circuit : The FSDM07652R has several self

protective functions such as over load protection (OLP),

abnormal over current protection (AOCP), over voltage

protection (OVP) and thermal shutdown (TSD). Because

these protection circuits are fully integrated into the IC

without external components, the reliability can be improved

without increasing cost. Once the fault condition occurs,

switching is terminated and the Sense FET remains off. This

causes Vcc to fall. When Vcc reaches the UVLO stop

voltage, 8V, the protection is reset and the internal high

voltage current source charges the Vcc capacitor via the Vstr

pin. When Vcc reaches the UVLO start voltage,12V, the

FPS^TMresumes its normal operation. In this manner, the

auto-restart can alternately enable and disable the switching

of the power Sense FET until the fault condition is

eliminated (see figure 6).

2. Feedback Control : FSDM07652R employs current

mode control, as shown in figure 5. An opto-coupler (such as

the H11A817A) and shunt regulator (such as the KA431) are

typically used to implement the feedback network.

Comparing the feedback voltage with the voltage across the

Rsense resistor plus an offset voltage makes it possible to

control the switching duty cycle. When the reference pin

voltage of the KA431 exceeds the internal reference voltage

of 2.5V, the H11A817A LED current increases, thus pulling

down the feedback voltage and reducing the duty cycle. This

event typically happens when the input voltage is increased

or the output load is decreased.

FSDM07652R

V_FB

Fault

occurs

Fault

Power

Over load protection

Vds

removed

6.0V

2.5V

Vcc

T₁₂= Cfb*(6.0-2.5)/I_delay

T₁

Figure 7. Over load protection

T₂

12V

3.2 Abnormal Over Current Protection (AOCP) : Even

though the FPS^TMhas OLP (Over Load Protection) and

current mode PWM feedback, these are not enough to protect

the FPS^TMwhen a secondary side diode short or a

transformer pin short occurs. The FPS^TMhas an internal

AOCP (Abnormal Over Current Protection) circuit as shown

in figure 8. When the gate turn-on signal is applied to the

power Sense FET, the AOCP block is enabled and monitors

the current through the sensing resistor. The voltage across

the resistor is then compared with a preset AOCP level. If the

sensing resistor voltage is greater than the AOCP level for

longer than 300ns, the reset signal is applied to the latch,

resulting in the shutdown of SMPS.

Normal

operation

Fault

situation

Normal

operation

Figure 6. Auto restart operation

3.1 Over Load Protection (OLP) : Overload is defined as

the load current exceeding a pre-set level due to an

unexpected event. In this situation, the protection circuit

should be activated in order to protect the SMPS. However,

even when the SMPS is in the normal operation, the over

load protection circuit can be activated during the load

transition. In order to avoid this undesired operation, the over

load protection circuit is designed to be activated after a

specified time to determine whether it is a transient situation

or an overload situation. Because of the pulse-by-pulse

current limit capability, the maximum peak current through

the Sense FET is limited, and therefore the maximum input

power is restricted with a given input voltage. If the output

consumes beyond this maximum power, the output voltage

(Vo) decreases below the set voltage. This reduces the

current through the opto-coupler LED, which also reduces

the opto-coupler transistor current, thus increasing the

feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked

2.5R

OSC

PWM

Gate

driver

LEB

sense

AOCP

and the 3.5uA current source starts to charge C slowly up to

GND

Vaocp

Vcc. In this condition, Vfb continues increasing until it

reaches 6V, when the switching operation is terminated as

shown in figure 7. The delay time for shutdown is the time

Figure 8. AOCP block

required to charge C from 2.5V to 6.0V with 3.5uA. In

general, a 10 ~ 50 ms delay time is typical for most

applications.

3.3 Over voltage Protection (OVP) : If the secondary side

feedback circuit were to malfunction or a solder defect

caused an open in the feedback path, the current through the

opto-coupler transistor becomes almost zero. Then, Vfb

climbs up in a similar manner to the over load situation,

forcing the preset maximum current to be supplied to the

SMPS until the over load protection is activated. Because

more energy than required is provided to the output, the

FSDM07652R

output voltage may exceed the rated voltage before the over

load protection is activated, resulting in the breakdown of the

devices in the secondary side. In order to prevent this

situation, an over voltage protection (OVP) circuit is

employed. In general, Vcc is proportional to the output

voltage and the FPS^TMuses Vcc instead of directly

Vo^set

V_FB

monitoring the output voltage. If V exceeds 19V, an OVP

circuit is activated resulting in the termination of the

switching operation. In order to avoid undesired activation of

OVP during normal operation, Vcc should be designed to be

below 19V.

0.7V

0.5V

Ids

3.4 Thermal Shutdown (TSD) : The Sense FET and the

control IC are built in one package. This makes it easy for

the control IC to detect the heat generation from the Sense

FET. When the temperature exceeds approximately 150°C,

the thermal shutdown is activated.

Vds

time

4. Soft Start : The FPS^TMhas an internal soft start circuit

that increases PWM comparator inverting input voltage

together with the Sense FET current slowly after it starts up.

The typical soft start time is 10msec, The pulse width to the

power switching device is progressively increased to

establish the correct working conditions for transformers,

inductors, and capacitors. The voltage on the output

capacitors is progressively increased with the intention of

smoothly establishing the required output voltage. It also

helps to prevent transformer saturation and reduce the stress

on the secondary diode during startup.

Switching

disabled

Switching

disabled

T2 T3

Figure 9. Waveforms of burst operation

5. Burst operation : In order to minimize power dissipation

in standby mode, the FPS^TMenters burst mode operation.

As the load decreases, the feedback voltage decreases. As

shown in figure 9, the device automatically enters burst

mode when the feedback voltage drops below

V (500mV). At this point switching stops and the

BURL

output voltages start to drop at a rate dependent on standby

current load. This causes the feedback voltage to rise. Once

it passes V (700mV) switching resumes. The feedback

BURH

voltage then falls and the process repeats. Burst mode

operation alternately enables and disables switching of the

power Sense FET thereby reducing switching loss in

Standby mode.

FSDM07652R

Typical application circuit

Application

Output power

40W

Input voltage

Universal input

(85-265Vac)

Output voltage (Max current)

5V (2.0A)

LCD Monitor

12V (2.5A)

Features

• High efficiency (>81% at 85Vac input)

• Low zero load power consumption (<300mW at 240Vac input)

• Low standby mode power consumption (<800mW at 240Vac input and 0.3W load)

• Low component count

• Enhanced system reliability through various protection functions

• Internal soft-start (10ms)

Key Design Notes

• Resistors R102 and R105 are employed to prevent start-up at low input voltage. After startup, there is no power loss in these

resistors since the startup pin is internally disconnected after startup.

• The delay time for over load protection is designed to be about 50ms with C106 of 47nF. If a faster triggering of OLP is

required, C106 can be reduced to 10nF.

• Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zener diode

fails and remains short, which causes the fuse (F1) blown and prevents explosion of the opto-coupler (IC301). This zener

diode also increases the immunity against line surge.

1. Schematic

D202

MBRF10100

EER3016

L201

12V, 2.5A

C202

1000uF

25V

C201

1000uF

25V

C104

2.2nF

1kV

R103

56kΩ

R102

D101

C103

100uF

400V

30kΩ

UF 4007

R105

BD101

2KBP06M3N257

40kΩ

IC1

FSDM07652R

Vstr

Drain

Vcc

D201

MBRF1045

L202

5V, 2A

Vfb

ZD102

10V

D102

TVR10G

R104

5Ω

C204

1000uF

10V

GND

C105

22uF

50V

C203

1000uF

10V

C106

47nF

50V

C102

220nF

275VAC

ZD101

22V

C301

4.7nF

LF101

23mH

R201

1kΩ

R101

560kΩ

R204

5.6kΩ

R202

1.2kΩ

R203

12kΩ

C205

47nF

IC301

H11A817A

IC201

KA431

C101

220nF

275VAC

RT1

5D-9

FUSE

250V

R205

5.6kΩ

FSDM07652R

2. Transformer Schematic Diagram

EER3016

N_p/2

N_12V

N_p/2

N_5V

N_a

3.Winding Specification

Pin (s→f)

4 → 5

Wire

0.2^φ× 1

Turns

Winding Method

Center Winding

Insulation: Polyester Tape t = 0.050mm, 2Layers

Np/2 2 → 1

0.4^φ× 1

Insulation: Polyester Tape t = 0.050mm, 2Layers

N12v 10 → 8

0.3^φ× 3

Insulation: Polyester Tape t = 0.050mm, 2Layers

N5v 7 → 6

0.3^φ× 3

Insulation: Polyester Tape t = 0.050mm, 2Layers

Np/2 3 → 2

0.4^φ× 1

Solenoid Winding

Center Winding

Solenoid Winding

Outer Insulation: Polyester Tape t = 0.050mm, 2Layers

4.Electrical Characteristics

Specification

520uH ± 10%

10uH Max

Remarks

100kHz, 1V

2^ndall short

Inductance

1 - 3

Leakage Inductance

5. Core & Bobbin

Core : EER 3016

Bobbin : EER3016

Ae(mm2) : 96

FSDM07652R

6.Demo Circuit Part List

Part

F101

Value

2A/250V

5D-9

Note

Part

Value

Note

Fuse

NTC

C301

4.7nF

Polyester Film Cap.

Inductor

RT101

L201

L202

5uH

Wire 1.2mm

Resistor

R101

R102

R103

R104

R105

R201

R202

R203

R204

R205

560K

30K

56K

1/4W

Diode

40K

D101

D102

UF4007

TVR10G

1.2K

12K

5.6K

D201

MBRF1045

MBRF10100

Zener Diode

D202

ZD101

ZD102

22V

10V

Bridge Diode

BD101 2KBP06M 3N257

Bridge Diode

Capacitor

C101

C102

C103

C104

C105

C106

C201

C202

C203

C204

C205

220nF/275VAC

100uF/400V

2.2nF/1kV

Box Capacitor

Line Filter

Box Capacitor

LF101

23mH

Wire 0.4mm

Electrolytic Capacitor

Ceramic Capacitor

Electrolytic Capacitor

Ceramic Capacitor

Electrolytic Capacitor

Ceramic Capacitor

IC101

IC201

IC301

FSDM07652R

KA431(TL431)

H11A817A

FPS^TM(7A,650V)

Voltage reference

Opto-coupler

22uF/50V

47nF/50V

1000uF/25V

1000uF/10V

47nF/50V

FSDM07652R

7. Layout

Figure 10. Layout Considerations for FSDM07652R

Figure 11. Layout Considerations for FSDM07652R

FSDM07652R

Package Dimensions

TO-220F-6L(Forming)

FSDM07652R

Ordering Information

Product Number

Package

TO-220F-6L(Forming)

Marking Code

BVdss

Rds(on)Max.

1.6 Ω

FSDM07652RWDTU

WDTU : Forming Type

DM07652R

650V

FSDM07652R

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perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

1/12/05 0.0m 001

2005 Fairchild Semiconductor Corporation

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FSDM07652RWDTU [ONSEMI]

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