FSGM300N [ONSEMI]
650V 集成电源开关，带异常 OCP，用于 30W 离线反激转换器;
| 型号： | FSGM300N |
| 厂家： | 
ONSEMI |
| 描述： | 650V 集成电源开关，带异常 OCP，用于 30W 离线反激转换器 开关 电源开关 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FSGM300N
Green-Mode Power Switch
Description
The FSGM300N is an integrated Pulse Width Modulation (PWM)
®
controller and SENSEFET specifically designed for offline
Switch−Mode Power Supplies (SMPS) with minimal external
components. The PWM controller includes an integrated
fixed−frequency oscillator, Under−Voltage Lockout (UVLO),
Leading−Edge Blanking (LEB), optimized gate driver, internal
soft−start, temperature−compensated precise current sources for loop
compensation, and self−protection circuitry. Compared with a discrete
MOSFET and PWM controller solution, the FSGM series can reduce
total cost, component count, size, and weight; while simultaneously
increasing efficiency, productivity, and system reliability. This device
provides a basic platform suited for cost−effective design of a flyback
converter.
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PDIP−8
CASE 626−05
MARKING DIAGRAM
Features
• Advanced Burst−Mode Operation for Low Standby Power
• Random Frequency Fluctuation for Low EMI
• Pulse−by−Pulse Current Limit
$Y&E&Z&2&K
FSGM300N
• Various Protection Functions: Overload Protection (OLP),
Over−Voltage Protection (OVP), Abnormal Over−Current Protection
(AOCP), Internal Thermal Shutdown (TSD) with Hysteresis,
Output−Short Protection (OSP), and Under−Voltage Lockout
(UVLO) with Hysteresis
• Auto−Restart Mode
• Internal Startup Circuit
$Y
&E
&Z
&2
&K
= ON Semiconductor Logo
‘= Designates Space
= Assembly Plant Code
= 2−Digit Date Code Format
= 2−Digit Lot Run Tracebility Code
FSGM300N = Specific Device Code
• Internal High−Voltage SENSEFET: 650 V
• Built−in Soft−Start: 15 ms
• This is a Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Applications
• Power Supply for LCD Monitor, STB and DVD Combination
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
July, 2019 − Rev. 3
FSGM300N/D
FSGM300N
ORDERING INFORMATION
Output Power Table (Note 2)
85 − 265 V
230V ꢀ 15% (Note 3)
AC
AC
Operating
Junction
Temperature
Adapter
(Note 4)
Open Frame
Adapter
Open Frame
Current
Limit
R
Replaces
Device
DS(ON)
(Note 5)
(Note 4)
(Note 5)
Part Number
Package
(Max.)
Shipping
FSGM300N
8−DIP
−40°C ~ +125°C
1.60 A
2.2 W
26 W
40 W
20 W
30 W
FSFM300N 3000 / Tube
1. Pb−free package per JEDEC J−STD−020B.
2. The junction temperature can limit the maximum output power.
3. 230 V or 100 / 115 V with voltage doubler.
AC
AC
4. Typical continuous power in a non−ventilated enclosed adapter measured at 50°C ambient temperature.
5. Maximum practical continuous power in an open−frame design at 50°C ambient temperature.
Application Circuit
VO
AC
IN
VSTR
Drain
N.C.
PWM
GND
VCC
FB
Figure 1. Typical Application Circuit
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2
FSGM300N
Internal Block Diagram
V
STR
V
CC
Drain
5
2
6, 7, 8
ICH
V
burst
0.5 V / 0.7 V
V
ref
VCC good
7.7 V / 12 V
Random
OSC
VCC
V
ref
Soft Start
IDELAY
IFB
S
R
Q
Q
PWM
Gate
Driver
FB
3
4
3R
LEB (400 ns)
R
N.C.
t
< t
OSP
(1.0 ms)
ON
LPF
1
GND
V
AOCP
VOSP
S
R
Q
TSD
V
6SVD
VCC good
Q
V
CC
V
24OVVP
Figure 2. Internal Block Diagram
Pin Configuration
1. GND
2. V
8. Drain
7. Drain
6. Drain
CC
FSGM300N
3. FB
4. NC
5. V
STR
Figure 3. Pin Configuration (Top View)
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3
FSGM300N
PIN DEFINITIONS
Pin No.
Name
Description
1
2
GND
Ground. This pin is the control ground and the SENSEFET source.
V
CC
Power Supply. This pin is the positive supply input, w hich provides the internal operating current for both startup
and steady−state operation.
3
FB
Feedback. This pin is internally connected to the inverting input of the PWM comparator. The collector of an
opto−coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and
GND. If the voltage of this pin reaches 6 V, the overload protection triggers, which shuts down the power switch.
4
5
N.C.
No connection.
V
STR
Startup. This pin is connected directly, or through a resistor, to the high−voltage DC link. At startup, the internal
high−voltage current source supplies internal bias and charges the external capacitor connected to the V pin.
CC
Once V reaches 12 V, the internal current source (I ) is disabled.
CC
CH
6, 7, 8
Drain
SENSEFET Drain. High−voltage power SENSEFET drain connection.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−
Max
650
650
26
Unit
V
V
STR
V
STR
Pin Voltage
V
Drain Pin Voltage
Pin Voltage
−
V
DS
V
CC
V
−
V
CC
V
Feedback Pin Voltage
Drain Current Pulsed
−0.3
−
8.0
4
V
FB
I
A
DM
I
Continuous Switching Drain Current (Note 6)
T
T
= 25°C
−
1.90
1.27
190
1.5
150
+125
+150
−
A
DS
C
= 100°C
−
A
C
E
Single Pulsed Avalanche Energy (Note 7)
−
mJ
W
°C
°C
°C
kV
AS
P
Total Power Dissipation (T = 25°C) (Note 8)
−
D
C
T
Maximum Junction Temperature
Operating Junction Temperature (Note 9)
Storage Temperature
−
J
−40
−55
2
T
STG
ESD
Electrostatic Discharge Capability
Human Body Model, JESD22−A114
Charged Device Model, JESD22−C101
2
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (D
= 0.83) and junction temperature
MAX
(see Figure 4).
7. L = 45 mH, starting T = 25°C.
J
8. Infinite cooling condition (refer to the SEMI G30−88).
9. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
IDS
DMAX
fSW
Figure 4. Repetitive Peak Switching Current
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4
FSGM300N
THERMAL CHARACTERISTICS
Symbol
Characteristic
Value
80
Unit
°C/W
°C/W
°C/W
q
JA
q
JC
Junction−to−Ambient Thermal Impedance (Note 10)
Junction−to−Case Thermal Impedance (Note 11)
Junction−to−Top Thermal Impedance (Note 12)
20
Y
JT
35
10.Infinite cooling condition (refer to the SEMI G30−88).
11. Free standing with no heat−sink under natural convection.
12.Measured on the package top surface.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
SENSEFET SECTION
−
−
−
BV
I
Drain−Source Breakdown Voltage
Zero−Gate−Voltage Drain Current
Drain−Source On−State Resistance
Input Capacitance (Note 13)
Output Capacitance (Note 13)
Rise Time
V
CC
V
DS
V
GS
V
DS
V
DS
V
DS
V
DS
V
DS
V
DS
= 0 V, I = 250 mA
650
V
DSS
D
−
250
mA
= 520 V, T = 125°C
A
DSS
−
−
−
−
−
−
−
R
= 10 V, I = 1 A
1.8
515
75
2.2
W
pF
pF
ns
ns
ns
ns
DS(ON)
D
−
C
= 25 V, V = 0 V, f = 1MHz
GS
ISS
−
−
−
−
−
C
= 25 V, V = 0 V, f = 1MHz
GS
OSS
t
= 325 V, I = 4 A, R = 25 W
26
r
D
G
t
Fall Time
= 325 V, I = 4 A, R = 25 W
25
f
D
G
t
t
Turn−On Delay Time
= 325 V, I = 4 A, R = 25 W
14
d(on)
d(off)
D
G
Turn−Off Delay Time
= 325 V, I = 4 A, R = 25 W
32
D
G
CONTROL SECTION
f
Switching Frequency (Note 13)
Switching Frequency Variation (Note 13)
Maximum Duty Ratio
V
= 14 V, V = 4 V
61
67
5
73
10
83
0
kHz
%
S
CC
FB
−
−25°C < T < 125°C
Df
J
S
D
V
CC
V
CC
V
FB
V
FB
= 14 V, V = 4 V
71
77
%
MAX
FB
−
−
D
Minimum Duty Ratio
= 14 V, V = 0 V
%
MIN
FB
FB
I
Feedback Source Current
UVLO Threshold Voltage
= 0
120
11
150
12
180
13
8.5
mA
V
V
= 0 V, V Sweep
CC
START
V
After Turn−on, V = 0 V
7.0
7.7
V
STOP
FB
−
V
OP
V
CC
Operating Range
13
22.5
V
−
−
t
Internal Soft−Start Time
V
V
= 40 V, V Sweep
15
ms
S/S
STR
CC
BURST−MODE SECTION
Burst−Mode Voltage
V
= 14 V, V Sweep
0.6
0.4
−
0.7
0.5
0.8
0.6
−
V
V
BURH
CC
FB
V
BURL
Hys
200
mV
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5
FSGM300N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
PROTECTION SECTION
I
Peak Drain Current Limit
di/dt = 300 mA/ms
1.44
5.5
2.0
−
1.60
6.0
2.7
400
24.0
1.0
1.6
2.5
135
40
1.76
6.5
3.4
−
A
V
LIM
V
Shutdown Feedback Voltage
Shutdown Delay Current
V
CC
V
CC
= 14 V, V Sweep
FB
SD
DELAY
I
= 14 V, V = 4 V
mA
ns
V
FB
t
Leading−Edge Blanking Time (Note 13, 15)
Over−Voltage Protection
LEB
V
V
CC
Sweep
22.5
0.7
1.4
2.0
125
−
25.5
1.3
1.8
3.0
145
−
OVP
OSP
t
Output Short
Protection (Note 13)
Threshold Time
OSP Triggered when t < t
&
ms
V
ON
OSP
V
t
> V
OSP_FB
(Lasts Longer than
FB
OSP
)
V
Threshold V
OSP
FB
t
V
Blanking Time
ms
°C
°C
OSP_FB
FB
T
Thermal Shutdown Temperature (Note 13)
Shutdown Temperature
Hysteresis
SD
Hys
TOTAL DEVICE SECTION
I
Operating Supply Current, (Control Part in
Burst Mode)
V
V
= 14 V, V = 0 V
1.0
2.1
1.5
2.5
2.0
2.9
mA
mA
mA
OP
CC
FB
I
Operating Switching Current, (Control Part
and SENSEFET Part)
= 14 V, V = 2 V
FB
OPS
CC
I
Start Current
V
V
= 11 V (Before V Reaches
400
500
600
START
CC
START
CC
)
I
Startup Charging Current
V
= V = 0 V, V
= 40 V
Sweep
0.95
1.10
26
1.50
mA
V
CH
CC
FB
STR
−
−
V
STR
Minimum V
Supply Voltage
V
CC
= V = 0 V, V
FB
STR
STR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
13.Although these parameters are guaranteed, they are not 100% tested in production.
14.Average value.
15.t
includes gate turn−on time.
LEB
Table 1. COMPARISON OF FSFM300N AND FSGM300N
Function
FSFM300N
FSGM300N
Advantages of FSFM300N
Random Frequency
Fluctuation
Built−in
Low EMI
Operating Current
Protections
3 mA
1.4 mA
Very low stand−by power
OLP
OVP
AOCP
TSD
OLP
OVP
OSP
AOCP
Enhanced protections and high reliability
TSD with Hysteresis
Power Balance
Long T
Very Short T
The difference of input power between the low and high input
voltage is quite small
CLD
CLD
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FSGM300N
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
−40
−25
0
25
50
75
100
120
−40
−25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 5. Operating Supply Current (IOP) vs. TA
Figure 6. Operating Switching Current (IOPS) vs. TA
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
−40
−25
0
25
50
75
100
125
−40
−25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 7. Startup Charging Current (ICH) vs. TA
Figure 8. Peak Drain Current Limit (ILIM) vs. TA
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
−40
−25
0
25
50
75
100
125
−40
−25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 9. Feedback Source Current (IFB) vs. TA
Figure 10. Shutdown Delay Current (IDELAY) vs. TA
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7
FSGM300N
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
−40
−25
0
25
50
75
100
125
−40
−25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 11. UVLO Threshold Voltage (VSTART) vs. TA
Figure 12. UVLO Threshold Voltage (VSTOP) vs. TA
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
−40
−25
0
25
50
75
100
125
−40
−25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 13. Shutdown Feedback Voltage (VSD) vs. TA
Figure 14. Over−Voltage Protection (VOVP) vs. TA
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
−40
−25
0
25
50
75
100
125
−40
−25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
Figure 15. Switching Frequency (fS) vs. TA
Figure 16. Maximum Duty Ratio (DMAX) vs. TA
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8
FSGM300N
FUNCTIONAL DESCRIPTION
the required output voltage. This helps prevent transformer
saturation and reduces stress on the secondary diode during
startup.
Startup
At startup, an internal high−voltage current source
supplies the internal bias and charges the external capacitor
Feedback Control
(C ) connected to the V pin, as illustrated in Figure 17.
This device employs current−mode control, as show n in
Figure 18. An opto−coupler (such as the FOD817) and shunt
regulator (such as the KA431) are typically used to
implement the feedback network. Comparing the feedback
Vcc
CC
When V reaches 12 V, the FSGM300N begins switching
CC
and the internal high−voltage current source is disabled. The
FSGM300N continues normal switching operation and the
power is supplied from the auxiliary transformer winding
voltage with the voltage across the R
resistor makes it
SENSE
unless V
goes below the stop voltage of 7.7 V.
possible to control the switching duty cycle. When the
reference pin voltage of the shunt regulator exceeds the
internal reference voltage of 2.5 V, the opto−coupler LED
current increases, pulling down the feedback voltage and
reducing drain current. This typically occurs when the input
voltage is increased or the output load is decreased.
CC
VDC
CVcc
Pulse−by−Pulse Current Limit
Because current−mode control is employed, the peak
current through the SENSEFET is limited by the inverting
VCC
VSTR
2
5
input of PWM comparator (V *), as shown in Figure 18.
FB
ICH
Assuming that the 150 mA current source flows only through
the internal resistor (3R + R = 16 kW), the cathode voltage
of diode D2 is about 2.4 V. Since D1 is blocked when the
V
ref
VCC good
feedback voltage (V ) exceeds 2.4 V, the maximum
FB
7.7 V / 12.0 V
Internal
Bias
voltage of the cathode of D2 is clamped at this voltage.
Therefore, the peak value of the current through the
SENSEFET is limited.
Figure 17. Startup Block
Leading−Edge Blanking (LEB)
Soft−Start
At the instant the internal SENSEFET is turned on, a
high−current spike usually occurs through the SENSEFET,
caused by primary−side capacitance and secondary−side
rectifier reverse recovery. Excessive voltage across the
The FSGM300N has an internal soft−start circuit that
increases PWM comparator inverting input voltage,
together with the SENSEFET current, slow ly after it starts.
The typical soft−start time is 15 ms. The pulse width to the
power switching device is progressively increased to
establish the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased to smoothly establish
R
SENSE
resistor leads to incorrect feedback operation in the
current mode PWM control. To counter this effect, the
FSGM300N employs a leading−edge blanking (LEB)
circuit. This circuit inhibits the PWM comparator for t
(400 ns) after the SenseFET is turned on.
LEB
Drain
6, 7, 8
Vref
VCC
IDELAY
IFB
D2
OSC
FB
3R
VOUT
VFB
PWM
4
Gate
Driver
D1
FOD817
KA431
*
CFB
R
VFB
LEB (400 ns)
OSP
OLP
VOSP
RSENSE
GND
1
AOCP
V
AOCP
VSD
Figure 18. Pulse Width Modulation Circuit
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9
FSGM300N
Protection Circuits
current, thus increasing the feedback voltage (V ). If V
FB
FB
The FSGM300N has several self−protective functions,
such as Overload Protection (OLP), Abnormal
Over−Current Protection (AOCP), Output−Short Protection
(OSP), Over−Voltage Protection (OVP), and Thermal
Shutdown (TSD). All the protections are implemented as
auto−restart. Once the fault condition is detected, switching
is terminated and the SENSEFET remains off. This causes
exceeds 2.4 V, D1 is blocked and the 2.7 mA current source
starts to charge C slowly up In this condition, V
continues increasing until it reaches 6.0 V, when the
switching operation is terminated, as show n in Figure 20.
The delay time for shutdown is the time required to charge
FB
.
FB
C
FB
from 2.4 V to 6.0 V with 2.7 mA. A 25 ~ 50 ms delay is
typical for most applications. This protection is
implemented in auto−restart mode.
V
CC
to fall. When V falls to the Under−Voltage Lockout
CC
(UVLO) stop voltage of 7.7 V, the protection is reset and the
startup circuit charges the V capacitor. When V reaches
the start voltage of 12.0 V, the FSGM300N resumes normal
operation. If the fault condition is not removed, the
VFB
CC
CC
Overload Protection
6.0 V
2.4 V
SENSEFET remains off and V drops to stop voltage
CC
again. In this manner, the auto−restart can alternately enable
and disable the switching of the power SENSEFET until the
fault condition is eliminated. Because these protection
circuits are fully integrated into the IC without external
components, the reliability is improved without increasing
cost.
t
12
= C x (6.0 − 2.4) / I
FB delay
t1
t 2
t
Fault
occurs
Fault
removed
Power
on
VDS
Figure 20. Overload Protection
Abnormal Over−Current Protection (AOCP)
When the secondary rectifier diodes or the transformer
pins are shorted, a steep current with extremely high di/dt
can flow through the SENSEFET during the minimum
turn−on time. Even though the FSGM300N has overload
protection, it is not enough to protect the FSGM300N in that
abnormal case; since severe current stress is imposed on the
SENSEFET until OLP is triggered. The FSGM300N
internal AOCP circuit is shown in Figure 21. When the gate
turn−on signal is applied to the power SENSEFET, the
AOCP block is enabled and monitors the current through the
sensing resistor. The voltage across the resistor is compared
with a preset AOCP level. If the sensing resistor voltage is
greater than the AOCP level, the set signal is applied to the
S- R latch, resulting in the shutdown of the SMPS.
VCC
12.0 V
7.5 V
t
Normal
operation
Fault
situation
Normal
operation
Figure 19. Auto−Restart Protection Waveforms
Overload Protection (OLP)
Drain
Overload is defined as the load current exceeding its
normal level due to an unexpected abnormal event. In this
situation, the protection circuit should trigger to protect the
SMPS. However, even when the SMPS is in normal
operation, the overload protection circuit can be triggered
during the load transition. To avoid this undesired operation,
the overload protection circuit is designed to trigger only
after a specified time to determine whether it is a transient
situation or a true overload situation. Because of the
pulse−by−pulse current limit capability, the maximum peak
current through the SENSEFET is limited and, therefore, the
maximum input power is restricted with a given input
voltage. If the output consumes more than this maximum
6, 7, 8
OSC
3R
PWM
Gate
Driver
*
R
VFB
LEB (400 ns)
RSENSE
VAOCP
GND
Q
Q
S
1
R
VCC good
pow er, the output voltage (V
voltage. This reduces the current through the opto−coupler
LED, which also reduces the opto−coupler transistor
) decreases below the set
OUT
Figure 21. Abnormal Over−Current Protection
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10
FSGM300N
Output−Short Protection (OSP)
operation. The FSGM300N operates in auto−restart mode
until the temperature decreases to around 95°C, when
normal operation resumes.
If the output is shorted, steep current with extremely high
di/dt can flow through the SENSEFET during the minimum
turn−on time. Such a steep current brings high−voltage
stress on the drain of the SENSEFET when turned off. To
protect the device from this abnormal condition, OSP is
Soft Burst−Mode Operation
To minimize power dissipation in standby mode, the
FSGM300N enters burst−mode operation. As the load
decreases, the feedback voltage decreases. As shown in
Figure 23, the device automatically enters burst mode when
included. It is comprised of detecting V and SENSEFET
FB
turn−on time. When the V is higher than 1.6 V and the
FB
SENSEFET turn−on time is lower than 1.0 ms, the
FSGM300N recognizes this condition as an abnormal error
and shuts down PWM switching until V reaches V
again. An abnormal condition output short is shown in
Figure 22.
the feedback voltage drops below V
(500 mV). At this
BURL
point, switching stops and the output voltages start to drop
at a rate dependent on standby current load. This causes the
CC
START
feedback voltage to rise. Once it passes V
(700 mV),
BURH
switching resumes. The feedback voltage then falls and the
process repeats. Burst−mode operation alternately enables
and disables switching of the SENSEFET, thereby reducing
switching loss in standby mode.
MOSFET
Drain
Current
Rectifier
Diode
Current
ILIM
* = 0.4 V
V
FB
*
ꢀ V * = 1.6 V
FB
VFB
VO
ILm
0
t
1.0 ms
1.0 ms
tOFF tON
output short occurs
t
VFB
VOUT
IOUT
0
0.70 V
0.50 V
t
t
t
OSP triggered
OSP
IDS
Soft Burst
0
Figure 22. Output−Short Protection
t
Over−Voltage Protection (OVP)
VDS
If the secondary−side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path, the
current through the opto−coupler transistor becomes almost
zero. Then V climbs up in a similar manner to the overload
FB
t
situation, forcing the preset maximum current to be supplied
to the SMPS until the overload protection is triggered.
Because more energy than required is provided to the output,
the output voltage may exceed the rated voltage before the
overload protection is triggered, resulting in the breakdown
of the devices in the secondary side. To prevent this
Switching
disabled
Switching
disabled
t4
t1
t2 t3
Figure 23. Burst−Mode Operation
Random Frequency Fluctuation (RFF)
situation, an OVP circuit is employed. In general, the V
is proportional to the output voltage and the FSGM300N
Fluctuating switching frequency of an SMPS can reduce
EMI by spreading the energy over a wide frequency range.
The amount of EMI reduction is directly related to the
switching frequency variation, which is limited internally.
The switching frequency is determined randomly by
external feedback voltage and internal free−running
oscillator at every switching instant. This Random
Frequency Fluctuation scatters the EMI noise around typical
switching frequency (67 kHz) effectively and can reduce the
cost of the input filter included to meet the EMI
requirements (e.g. EN55022).
CC
uses V instead of directly monitoring the output voltage.
CC
If V exceeds 24.0 V, an OVP circuit is triggered, resulting
CC
in the termination of the switching operation. To avoid
undesired activation of OVP during normal operation, V
CC
should be designed to be below 24.0 V.
Thermal Shutdown (TSD)
The SENSEFET and the control IC on a die in one
package makes it easier for the control IC to detect the over
temperature of the SENSEFET. If the temperature exceeds
~135°C, the thermal shutdown is triggered and stops
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11
FSGM300N
TYPICAL APPLICATION CIRCUIT
I
DS
Table 2. TYPICAL APPLICATION CIRCUIT
f
SW
Application Input Voltage Rated Output Rated Power
Df
SW
t (ms)
LCD Monitor
Power Supply
85 ~ 265 V
5.0 V (2 A)
14.0 V (1.2 A)
26.8 W
AC
f
SW
f
+ 1/2 Df
SW
SW
f
− 1/2 Df
SW
SW
Key Design Notes:
No repetition
1. The delay time for overload protection is designed
to be about 30 ms with C105 (22 nF). OLP time
between 25 ms (18 nF) and 50 ms (39 nF) is
recommended.
t (ms)
Figure 24. Random Frequency Fluctuation
2. The SMD−type capacitor (C106) must be placed
as close as possible to the V pin to avoid
CC
malfunction by abrupt pulsating noises and to
improve ESD and surge immunity. Capacitance
between 100 nF and 220 nF is recommended.
Schematic
L201
5mH
D201
MBRF10H100
T1
EER3016
14V, 1.2A
10
1
2
C201
1000mF
25V
C202
1000mF
25V
R103
C104
3.3nF
630V
R102
68kW
43kW
6
1W
D101
C103
100mF
400V
1N4007
3
2
BD101
2KBP06M
C301
4.7nF
Y2
FSGM300N
VSTR
5
1
6,7,8
3
Drain
C107
47mF
50V
D202
MBRF1060
L202
5mH
C106
220nF
4
3
N.C.
VCC
5V, 2A
2
FB
4
5
7
6
4
D102
UF 4007
GND
C204
1000mF
10V
C203
2200mF
10V
C105
22nF
100V
C102
150nF
275VAC
1
ZD101
1N4750A
LF101
30mH
R201
620W
R101
1.5MW
1W
R204
8kW
R202
1.2kW
C205
47nF
R203
18kW
IC301
FOD817B
IC201
KA431LZ
RT1
NTC
5D−9
F1
C101
220nF
275VAC
FUSE
250V
2A
R205
8kW
Figure 25. Schematic of Demonstration Board
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12
FSGM300N
Transformer
Barrier tape
EER3016
1
10
9
N15V
1
6
Np/2
N14V
N5V
2
2
Np/2
8
10
3
8
7
6
Np/2
8
4
7
3
N5V
N5V
Na
5
6
2
4
5
Na
N5V
Np/2
TOP
BOT
Figure 26. Schematic of Transformer
Winding Specification
Table 3. WINDING SPECIFICATION
Barrier Tape
BOT
TOP
Ts
Pin (S ꢁ F)
3 → 2
Wire
0.25 φ x 1
Turns
Winding Method
N /2
p
21
Solenoid Winding
2.0 mm
1
Insulation: Polyester Tape t = 0.025 mm, 2 Layers
7 → 6
0.4 φ x 2 (TIW)
Insulation: Polyester Tape t = 0.025 mm, 2 Layers
4 → 5
0.2 φ x 1
Insulation: Polyester Tape t = 0.025 mm, 2 Layers
8 → 6
0.4 φ x 2 (TIW)
Insulation: Polyester Tape t = 0.025 mm, 2 Layers
10 → 8
0.4 φ x 2 (TIW)
Insulation: Polyester Tape t = 0.025 mm, 2 Layers
N /2 2 → 1
0.25 φ x 1
N
3
7
Solenoid Winding
Solenoid Winding
Solenoid Winding
Solenoid Winding
Solenoid Winding
3.0 mm
3.0 mm
3.0 mm
2.0 mm
2.0 mm
1
1
1
1
1
5V
N
4.0 mm
a
N
3
5V
N
5
14V
21
p
Insulation: Polyester Tape t = 0.025 mm, 2 Layers
Electrical Characteristics
Table 4. ELECTRICAL CHARACTERISTICS
Pin
Specification
Remark
67 kHz, 1 V
Short All Other Pins
Inductance
Leakage
1 − 3
1 − 3
900 μH 7%
15 mH Maximum
Core & Bobbin
2
• Core: EER3016 (Ae = 109.7 mm )
• Bobbin: EER3016
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13
FSGM300N
Bill of Materials
Table 5. Bill of Materials
Part #
Value
Fuse
250 V 2 A
NTC
5D−9
Resistor
1.5 MW, J
Note
Part #
Value
Capacitor
Note
F101
C101
C102
C103
220 nF / 275 V
150 nF / 275 V
100 mF / 400 V
Box (Pilkor)
Box (Pilkor)
NTC101
DSC
Electrolytic (SamYoung)
C104
C105
C106
3.3 nF / 630 V
27 nF / 100 V
220 nF
Film (Sehwa)
Film (Sehwa)
SMD (2012)
R101
R102
R103
R201
R202
1 W
1/2 W
68 kW, J
43 kW, J
620 W, F
1.2 kW, F
1 W
47 mF / 50 V
1000 mF / 25 V
1000 mF / 25 V
2200 mF / 10 V
C107
C201
C202
C203
Electrolytic (SamYoung)
Electrolytic (SamYoung)
Electrolytic (SamYoung)
Electrolytic (SamYoung)
1/4 W, 1%
1/4 W, 1%
R203
R204
R205
18 kW, F
8 kW, F
1/4 W, 1%
1/4 W, 1%
1/4 W, 1%
1000 mF / 16 V
47 nF / 100 V
4.7 nF / Y2
Inductor
30 mH
8 kW, F
C204
C205
C301
Electrolytic (SamYoung)
Film (Sehwa)
IC
FSGM300N
IC201
FSGM300N
KA431LZ
FOD817B
Diode
ON Semiconductor
ON Semiconductor
ON Semiconductor
Y−cap (Samhwa)
IC301
LF101
L201
L202
Line filter 0.5Ø
5 A Rating
5 mH
D101
D102
1N4007
Vishay
Vishay
5 mH
5 A Rating
UF4007
Transformer
900 mH
ZD101
D201
1N4750
Vishay
T101
MBRF10H100
MBRF1060
2KBP06
ON Semiconductor
ON Semiconductor
Vishay
D202
BD101
SENSEFET is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
E
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
H
8
5
4
E1
1
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 8
c
b2
B
END VIEW
WITH LEADS CONSTRAINED
TOP VIEW
NOTE 5
INCHES
DIM MIN MAX
−−−−
A1 0.015
MILLIMETERS
A2
A
MIN
−−−
0.38
2.92
0.35
MAX
5.33
−−−
4.95
0.56
e/2
A
0.210
−−−−
NOTE 3
A2 0.115 0.195
L
b
b2
C
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
1.52 TYP
0.20
9.02
0.13
7.62
6.10
0.36
10.16
−−−
8.26
7.11
D
SEATING
PLANE
D1 0.005
0.300 0.325
E1 0.240 0.280
−−−−
A1
D1
E
C
M
e
eB
L
0.100 BSC
−−−− 0.430
0.115 0.150
−−−− 10°
2.54 BSC
−−−
2.92
−−−
10.92
3.81
10°
e
eB
8X
b
END VIEW
M
NOTE 6
M
M
M
0.010
C A
B
SIDE VIEW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
XXXXXXXXX
AWL
YYWWG
5. GROUND
6. OUTPUT
7. AUXILIARY
8. V
CC
XXXX = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
PAGE 1 OF 1
ON Semiconductor and
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