FSL518APG [ONSEMI]
高性能 800 V 离线开关，带高电压启动和 SenseFET;
| 型号： | FSL518APG |
| 厂家： | 
ONSEMI |
| 描述： | 高性能 800 V 离线开关，带高电压启动和 SenseFET 开关 |
| 文件： | 总27页 (文件大小：1285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FSL518H, FSL538H,
FSL518A, FSL538A
High Performance Switcher
Integrated with HV Startup
and SENSEFET)
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The FSL5x8 is an integrated peak-current-mode controlled pulse
width modulation (PWM) power switch, specifically designed for
off-line switch-mode power supplies. The PWM controller includes an
advanced soft-start, frequency hopping, optimized gate driver, internal
transconductance amplifier, temperature-compensated precise current
source for loop compensation and enhanced self-protections as well.
Compared to a discrete MOSFET and PWM controller solution, the
FSL5x8 allows to reduce total cost, component count, size, and
weight, while simultaneously increasing efficiency, productivity, and
system reliability. This device provides a basic platform for
cost-effective design of both isolated and non-isolated Flyback
converters.
PDIP−7
CASE 626A
MARKING DIAGRAM
Features
ON
AYWWL
• Integrated Rugged 800 V Super-Junction MOSFET with SENSEFET
Technology
L5x8y
• Built-in HV Current Source for Start-up
• Peak-current-mode Control with Slope Compensation
• AC Line Compensation for Accurate Over Power Protection
• Advanced Soft-start for Low Electrical Stress
• Pulse-by-pulse Current Limit
A
Y
W
WL
L5x8
x
= Plant Code
= 1−digit Year Code
= 1−digit Week Code
= 2−digit Die−Run Code
= Specific Device Code
= Device Option (1 or 3)
= Frequency Option (A or H)
• FSL5x8A: 100 kHz and FSL5x8H: 130 kHz
• Line Brown-in, Brown-out Function
• Line Over-voltage Protection (LOVP)
• Adjustable Burst−mode Operation
y
• Frequency Hopping for Low EMI
PIN CONNECTIONS
• All Protections are Auto-Recovery: Brown-out, OLP, OVP, AOCP
and TSD
GND 1
VCC 2
8 DRAIN
7 DRAIN
• These Devices are Pb-Free, Halogen Free/BFR Free and RoHS
Compliant
Typical Applications
• Power Supplies for White Goods
• Industrial Auxiliary Power Supply, E-metering SMPS
• Consumer Electronics (Chargers, Set-top-boxes and TVs)
FB 3
COMP 4
5 LINE
ORDERING INFORMATION
See detailed ordering and shipping information on page 25 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
July, 2019 − Rev. 2
FSL538HR/D
FSL518H, FSL538H, FSL518A, FSL538A
PRODUCT INFORMATION & INDICATIVE RECOMMENDED OUTPUT POWER
Output Power Table (Open Frame) (Notes 1, 2)
Operating
Junction
Temperature
230 V
+
85 ~ 265
Part
Operation
Frequency
AC
15%
V
AC
Number
Current Limit (A) Max. R
(W)
Package
PDIP−7
PDIP−7
PDIP−7
PDIP−7
DS(ON)
FSL518H
FSL538H
FSL518A
FSL538A
−40 ~ 125°C
−40 ~ 125°C
−40 ~ 125°C
−40 ~ 125°C
130 kHz
130 kHz
100 kHz
100 kHz
0.46
0.66
0.61
0.86
8.0
15 W
21 W
17 W
25 W
12 W
17 W
14 W
20 W
4.6
8.0
4.6
1. The junction temperature can limit the maximum output power.
2. Maximum practical continuous power in an open-frame design at 50°C ambient.
Vo
AC
IN
LINE
DRAIN
FB
PWM
GND
VCC
COMP
(a) Isolated Opto−coupler Feedback (Enable Line Detection)
Vo
AC
IN
LINE
DRAIN
COMP
PWM
GND
VCC
FB
(b) Non−isolated Direct Feedback (Disable Line Detection)
Figure 1. Application Schematic − Isolated or Non-isolated Flyback Converter
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2
FSL518H, FSL538H, FSL518A, FSL538A
LINE
DRAIN
VCC
Brown out
−
Initial Setting and
Line Detection
VCC good
VCC Supply
HV Current
Source
V
CC−START/ STOP
VBURH/L
LOVP
VCOMP
Frequency
Reduction
OSC
VLIMIT
Soft
Start
Q
Q
S
R
E/A
PWM
FB
Gate Driver
3R
VREF
R
LEB
Slope
Compensation
S
COMP
AOCP
Logic
RSENSE
AOCP
V
Brown−out
tD− OLP
tBO
Protection
S
Q
Q
V
OLP
TSD
R
VCC good
V
CC
V
−
CC OVP
GND
Figure 2. Internal Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
GND
Pin Function
Ground
Description
SENSEFET source terminal and internal controller ground.
1
2
VCC
Power Supply
This pin is connected to an external capacitor and provides internal operating current of
the IC. It also includes an auto-recovery over-voltage protection.
This pin is connected to the input of transconductance amplifier for regulating output volt-
age of the power converter. If transconductance amplifier is not used, connect FB to
GND.
3
FB
Feedback
4
5
COMP
LINE
Feedback-Loop
Compensation
Control-loop compensation. For opto-coupler feedback, connect COMP to opto coupler
directly.
Brown in/out, LOVP, For line detection(Line OVP, Brown in/out), this pin needs to be connected to the high-
Burst-mode Setting voltage DC link through voltage divider. And it’s also multiple-function pin for burst−mode
adjustment.
7,8
DRAIN
MOSFET Drain
High-voltage power MOSFET drain connection. In addition, during startup and protection
mode, the internal high-voltage current source supplies internal bias current and charges
the external capacitor connected to the VCC pin.
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3
FSL518H, FSL538H, FSL518A, FSL538A
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
DRAIN Pin Voltage
V
−0.3 to 800
−0.3 to 26
−0.3 to 5.0
−0.3 to 5.0
DS
CC
VCC Pin Voltage
V
V
Feedback Pin Voltage
Compensation Pin Voltage
Line-detection Pin Voltage
V
FB
V
V
COMP
V
V
LINE
−0.3 to V
V
CC
DRAIN Pin Pulsed Current (Note 3)
FSL518H/A
FSL538H/A
I
A
D-PULSE
2.1
2.8
Single Pulse Avalanche Energy (Note 4)
FSL518H/A
EAS
mJ
W
6.0
FSL538H/A
11.7
Total Power Dissipation (PDIP−7)
FSL518H/A & FSL538H/A
P
D
1.25
150
Junction Temperature (Note 5)
Operating Junction Temperature (Note 6)
Storage Temperature
T
T
°C
°C
°C
J
−40 to +125
−55 to +150
J
T
STG
ESD Capability HBM, JESD22−A114
ESD Capability HBM, JESD22−A114 (Except DRAIN pin)
1000
2000
V
ESD Capability CDM, JESD22−C101
1000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty and junction temperature.
4. L= 45 mH, starting T = 25°C.
J
5. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics
6. Junction temperature can limit maximum output power of power converter controlled by the device.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, PDIP−7
°C/W
Thermal Resistance, Junction-to-Air (Note 7)
FSL518H/A & FSL538H/A
R
100
18
q
JA
Thermal Reference, Junction-to-Lead (Note 7)
FSL518H/A & FSL538H/A
R
y
JL
7. JEDEC recommended environment, JESD51−2, and test board, JESD51−3, with minimum land pattern.
ELECTRICAL CHARACTERISTICS
T = −40 to +125°C and V = 14 V unless otherwise specified.
J
CC
Parameter
SENSEFET Section
Test Conditions
Symbol
Min
Typ
Max
Unit
MOSFET Peak Current Limit
T = 25°C, Duty = 60%
I
mA
J
LIM
di/dt = 100 mA/ms FSL518H
di/dt = 100 mA/ms FSL518A
di/dt = 143 mA/ms FSL538H
di/dt = 143 mA/ms FSL538A
428
560
614
790
460
610
660
860
492
660
706
930
Drain-to-Source On-State Resistance
Output Capacitance (Note 9)
MOSFET ON, T = 25°C
R
Ω
J
DS(ON)
FSL518H/A, I
FSL538H/A, I
= 0.46 A
= 0.66 A
6.3
3.8
8.0
4.6
DRAIN
DRAIN
V
J
= 480 V, V = 0 V, f = 1 MHz,
C
OSS
pF
DS
GS
T = 25°C
FSL518H/A
FSL538H/A
3.8
5.0
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4
FSL518H, FSL538H, FSL518A, FSL538A
ELECTRICAL CHARACTERISTICS (continued)
T = −40 to +125°C and V = 14 V unless otherwise specified.
J
CC
Parameter
SENSEFET Section
Test Conditions
Symbol
Min
Typ
Max
Unit
Effective Output Capacitance (Note 9)
DRAIN Voltage Rise Time (Note 8)
DRAIN Voltage Fall Time (Note 8)
V
V
= 0 to 480 V, V = 0 V, T = 25°C
C
OSS(eff)
pF
DS
GS
J
FSL518H/A
31
40
FSL538H/A
= 40 V to 360 V
DRAIN
t
r
ns
ns
FSL518H/A, I
FSL538H/A, I
= 0.4 A
= 0.6 A
26
35
DRAIN
DRAIN
V
DRAIN
= 360 V to 40 V
t
f
FSL518H/A, I
FSL538H/A, I
= 0.4 A
= 0.6 A
34
30
DRAIN
DRAIN
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
= 0 V, I = 250 mA, T = 25°C
BV
DSS
800
V
GS
D
J
25
250
V
V
= 800 V, V = 0 V, T = 25°C
GS J
DS
I
mA
DSS
= 640 V, V = 0 V, T = 125°C
DS
GS
J
VCC Section
Controller Turn-on Threshold Voltage
V
15
7
16
8
17
9
V
V
CC-START
Under-voltage Lockout Threshold
Voltage
V
CC-STOP
V
Regulation Voltage
During Protection, T = 25°C
V
9
7
10
800
10
11
13
V
CC
J
CC-HVREG
Restart Time in Protection Mode (Note 9)
Soft-start Time
t
ms
ms
AR
t
SS
Oscillation Section
Switching Frequency
V
CC
= 14 V, V
= 3.6 V, T = 25°C
f
S
kHz
COMP
J
FSL5x8H
FSL5x8A
122
94
130
100
138
106
Switching Frequency Variation
Frequency Modulation Range
T = −40 ~ 125°C
Δf
5
10
%
J
S
V
COMP
= 3.6 V
f
M
kHz
FSL5x8H
FSL5x8A
6.2
4.8
Frequency Modulation Period (Note 9)
Green-mode Entry Frequency
V
V
= 3.6 V
T
3.2
ms
COMP
FM
= 1.4 V
FSL5x8H
FSL5x8A
f
kHz
COMP
N
115
89
Green-mode Ending Frequency
Frequency-limiting Voltage
V
BURL
= 0.4 V
f
22
25
28
kHz
V
G
V
V
OLP
COMP-S
COMP-N
COMP-G
Green-mode Entry COMP Voltage (Note 9)
Green-mode Ending COMP Voltage
Burst-Mode Section
V
V
1.4
V
V
V
BURL
0.35
0.45
0.55
0.4
0.5
0.6
0.45
0.55
0.65
V
V
V
COMP Threshold Voltage for Entering
Burst−mode when Line Detection is
Enabled
VLINE in VLINE-SET0 during tSET
VLINE in VLINE-SET1 during tSET
VLINE in VLINE-SET2 during tSET
V
BURL
BURL
BURH
COMP Threshold Voltage for Entering
Burst−mode when Line Detection is
Disabled
0.9 V < V
1.2 V < V
< 1.2 V
< 3.6 V
V
0.4
LINE
LINE
AV-BURST × VLINE
COMP Threshold Voltage for Leaving
Burst−mode
V
V
+ 0.1
BURL
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FSL518H, FSL538H, FSL518A, FSL538A
ELECTRICAL CHARACTERISTICS (continued)
T = −40 to +125°C and V = 14 V unless otherwise specified.
J
CC
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Control Section
Maximum Duty Ratio
V
= 3.6 V
D
68
75
5
82
%
V
COMP
MAX
COMP Output High Voltage
COMP−pin Open
V
COMP-
OPEN
COMP Sourcing Current
I
70
100
300
135
mA
mS
COMP
Transconductance of Internal Error
Amplifier
G
M
Current-sourcing capability of Internal
Error Amplifier
V
V
= V
= V
− 1 V
I
GM-SOURCE
55
90
125
−125
2.55
mA
mA
V
FB
REF
Current-sinking capability of Internal
Error Amplifier
+ 1 V
I
−55
2.45
−90
2.5
FB
REF
GM-SINK
Reference Voltage to Regulate FB-pin
Voltage
V
REF
LEB
Leading-edge Blanking Time of Internal
SENSEFET Current Signal (Note 9)
t
250
100
ns
ns
Propagation Delay of Turning-off Power
MOSFET (Note 9)
t
PD
LINE Section
0.15
V
V
Threshold Voltage for Line Detection
Enable
V
V
> V
< V
V
LINE
LINE-DET
LINE-DET
0.05
Threshold Voltage for Line Detection
Disable
V
LINE-ADJ
LINE
LINE-ADJ
Burst-mode Level Setting Time when Line
Detection is Enabled (Note 9)
t
I
100
2.7
ms
SET
SET
Sourcing Current for Detecting Burst
During t , V = 15 V, V
= 10 V
1.6
3.8
mA
SET CC
LINE
Setting Zener Voltage in t
SET
Burst-mode Level 0 Set up Voltage
Burst-mode Level 1 Set up Voltage
Burst-mode Level 2 Set up Voltage
During t
During t
During t
V
V
V
12.4
9.3
V
V
SET
SET
SET
LINE-SET0
LINE-SET1
LINE-SET2
10.6
7.9
V
9.4
10
10.6
mA
Sourcing Current for Setting Burst-mode
Level when Line Detection is Disabled
V
V
= 0 V before V is charged to
I
BURST
LINE
CC-START
CC
A
1/3
V/V
LINE-pin Voltage to Burst-mode Level
Attenuation when Line Detection is
Disabled (Note 9)
V-BURST
Protections: Over-Voltage Protection (OVP)
Over-Voltage Protection Threshold Voltage
V
23.0
24.5
6.0
26.0
V
CC-OVP
for VCC−pin
Delay time for OVP (Note 9)
t
ms
D-OVP
Protections: Over-Load Protection (OLP)
OLP-Triggering Threshold Voltage on
V
3.3
30
3.6
60
3.9
90
V
OLP
COMP−pin
Delay Time for OLP
V
COMP
> V
after Soft-start Time
t
D-OLP
ms
OLP
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FSL518H, FSL538H, FSL518A, FSL538A
ELECTRICAL CHARACTERISTICS (continued)
T = −40 to +125°C and V = 14 V unless otherwise specified.
J
CC
Parameter
Abnormal Over-Current Protection (AOCP)
Test Conditions
Symbol
Min
Typ
Max
Unit
AOCP Monitoring duration after t
(Note 9)
t
I
150
ns
LEB
AOCP
Threshold Drain Current for Triggering
AOCP (Note 9)
I
mA
AOCP
LIM
N
2
times
Number of pulse for AOCP to skip
AOCP-TRIG
switching operation for N
(Note 9)
times
AOCP-HALT
Number of skipped pulses after
is satisfied (Note 9)
N
7
3
times
times
AOCP-HALT
N
AOCP-TRIG
Number of Pulse for Satisfying N
to Trigger Auto-restart Protection (Note 9)
N
AOCP-TRIG
AOCP-
COUNT
Protections: Line Detection (BI, BO, LOVP)
Brown-out (BO) Threshold Voltage on
V
0.80
0.95
0.09
0.85
1
0.90
1.05
0.21
V
V
V
LINE-BO
LINE−pin
Brown-in (BI) Threshold Voltage on
LINE−pin
V
LINE-BI
Hysteresis between BI and BO
V
− V
DV
0.15
LINE-BI
LINE-BO
LINE-
BIBO
Delay Time for Brown−out (Note 9)
t
100
4.5
ms
V
BO
Threshold Voltage for Line Over−Voltage
Protection (LOVP)
V
4.3
4.2
4.7
4.6
LINE-OVP
Recovering Level for LOVP
V
4.4
V
LINE-OVP-
RECOVER
Hysteresis Voltage for LOVP
Delay Time for LOVP (Note 9)
Protections: Thermal Shutdown
V
− V
DV
0.05
0.1
2
0.15
V
LINE-OVP
LINE-OVP-RECOVER
LINE-OVP
t
ms
LINE-OVP
Junction Temperature to Trigger Thermal
Shutdown (Note 9)
T
147
95
°C
°C
SD
Junction Temperature for Resuming from
Thermal Shutdown (Note 9)
T
RECOVER
Total Device Section
Operating Supply Current
V
= 0 V, V
= 12 V,
I
I
0.9
1.2
mA
COMP
DRAIN
DRAIN
OP1
(Control Part in Burst−mode)
R
= 500 W
Operating Supply Current
V
COMP
= 3.2 V, V
= 12 V
1.7
2.0
mA
DRAIN
OP2
VCC-pin current at startup condition
V
= 14.9 V, V
= 3.6 V
CC-START
I
170
205
mA
CC
COMP
START
(Before V Reaches V
)
CC
Startup Charging Current
(JFET saturation current)
V
= 0 V, V
= 40 V
I
CH
1.2
4
mA
V
CC
DRAIN
Minimum DRAIN-pin Voltage to Start
Operation (Note 10)
V
CC
= V
= 0 V
V
40
COMP
START
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Evaluated in the typical flyback application board, T = 25°C
A
9. This parameter is not tested in production, but verified by design/characterization.
10.It is guaranteed that I can charge V up to V
if DRAIN-pin voltage is higher than V
.
CH
CC
CC-START
START
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 3. VCC-START vs. Temperature
Figure 4. VCC-STOP vs. Temperature
Figure 5. VCC-HVREG vs. Temperature
Figure 6. ICH vs. Temperature
Figure 7. FSL5x8H IOP1 vs. Temperature
Figure 8. FSL5x8H IOP2 vs. Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 9. FSL5x8A IOP1 vs. Temperature
Figure 10. FSL5x8A IOP2 vs. Temperature
Figure 11. FSL5x8H fs vs. Temperature
Figure 12. FSL5x8A fs vs. Temperature
Figure 13. FSL518H ILIM (Normalized to 255C) vs.
Figure 14. FSL518A ILIM (Normalized to 255C) vs.
Temperature
Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 15. FSL538H ILIM (Normalized to 255C) vs.
Figure 16. FSL538A ILIM (Normalized to 255C) vs.
Temperature
Temperature
Figure 17. ICOMP vs. Temperature
Figure 18. GM vs. Temperature
Figure 19. IGM vs. Temperature
Figure 20. VREF vs. Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 21. VBURL vs. Temperature
Figure 22. VBURH vs. Temperature
Figure 23. VLINE-OVP vs. Temperature
Figure 24. IBURST vs. Temperature
Figure 25. FSL518H/A RDS(ON) vs. Temperature
Figure 26. FSL538H/A RDS(ON) vs. Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 27. FSL518H/A COSS vs. VDRAIN
Figure 28. FSL538H/A COSS vs. VDRAIN
Figure 30. FSL538H/A Safe Operating Range
Figure 32. FSL538H/A BVDSS vs. Temperature
Figure 29. FSL518H/A Safe Operating Range
Figure 31. FSL518H/A BVDSS vs. Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 33. FSL5x8H/A Power Dissipation vs.
Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
APPLICATION INFORMATION
HV Current Source for VCC Start up and
CC Regulation
V
The HV current source utilizes voltage on DRAIN pin to
V
CC
regulation also helps avoiding start-up failure during
charge capacitor on VCC pin. This current source is
activated during start-up and provides operating current
soft-start and keeps FSL5x8 operating to count auto-restart
delay time (t ) in protection mode, as illustrated in Figure
AR
when V
is lower than V
. Thanks to V
34. It also enables the use of smaller capacitance for V
CC
CC-HVREG
CC
CC
start-up function, no external start-up circuitry is needed.
The HV current source is disabled when V voltage is
biasing. The V
external bias is higher than V
regulation is not functional when the
CC
.
CC
CC-HVREG
charged to V
.
CC-START
DRAIN
VCC
HV Current
Source
VCC−START/STOP
VCC
Regulation
tAR
Figure 34. VCC Start Up and VCC Regulation
Initial Setting for Line Detection and Adjusting
Burst-mode Operation
noise, connecting a ceramic capacitor to LINE pin is
recommended.
LINE pin is used for both input-voltage detection and
burst-mode setting. When a voltage divider is connected
between bulk capacitor and LINE pin, a Zener diode
connected to LINE pin will allow to set level of burst-mode
operation. If there is no voltage divider, the line-detection
function is disabled and burst-mode operation level is set
linearly by simply connecting a resistor between LINE pin
and GND pin. In order to avoid interference from switching
When line detection is enabled, voltage on LINE pin is
monitored to offer brown-in (BI), brown-out (BO) and line
over-voltage protections (LOVP).
With I
, V
reflects resistance of the external
BURST
LINE
resistor. FSL5x8 adjusts burst-mode operation threshold
based on real-time V level. Please refer to burst
LINE
threshold setting table for LINE pin configuration and
settings.
VBULK
•
•
•
Input Voltage Detection
Brown−in/out Function
LINE
Setting Burst Threshold by
Zener
VZ
LINE
RBURST
•
Setting Burst Threshold by
Resistance
IBURST
Figure 35. Architecture of LINE-pin Setting
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FSL518H, FSL538H, FSL518A, FSL538A
BURST THRESHOLD SETTING TABLE
Line Detection Enable/Disable
Enable
V
(V)
V
/V
(V)
LINE
BURH BURL
12.4 V < V
0.5 / 0.4
0.6 / 0.5
0.7 / 0.6
0.5 / 0.4
Z
Architecture A
Architecture B
9.3 V < V < 10.6 V
Z
V
Z
< 7.9 V
0.9 V < I
1.2 V < I
× R
< 1.2 V
< 3.6 V
BURST
BURST
Disable
A
× (I
× R
) + 0.1
V-BURST
BURST
BURST
× R
BURST
BURST
/A
× (I
× R
)
V-BURST
BURST
BURST
Initial Setting for Configuration of Feedback
Regulation
Being simultaneous to the initial setting of LINE-pin
functions, configuration of feedback regulation is also
decided based on peripheral circuitry to FB pin. If a voltage
divider is connected to FB pin, the IC will regulate output
In the case that external error amplifier is used for output
regulation, simply connect FB pin to GND pin. The external
output regulation circuitry will sinks I
(100 mA) to
COMP
control PWM duty cycle for accuracy output regulation.
voltage by referring to the reference voltage, V
transconductance error amplifier.
of
REF
Controller
Controller
VCOMP OPEN
−
VOUT
FB
VOUT
ICOMP
E/A
FB
COMP
IGM−SOURCE
VREF
IGM SINK
−
COMP
(a) Isolated Application
(b) Non − Isolated Application
Figure 36. Isolated vs. Non-Isolated Application
Advanced Soft-Start Operation
After V is charged to V
and all settings about
frequency limits are settled to target value gradually as
shown in Fig. 37. Thus, output voltage will be increased
smoothly and the voltage stresses in switching devices can
be minimized.
CC
CC-START
LINE-pin and FB-pin functions are done, switching
operation can be initiated with a soft-start period. For
soft−start period of 10 ms, both drain current and switching
www.onsemi.com
15
FSL518H, FSL538H, FSL518A, FSL538A
Pull high (5 V)
1.25 ms
IDRAIN
ILIM
VCOMP
VSS− LIMIT
Drain Current
8 Steps
t
Figure 37. Soft-start Operation
Main Control Frequency Reduction
Operating frequency of switching operation is
synchronized with COMP-pin voltage, V
comparing drain peak current and V
. The V
can
COMP
COMP
be controlled by either the input signal of error amplifier or
the signal delivered via opto−coupler and feedback loop for
output regulation.
. When
COMP
V
COMP
drops, operating frequency will also decrease. This
helps reducing switching losses and thus improve light-load
efficiency operation. The operating frequency will not be
decreased below 22-kHz so acoustic noise can be avoided.
Slope Compensation
Built-in slope compensation is added into the PWM
procedure when duty cycle is higher than 45%. It helps to
avoid sub-harmonic oscillation of peak-current control.
PWM Control
The FSL5x8 operates with peak−current mode to regulate
output voltage. The duty cycle of PWM is determined by
VSENSE
t
VSLOPE
45%Duty
45%Duty
t
t
VSENSE+COMP
Figure 38. Slope Compensation
Burst−mode Operation
As loading of the power converter decreases, V
into burst−mode. In burst−mode, switching operation is
halted when V is lower than V and resumed when
COMP
COMP
BURL
decreases, thus reducing switching frequency of the
oscillator. When minimum operating frequency is reached,
to further reduce delivered output power, the device goes
V
is higher than V
. By skipping un-needed
COMP
BURH
switching cycles, the FSL5x8 drastically reduced the power
wasted during light load conditions.
www.onsemi.com
16
FSL518H, FSL538H, FSL518A, FSL538A
VO
VCOMP
t
t
t
VBURH
VBURL
IDS
PWM
disabled
PWM
disabled
Figure 39. Burst−mode Behavior
Protections
Over Load Protection (OLP)
V
and V
can be adjusted LINE-pin voltage
BURL
BURH
detected. It is provided for tuning light load efficiency and
acoustic noise. By adjusting V , minimum peak value
of drain current of each switching cycle is adjusted as
described in Equation 1.
V
COMP
will be pulled higher than V
when drain
OLP
BURL
current hits current limit and switching frequency operates
at its highest range. If the condition continues for t
OLP will be triggered and switching operation is stopped as
shown in Fig. 40.
The figure also shows typical protection mode behavior of
the IC. The operation current is supplied by HV current
,
D-OLP
VBURL
4 @ 0.6
IDRAIN.PEAK.BURL
+
@ ILIM
(eq. 1)
Line Compensation
source for t that can extend the restart period to reduce
AR
Propagation delay in turning off power MOSFET makes
drain current exceed current limit by an amount that related
to slope of drain current. The device adjusts its internal
current-limit reference voltage according to duty cycle to
compensate the effect of propagation delay. As a result, the
delivered output power is kept under control across different
input voltage conditions.
average power dissipation when fault is still present. After
t
V
drops to V
to reset protective operation
AR, CC
CC-STOP
and then, controller will be restarted.
www.onsemi.com
17
FSL518H, FSL538H, FSL518A, FSL538A
VCOMP
VOLP
tD
−
OLP
t
t
IDRAIN
ILIM
VCC
VCC
−
HVREG
VCC−STOP
tAR
Protection
t
t
Figure 40. Timing Chart of OLP
Over Voltage Protection (OVP)
A malfunction of voltage-feedback circuitry for output
regulation in power converter could result in excessive
energy delivered to output. In this condition, both output
OVP will be triggered after delay time t
when V
D−OVP CC
rises above V
.
CC−OVP
voltage and V can be increased by unstable operation, and
CC
Fault
IDRAIN
Vcc
t
VCC
−
OVP
tD
−
OVP
VCC −
HVREG
VCC
−
STOP
tAR
Protection
t
t
Figure 41. Timing Chart of OVP
Abnormal Over-Current Protection (AOCP)
limited leading-edge time duration t
+ t
of each
LEB
AOCP
When the secondary-side rectifier diodes or the
transformer windings are shorted, a steep drain current with
extremely high di/dt will flow through the MOSFET during
the minimum turn-on time. Under this condition, each
switching cycle generates very high current stress on power
MOSFET. The controller monitors drain current within a
switching cycle. If drain current exceeds current limit for a
few consecutive switching cycles, N , switching
AOCP-TRIG
will be stopped for number of pulses, N . If the
AOCP-HALT
fault condition is met for three times, N , the
AOCP-COUNT
controller goes into protection mode as shown in Fig. 42.
www.onsemi.com
18
FSL518H, FSL538H, FSL518A, FSL538A
IDRAIN
3
1
2
ILIM
Stop
Stop
Protection
switching
switching
+
tLEB
FSL5x8H: 1 pulse
FSL5x8A: 2 pulses
t
AOCP
t
VCC
tAR
V
−
CC
HVREG
V
CC −STOP
t
Figure 42. Timing Chart of AOCP
Brown−in, Brown−out (BI/BO) and Line Over-Voltage
Protection (LOVP)
When a voltage divider is connected between LINE pin
and input bulk capacitor, line-detection function is enabled
lower than V
for t
during normal operation,
BO
LINE-BO
brown-out will be triggered and the controller will go into
protection mode. If V is higher than V
switching operation is halted until V
,
LINE-OVP
LINE
drops down below
LINE
and V
reflects peak of AC input voltage. If V
is
LINE
LINE
V
. Both recovering from LOVP or after
LINE-OVP-RECOVER
below V
after initial setting, switching operation will
LINE-BI
BI, the controller performs a soft start sequence.
not be initiated until V
reaches V
. If V
is
LINE
LINE-BI
LINE
VBULK
tSET
tSET
t
VLINE
V
LINE−
OVP
VLINE OVP
−
−
RECOVER
VLINE−BI
VLINE
−BO
t
IDRAIN
tLINE−OVP
tSS
tSS
tBO
tBO
t
VCC
VCC
−
HVREG
tAR
tAR
t
Figure 43. LOVP, Brown-out and Brown-in Behavior
Thermal Shutdown (TSD)
exceeds shut-down temperature, T , thermal shutdown is
SD
Since SENSEFET and controller are integrated in the
same package, it is easier for the controller to detect
temperature inside the package. When junction temperature
activated. The controller will go into protection mode after
thermal shutdown. If temperature is not lower than
T
, switching operation will not be resumed.
RECOVER
www.onsemi.com
19
FSL518H, FSL538H, FSL518A, FSL538A
TJ
TSD
TRECOVER
IDRAIN
t
tSS
VCC
t
t
tAR
V
CC
−
HVREG
Figure 44. Timing Chart of TSD
www.onsemi.com
20
FSL518H, FSL538H, FSL518A, FSL538A
DESIGN CONSIDERATIONS
Peripheral Components
VBULK
RLINE-upper
While designing flyback converters using FSL5x8H/A,
there are some design considerations on selecting value and
rating of components and PCB (Printed Circuit Board)
layout as the following.
LINE
• Input/Output Capacitor
It is typical to select the input capacitor as 2~3 mF per
watt of peak input power for universal input range
RLINE-lower
CLINE−F
(85−265 V ) and 1 mF per watt of peak input power for
RMS
European high input voltage range (195−265 V
).
RMS
The minimum DC link voltage is obtained as:
Figure 45. LINE Pin Settle for BI/BO/LOVP
2
ǒ
Ǔ
Pin @ 1 * Dch
+ Ǹ
2 @ ǒ
Ǔ
VDC
Vline
*
,
(eq. 2)
min
min
fL @ CDC
Brown−in AC Voltage +
where D is the DC link capacitor charging duty ratio
ch
(eq. 5)
RLINE−upper ) RLINE−lower
1
which is typically about 0.2. f is line voltage frequency.
L
VLINE−BI
Ǹ
RLINE−lower
Line OVP AC Voltage +
Considering the output voltage ripple, capacitance at
the output terminal can be determined as the following.
For better voltage ripple at output terminal, low ESR
(Effective Series Resistance) type capacitor is
recommended.
2
(eq. 6)
(eq. 7)
RLINE−upper ) RLINE−lower
1
Ǹ
VLINE−OVP
RLINE−lower
2
0.25 @ IOUT
3
CLINE−F
+ ǒ
Ǔ
COUT
+
,
(eq. 3)
VOUT*ripple @ fmin
RLINE−upperńńRLINE−lower @ fSW
where I
is a max output load current, V
is
OUT
OUT-ripple
• Selecting FB/COMP and Consideration when One of
Both is Selected
deviation of a ripple voltage and f
freqeuncy between operating frequency deviation.
should minimum
min
For non-isolated converters, connects the output
voltage divider to FB pin. For isolated converters, FB pin
should be connected to GND, and the external feedback
circuit should connect to COMP as well.
• V Capacitance
CC
FSL5x8 includes HV start-up circuit providing startup
current, which determine startup time. It can be calculated
with I and V capacitance. The typical value of V
capacitor is selected in a range of 10 to 47 mF. It is
CH
CC
CC
• Preventing Audible Noise
Even though the switching frequency of the FSL5x8 is
above the range of human hearing, audible noise can be
generated during transient or burst operation. In most
flyback converters, the major noise sources are
transformers and capacitors. Transformers produce
audible noise, since they contain many physically
movable elements, such as coils, isolation tapes and
bobbins. The most effective way to reduce the audible
noise in the transformer is to remove the possibility of
physical movement of the transformer elements by using
adhesive material or by varnishing.
Ceramic capacitors can also produce audible noise,
because of their piezoelectric characteristics. By
replacing the ceramic capacitor with a film capacitor, the
audible noise can be reduced. Another way to lower
audible noise is to reduce the snubber capacitor value,
recommended that V capacitor and FSL5x8 should be
placed as close as possible to reject noise decoupling.
CC
CVCC @ VCC*START
Start−up Time +
,
(eq. 4)
ICH
• Consideration on Designing BI/BO/LOVP
Line input voltage can be detected for brown-in (BI),
brown-out (BO) and input line over-voltage protection
(LOVP) by connecting LINE pin with dividing resisters
linking to input bulk capacitor. Each level of BI and
LOVP can be determined as following. Meanwhile,
C
LINE-F
should be choosen considering some noises on
the line induced by switching of the main switch and etc.
It is typical to select 3~5 times of time constant higher
than switching frequency.
www.onsemi.com
21
FSL518H, FSL538H, FSL518A, FSL538A
which decreases the pulse current that charges the
capacitor every time the FSL5x8 resumes switching
operation in burst−mode.
• Clamping Circuit for internal MOSFET
Due to parasitic or leakage inductance, it is inevitable
that voltage on DRAIN pin of MOSFET shows some
spikes during switching off. A clamping circuit is
generally implemented if the spike can be so high that
makes DRAIN voltage possibly exceeds MOSFET’s
For more information, please refer to AN−4148.
• Maximum Duty and Reflected Output Voltage
When MOSFET in FSL5x8 is turned off, the input
breakdown voltage, BV . The clamping circuit can be
DSS
voltage together with the reflected output voltage (V
)
RO
RCD snubber or transient-voltage suppressor. In both
cases, the design target is to clamp the reflected voltage
that appears across primary winding with a clamping
on primary winding of the transformer are imposed on
MOSFET.
Ǹ
voltage V
.
VDRAIN
+
2 @ Vlinemax ) VRO
(eq. 8)
clamp
max
V
clamp
should be set up properly considering power
V
linemax
is maximum ac-input voltage in r.m.s. value.
loss and BV
of MOSFET. V
is way too high,
DSS
clamp
V
RO
is a function of maximum duty (D ) and minimum
max
MOSFET is likely to get damage at maximum input
voltage. Whereas, too low one could cause power loss
increasing at the clamp circuit. Generally, value in 2~2.5
times of VRO is usually chosen. Additionally, it should
DC-link voltage.
Dmax
VRO
+
@ VDC
(eq. 9)
min
1 * Dmax
The designed D
should not exceed FSL5x8’s
not exceed over 90% of BV
.
max
DSS
maximum duty raio specification, D
. It is typical to
according to
MAX
Ǹ
2 @ Vlinemax ) Vclamp v 90% @ BVDSS
(eq. 13)
have 70% of de-rating on V
DRAINmax
AN−4137 and AN−4140 provide detailed flyback
converter, transformer, and snubber design information.
A design tool with accompanying manual is also made for
FSL5x8 series.
MOSFET’s breakdown voltage. With 800 V of
breakdown voltage in FSL5x8, more room are created to
target higher D
.
max
• Transformer Design Considerations
When D is assigned, turn ratio of the transformer has
NP NS
max
−
been decided.
+
VRO
NP
NS
VIN
n +
+
,
(eq. 10)
VOUT ) VF
VRO
−
where N and N stands for primary and secondary
P
S
L
+
windings’ turn ratio of the transformer, V
stands for
OUT
output voltage, and V stands for forward voltage of
rectifying diode connecting to the secondary winding.
F
+
VDRAIN
−
Llk
Inductance (L ) of the primary winding can be
m
obtained from input power (P ) and switching frequency
in
(f ), with ripple factor (K ) left to be decided. K ≥ 1
sw
RF
RF
results in lower inductance and discontinuous-
conduction-mode (DCM) design, which tend to have
Figure 46. Magnetic Component and RCD Snubber
smaller switching loss. K < 1 results in a continuous-
RF
conduction-mode (CCM) design. Which tend to be able
to deliver more power with same maximum drain current.
IDRAIN
2
ǒV
Ǔ
PEAK
@ Dmax
DC
IDRAIN
min
Lm
+
(eq. 11)
2 Pin @ fSW @ KRF
t
VDS
The inductance value affects maximum drain current
), which should be limited by FSL5x8’s I
specification with some margin. Care needs to be taken
(I
DRAINPEAK
LIM
Vclamp
VRO
when designing L and choosing part from FSL5x8
m
series.
VIN
VDC @ Dmax
Pin
min
IDRAIN
+
+
(eq. 12)
PEAK
VDC @ Dmax
2 @ Lm @ fSW
t
min
Figure 47. Typical Waveform of DRAIN Current
and Voltage
www.onsemi.com
22
FSL518H, FSL538H, FSL518A, FSL538A
PCB Layout Recommendations
Hereafter are a few hints that would help designers to
make their SMPS working better.
• High-frequency switching current/voltage makes PCB
layout a very important design issue. Good PCB layout
minimizes EMI (Electromagnetic Interference) and helps
the power supply survive during surge/ESD
(ElectroStatic Discharge) tests.
There are some suggestions for grounding connection.
• GND: There are two kinds of GND in power conversion
board and should be separated for avoiding interference
and better performance.
• Regarding the ESD discharge path, the charges go from
secondary, through the transformer stray capacitance, to
GND first, and back to mains. It should be noted that
control circuits should not be placed on the discharge
path. Point discharge for common choke can decrease
high-frequency impedance and increase ESD immunity.
• To improve EMI performance and reduce line frequency
ripples, the output of the bridge rectifier should be
connected to capacitor C as close as possible.
DC
• 3 should be a point-discharger route to bypass the static
electricity energy. It is suggested to map out this discharge
route.
• The high-frequency current loop is formed from the
beginning of bridge rectifier, C , power transformer,
DC
Integrated MOSFET and return to GND of C . The area
DC
• Should a Y-cap be required between primary and
enclosed by this current loop should be designed as small
as possible to reduce conduction and radiation noise.
Keep the traces (especially 2a " 2b " 1) short, direct,
and wide. High-voltage traces related the drain of
MOSFET and RCD snubber should be kept far way from
control circuits to prevent unnecessary interference. If
a heatsink is used for MOSFET, connect this heatsink to
power ground.
secondary, connect this Y-cap to the positive terminal of
C . If this Y-cap is connected to primary GND, it should
DC
be connected to the negative terminal of C
(GND)
DC
directly. Point discharge of this Y-cap helps for ESD;
however, the creepage between these two pointed ends
should be at least 5 mm according to safety requirements.
Thermal Considerations
Power MOSFET dissipates heat during switching
• As indicated by 2a, the ground of control circuits should
be connected first, then to other circuitry.
operation. If chip temperature exceed T , thermal
SD
shutdown would be triggered and FSL5x8 stops operating to
protect itself from damage. The path of lowest thermal
impedance from FSL5x8’s chip to external are DRAIN pins.
It is recommended to increase area of connected copper to
DRAIN pin as much as possible.
• Place C
as close to VCC pin of the FSL5x8H/A as
Vcc
possible for good decoupling. It is recommended to use
a few of micro-farad capacitor and 100 nF ceramic
capacitor for high frequency noise decoupling as well.
Enlarge DRAIN pin pattern
for better heat emission
Figure 48. Layout Considerations
www.onsemi.com
23
FSL518H, FSL538H, FSL518A, FSL538A
Design Example
Hereafter is a typical schematic of an isolated flyback.
240R
240R
220pF/
100V
15V+
1uH
1A/250V
15V
12V
2A/600V
DF06M
220uF/
35V
MOV
220uF/
35V
XC/0.33uF
10mH
22uF/50V
ACTVR/1047
Input
T1
Z
1nF/
1kV
FSV10150V
FSV10120V
200k
200k
0R
1uH
47uF/400V
470uF/
25V
24k
68uF/25V
470uF/25V
1R
0R
GND
15V+
15V 12V
ES1J
1
8
7
GND DRAIN
COMP
5.1k
VCC
2
3
4
DRAIN
VCC
FB
VCC
FOD817A
NC
150k
22uF/
50V
5.1k
100nF/50V
COMP
5
100nF
COMP LINE
FSL538A
200k
1nF
100k
2M
1nF
7.5V
NCP431
30k
YC/222pF
Figure 49. FSL538AFLYGEVB Schematic
REFERENCES
For more details on specific designs, please refer to below documents:
• AN−4148 Audible Noise Reduction Technique for FPS Applications
https://www.onsemi.com/pub/Collateral/AN−4148.pdf.pdf
• AN−4137 Design Guidelines for Off-line Flyback Converters Using Power Switch
https://www.onsemi.com/pub/Collateral/AN−4137.pdf.pdf
• AN−4140 Transformer Design Consideration for Offline Flyback Converters Using Power Switch
https://www.onsemi.com/pub/Collateral/AN−4140.pdf.pdf
• EVBUM2650/D: 14.5 W auxiliary power for white goods and industrial equipment with FSL538HPG
https://www.onsemi.com/pub/Collateral/EVBUM2650−D.PDF
• EVBUM2651/D: 15 W auxiliary power for white goods and industrial equipment with FSL538APG
https://www.onsemi.com/pub/Collateral/EVBUM2651−D.PDF
• EVBUM2652/D: 8 W auxiliary power for white goods and industrial equipment with FSL518APG
https://www.onsemi.com/pub/Collateral/EVBUM2652−D.PDF
• FSL5x8 Application note and Design tool
https://www.onsemi.com/PowerSolutions/supportDoc.do?type=tools&rpn=FSL538
www.onsemi.com
24
FSL518H, FSL538H, FSL518A, FSL538A
ORDERING INFORMATION
Device
†
Current Limit (A)
R
(W)
Package
Shipping
DS.ON,max
FSL518HPG
0.46
8.0
PDIP−7
(Pb-Free)
Tube
FSL518APG
FSL538HPG
FSL538APG
0.61
0.66
0.86
8.0
4.6
4.6
PDIP−7
Tube
Tube
Tube
(Pb-Free)
PDIP−7
(Pb-Free)
PDIP−7
(Pb-Free)
SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
www.onsemi.com
25
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 6)
CASE 626A
ISSUE C
DATE 22 APR 2015
SCALE 1:1
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
E
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
H
8
5
4
E1
1
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 8
c
b2
B
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
TOP VIEW
INCHES
DIM MIN MAX
−−−−
A1 0.015
MILLIMETERS
A2
A
MIN
−−−
0.38
2.92
0.35
MAX
5.33
−−−
4.95
0.56
e/2
A
0.210
−−−−
NOTE 3
A2 0.115 0.195
L
b
b2
C
0.014 0.022
0.060 TYP
0.008 0.014
1.52 TYP
0.20
9.02
0.13
7.62
6.10
0.36
10.16
−−−
8.26
7.11
D
0.355 0.400
SEATING
PLANE
D1 0.005
0.300 0.325
E1 0.240 0.280
−−−−
A1
D1
E
C
M
e
eB
L
0.100 BSC
−−−− 0.430
0.115 0.150
−−−− 10°
2.54 BSC
−−−
2.92
−−−
10.92
3.81
10°
e
eB
8X
b
END VIEW
M
NOTE 6
M
M
M
0.010
C A
B
SIDE VIEW
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AWL
YYWWG
XXXX = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11774D
PDIP−7 (PDIP−8 LESS PIN 6)
PAGE 1 OF 1
ON Semiconductor and
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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相关型号：
FSL9110D3
Power Field-Effect Transistor, 2.5A I(D), 100V, 1.3ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, HERMETIC SEALED, METAL CAN-3
FAIRCHILD
FSL9110R1
Power Field-Effect Transistor, 2.5A I(D), 100V, 1.3ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, HERMETIC SEALED, METAL CAN-3
FAIRCHILD
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