FSQ0170RNA [ONSEMI]
具有100kHz 的 700V 集成电源开关，用于 13W 离线反激转换器;
| 型号： | FSQ0170RNA |
| 厂家： | 
ONSEMI |
| 描述： | 具有100kHz 的 700V 集成电源开关，用于 13W 离线反激转换器 开关 电源开关 光电二极管 转换器 |
| 文件： | 总18页 (文件大小：495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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October 2011
FSQ0170RNA, FSQ0270RNA
Green Mode Fairchild Power Switch (FPS™)
Features
Description
Internal Avalanche Rugged 700V SenseFET
Consumes only 0.8W at 230 VAC & 0.5W Load with
Burst-Mode Operation
Precision Fixed Operating Frequency, 100kHz
Internal Start-up Circuit and Built-in Soft-Start
The FSQ0170RNA, and FSQ0270RNA, consists of an
integrated current mode Pulse Width Modulator (PWM)
and an avalanche-rugged 700V Sense FET. It is
specifically designed for high-performance off-line
Switch Mode Power Supplies (SMPS) with minimal
external components. The integrated PWM controller
features include: a fixed-frequency generating oscillator,
Under-Voltage Lockout (UVLO) protection, Leading
Edge Blanking (LEB), an optimized gate turn-on/turn-off
driver, Thermal Shutdown (TSD) protection, and
temperature compensated precision current sources for
loop compensation and fault protection circuitry.
Pulse-by-Pulse Current Limiting and Auto-Restart
Mode
Over-Voltage Protection (OVP), Overload Protection
(OLP), Internal Thermal Shutdown Function (TSD)
Under-Voltage Lockout (UVLO)
Low Operating Current (3mA)
Adjustable Peak Current Limit
Compared to a discrete MOSFET and controller or RCC
switching converter solution, the FSQ0170RNA, and
FSQ0270RNA reduces total component count, design
size, and weight while increasing efficiency, productivity,
and system reliability. These devices provide a basic
platform that is well suited for the design of cost-effective
flyback converters, as in PC auxiliary power supplies.
Applications
Auxiliary Power Supply for PC and Server
SMPS for VCR, SVR, STB, DVD & DVCD Player,
Printer, Facsimile & Scanner
Adapter for Camcorder
Related Application Notes
AN-4134: Design Guidelines for Off-line Forward
8-DIP
Converters Using Fairchild Power Switch (FPS™)
AN-4137: Design Guidelines for Off-line Flyback
Converters Using Fairchild Power Switch (FPS™)
AN-4141: Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
AN-4147: Design Guidelines for RCD Snubber of
Flyback
AN-4148: Audible Noise Reduction Techniques for
FPS™ Applications
Ordering Information
Product Number
FSQ0170RNA
Package
8DIP
Marking Code
Q0170RA
BV
f
R
DS(ON) (MAX.)
DSS
OSC
700V
700V
100kHz
100kHz
11
FSQ0270RNA
8DIP
Q0270RA
7.2
FPSTM is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
Application Diagram
AC
IN
DC
OUT
Vstr
PWM
Drain
IPK
VCC
FB
GND
FSQ0x70RNA Rev. 1.01
Figure 1. Typical Flyback Application
(1)
Output Power Table
(2)
230V 15%
85–265V
AC
AC
Product
(3)
(4)
(3)
(4)
Adapter
14W
Open Frame
20W
Adapter
9W
Open Frame
13W
FSQ0170RNA
FSQ0270RNA
17W
24W
11W
16W
Notes:
1. The maximum output power can be limited by junction temperature.
2. 230 VAC or 100/115 VAC with doubler.
3. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sink, at 50C
ambient.
4. Maximum practical continuous power in an open-frame design with sufficient drain pattern as a heat sink, at 50C
ambient.
Internal Block Diagram
Vstr
5
VCC
2
Drain
6,7,8
ICH
8V/12V
VCC good
Internal
Bias
Vref
VBURL/VBURH
VCC
VCC
OSC
PWM
IDELAY
IFB
Normal
FB 3
S
R
Q
Gate
Driver
2.5R
Burst
R
Q
IPK
4
LEB
VSD
VCC
Vovp
1
GND
S
R
Q
Q
VCC good
TSD
Soft-Start
FSQ0x70RNA Rev. 1.00
Figure 2. Internal Block Diagram
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
2
Pin Configuration
GND
VCC
FB
D
D
8-DIP
D
IPK
Vstr
FSQ0x70RNA Rev. 1.00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
Ground. SenseFET source terminal on primary side and internal control
ground.
1
GND
Power Supply. Positive supply voltage input. Although connected to an aux-
iliary transformer winding, current is supplied from pin 5 (Vstr) via an internal
switch during start-up, see Figure 2. It is not until VCC reaches the UVLO upper
threshold (12V) that the internal start-up switch opens and device power is
supplied via the auxiliary transformer winding.
2
3
VCC
Feedback. The feedback voltage pin is the non-inverting input to the PWM
comparator. It has a 0.9mA current source connected internally while a capac-
itor and opto-coupler are typically connected externally. A feedback voltage of
6V triggers overload protection (OLP). There is a time delay while charging ex-
ternal capacitor CFB from 3V to 6V using an internal 5µA current source. This
time delay prevents false triggering under transient conditions, but still allows
the protection mechanism to operate under true overload conditions.
FB
Peak Current Limit. This pin adjusts the peak current limit of the SenseFET.
The 0.9mA feedback current source is diverted to the parallel combination of
an internal 2.8k resistor and any external resistor to GND on this pin. This
determines the peak current limit. If this pin is tied to VCC or left floating, the
typical peak current limit is 0.8A (FSQ0170RNA), 0.9A (FSQ0270RNA).
4
5
IPK
Start-up. This pin connects to the rectified AC line voltage source. At start-up,
the internal switch supplies internal bias and charges an external storage ca-
pacitor placed between the VCC pin and ground. Once the VCC reaches 12V,
the internal switch is opened.
Vstr
6
7
8
Drain
Drain
Drain
SenseFET drain. High-voltage power SenseFET drain connection.
SenseFET drain. High-voltage power SenseFET drain connection.
SenseFET drain. High-voltage power SenseFET drain connection.
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only
Symbol
VDRAIN
VSTR
Characteristic
Value
Unit
V
Drain Pin Voltage
Vstr Pin Voltage
700
700
V
FSQ0170RNA
FSQ0270RNA
FSQ0170RNA
FSQ0270RNA
4
IDM
Drain Current Pulsed(5)
A
8
50
EAS
Single Pulsed Avalanche Energy(6)
mJ
140
VCC
VFB
PD
Supply Voltage
20
V
V
Feedback Voltage Range
Total Power Dissipation
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
-0.3 to VCC
1.5
W
C
C
C
TJ
Internally limited
-25 to +85
-55 to +150
TA
TSTG
Notes:
5. Non-repetitive rating: Pulse width is limited by maximum junction temperature.
6. L = 51mH, starting TJ = 25C.
Thermal Impedance
TA = 25C, unless otherwise specified. All items are tested with the standards JESD 51-2 and 51-10 (DIP).
Symbol
JA
Parameter
Value
80
Unit
C/W
C/W
C/W
Junction-to-Ambient Thermal Resistance(7)
Junction-to-Case Thermal Resistance(8)
Junction-to-Top Thermal Resistance(9)
JC
20
JT
35
Notes:
7. Free standing with no heatsink; without copper clad.
(Measurement Condition - Just before junction temperature TJ enters into OTP.)
8. Measured on the DRAIN pin close to plastic interface.
9. Measured on the PKG top surface.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
4
Electrical Characteristics
TA = 25C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
SenseFET Section(10)
VDS = 700V, VGS = 0V
50
IDSS
Zero-Gate-Voltage Drain Current
A
VDS = 560V, VGS = 0V,
TC = 125C
200
Drain-Source
On-State
FSQ0170RNA
FSQ0270RNA
8.8
6.0
11
RDS(ON)
VGS = 10V, ID = 0.5A
Resistance(11)
7.2
FSQ0170RNA
FSQ0270RNA
FSQ0170RNA
FSQ0270RNA
FSQ0170RNA
FSQ0270RNA
FSQ0170RNA
FSQ0270RNA
FSQ0170RNA
FSQ0270RNA
FSQ0170RNA
FSQ0270RNA
FSQ0170RNA
FSQ0270RNA
250
550
25
38
10
17
12
20
4
CISS
COSS
CRSS
td(on)
tr
Input Capacitance
Output Capacitance
V
GS = 0V, VDS = 25V,
pF
f = 1MHz
Reverse Transfer
Capacitance
Turn-On Delay Time
Rise Time
15
30
55
10
25
VDS = 350V, ID = 1.0A
ns
td(off)
Turn-Off Delay Time
Fall Time
tf
Control Section
fOSC
fOSC
DMAX
DMIN
VSTART
VSTOP
IFB
Switching Frequency
Switching Frequency Variation(10)
92
100
±5
60
0
108
±10
65
0
KHz
%
-25C TA 85C
Maximum Duty Cycle
Minimum Duty Cycle
Measured at 0.1 x VDS
55
0
%
%
VFB = GND
VFB = GND
VFB = GND
VFB = 4V
11
7
12
8
13
9
UVLO Threshold Voltage
V
Feedback Source Current
Internal Soft-Start Time(10)
0.7
0.9
10
1.1
mA
ms
tS/S
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
TA = 25C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Burst-Mode Section
VBURH
0.5
0.3
0.6
0.4
0.7
0.5
300
V
V
VBURL
Burst-Mode Voltage
TJ 25C
VBUR(HYS)
100
200
mV
Protection Section
FSQ0170RNA
FSQ0270RNA
Current Limit Delay Time(10)
Thermal Shutdown Temperature(10)
Shutdown Feedback Voltage
Over-Voltage Protection
di/dt = 170mA/µs
di/dt = 200mA/µs
0.70
0.79
0.80
0.90
500
140
6.0
0.90
1.01
ILIM
Peak Current Limit
A
tCLD
TSD
ns
C
V
125
5.5
18
VSD
6.5
6.5
VOVP
IDELAY
tLEB
19
V
Shutdown Delay Current
Leading Edge Blanking Time(10)
VFB = 4V
3.5
200
5.0
A
ns
Total Device Section
Operating Supply Current
(Control Part Only)
IOP
VCC = 14V
1
3
5
mA
VCC = 0V,
ICH
Startup Charging Current
Vstr Supply Voltage
0.70
0.85
24
1.00
mA
V
RSTR<100k (12)
VSTR
VCC = 0V
Notes:
10. These parameters, although guaranteed, are not 100% tested in production.
11. Pulse test: Pulse width ≤ 300µs, duty ≤ 2%.
12. RSTR is connected between the rectified AC line voltage source and VSTR pin.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
6
Typical Performance Characteristics (Control Part)
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100 125 150
-25
0
25
50
75
100 125 150
Temperature [°C]
Temperature [°C]
Figure 4. Operating Frequency (fOSC) vs. TA
Figure 5. Over-Voltage Protection (VOVP) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100 125 150
-25
0
25
50
75
100 125 150
Temperature [°C]
Temperature [°C]
Figure 6. Maximum Duty Cycle (DMAX) vs. TA
Figure 7. Operating Supply Current (IOP) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100 125 150
-25
0
25
50
75
100 125 150
Temperature [°C]
Temperature [°C]
Figure 8. Start Threshold Voltage (VSTART) vs. TA
Figure 9. Stop Threshold Voltage (VSTOP) vs. TA
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA= 25°C.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100 125 150
-25
0
25
50
75
100 125 150
Temperature [°C]
Temperature [°C]
Figure 10. Feedback Source Current (IFB) vs. TA
Figure 11. Startup Charging Current (ICH) vs. TA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100 125 150
Temperature [°C]
Figure 12. Peak Current Limit (ILIM) vs. TA
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
8
4. Protection Circuits: The FPS has several protective
functions, such as Overload Protection (OLP), Over-
Voltage Protection (OVP), Under-Voltage Lockout
(UVLO), and Thermal Shutdown (TSD). Because these
protection circuits are fully integrated in the IC without
external components, reliability is improved without
increasing cost. Once a fault condition occurs, switching
is terminated and the SenseFET remains off. This
causes VCC to fall. When VCC reaches the UVLO stop
Functional Description
1. Startup: In previous generations of Fairchild Power
Switches (FPS™), the Vstr pin required an external
resistor to the DC input voltage line. In this generation,
the startup resistor is replaced by an internal high-
voltage current source and a switch that shuts off 10ms
after the supply voltage, VCC, goes above 12V. The
source turns back on if VCC drops below 8V.
voltage, VSTOP (typically 8V), the protection is reset and
the internal high-voltage current source charges the VCC
capacitor via the Vstr pin. When VCC reaches the UVLO
start voltage, VSTART (typically 12V), the FPS resumes
VIN,dc
ISTR
Vstr
Vcc<8V
UVLO on
Vcc
its normal operation. In this manner, the auto-restart can
alternately enable and disable the switching of the power
SenseFET until the fault condition is eliminated.
J-FET
ICH
10ms after
Vcc≥12V
UVLO off
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding a pre-set level due to an
unexpected event. In this situation, the protection circuit
should be activated to protect the SMPS. However, even
when the SMPS is operating normally, the OLP circuit
can be activated during the load transition. To avoid this
undesired operation, the OLP circuit is designed to be
activated after a specified time to determine whether it is
a transient situation or a true overload situation. In
conjunction with the IPK current limit pin (if used), the
FSQ0x70RNA Rev. 1.00
Figure 13. High-Voltage Current Source
2. Feedback Control: The 700V FPS series employs
current-mode control, as shown in Figure 14. An opto-
coupler (such as the H11A817A) and shunt regulator
(such as the KA431) are typically used to implement the
feedback network. Comparing the feedback voltage with
the voltage across the Rsense resistor of SenseFET, plus
current mode feedback path limits the current in the
SenseFET when the maximum PWM duty cycle is
attained. If the output consumes more than this
maximum power, the output voltage (VO) decreases
an offset voltage, makes it possible to control the
switching duty cycle. When the shunt regulator reference
pin voltage exceeds the internal reference voltage of
2.5V, the opto-coupler LED current increases, the
feedback voltage VFB is pulled down and thereby
below nominal voltage. This reduces the current through
the opto-coupler LED, which also reduces the opto-
coupler transistor current, thus increasing the feedback
voltage (VFB). If VFB exceeds 3V, the feedback input
reduces the duty cycle. This typically happens when the
input voltage increases or the output load decreases.
VCC
VCC
5A
diode is blocked and the 5µA current source (IDELAY
)
900A
FB
VO
starts to slowly charge CFB up to VCC. In this condition,
VFB increases until it reaches 6V, when the switching
3
OSC
2.5R
D1
D2
+
CFB
VFB
operation is terminated, as shown in Figure 15. The
shutdown delay time is the time required to charge CFB
VFB,in
Gate
driver
R
-
from 3V to 6V with 5µA current source.
431
VFB
FSQ0x70RNA Rev.00
Overload Protection
OLP
VSD
6V
FSQ0x70RNA Rev. 1.00
Figure 14. Pulse Width Modulation Circuit
3V
3. Leading Edge Blanking (LEB): When the internal
SenseFET is turned on, the primary-side capacitance
and secondary-side rectifier diode reverse recovery
t12= CFB×(V(t2)-V(t1)) / IDELAY
typically cause
SenseFET. Excessive voltage across the Rsense resistor
a high-current spike through the
t1
t2
t
V (t2 ) V (t1)
IDELAY
t12 CFB
;
IDELAY 5 A,V (t1) 3V,V (t2 ) 6V
leads to incorrect feedback operation in the current-
mode PWM control. To counter this effect, the FPS
employs a Leading Edge Blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
(tLEB) after the Sense FET is turned on.
Figure 15. Overload Protection (OLP)
4.2 Thermal Shutdown (TSD): The SenseFET and the
control IC are integrated, making it easier for the control
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
9
IC to detect the temperature of the SenseFET. When the
temperature exceeds approximately 140C, thermal
shutdown is activated.
At this point, switching stops and the output voltage
starts to drop at a rate dependent on the standby current
load. This causes the feedback voltage to rise. Once it
passes VBURH
, switching resumes. The feedback
4.3 Over-Voltage Protection (OVP): In the event of a
malfunction in the secondary-side feedback circuit, or an
open feedback loop caused by a soldering defect, the
current through the opto-coupler transistor becomes
almost zero (see Figure 14). VFB climbs up in a similar
voltage then falls and the process is repeated. Burst-
mode operation alternately enables and disables
switching of the SenseFET and reduces switching loss in
standby mode.
manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is activated. Because excess energy
is provided to the output, the output voltage may exceed
the rated voltage before the overload protection is
activated, resulting in the breakdown of the devices in
the secondary side. To prevent this situation, an Over-
Voltage Protection (OVP) circuit is employed. In general,
VCC is proportional to the output voltage and the FPS
Burst Operation
Burst Operation
Normal
Operation
VFB
VBURH
VBURL
Current
Waveform
Switching
OFF
FSQ0x70RNA Rev.00
Switching OFF
uses VCC instead of directly monitoring the output
voltage. If VCC exceeds 19V, the OVP circuit is activated,
resulting in termination of the switching operation. To
avoid undesired activation of OVP during normal
operation, VCC should be designed to be below 19V.
Figure 17. Burst Operation Function
7. Adjusting Peak Current Limit: As shown in Figure
18, a combined 2.8k internal resistance is connected to
the non-inverting lead on the PWM comparator. An
external resistance of Rx on the current limit pin forms a
parallel resistance with the 2.8k when the internal
diodes are biased by the main current source of 900µA.
5. Soft-Start: The FPS has an internal soft-start circuit
that slowly increases the SenseFET current after start-
up, as shown in Figure 16. The typical soft-start time is
10ms, where progressive increments of the SenseFET
current are allowed during the start-up phase. The pulse
width to the power switching device is progressively
increased to establish the correct working conditions for
transformers, inductors, and capacitors. The voltage on
the output capacitors is progressively increased to
smoothly establish the required output voltage. This also
helps prevent transformer saturation and reduces the
stress on the secondary diode during startup.
VCC
VCC
PWM
Comparator
5A
900A
IDELAY
IFB
VFB
2kΩ
3
4
0.8kΩ
IPK
#6,7,8
5V
SenseFET
Current
Sense
DRAIN
Rx
FSQ0x70RNA Rev. 1.00
#1
GND
Figure 18. Peak Current Limit Adjustment
ILIM
Rsense
For example, FSQ0270RNA has a typical SenseFET
peak current limit (ILIM) of 0.9A. ILIM can be adjusted to
FSQ0x70RNA Rev. 1.00
0.6A by inserting Rx between the IPK pin and the ground.
The value of the Rx can be estimated by the following
equations:
Figure 16. Soft-Start Function
0.9A: 0.6A = 2.8k : Xk,
6. Burst Operation: To minimize power dissipation in
standby mode, the FPS enters burst-mode operation.
Feedback voltage decreases as the load decreases, as
shown in Figure 17, and the device automatically enters
burst-mode when the feedback voltage drops below
VBURH (typically 600mV). Switching continues until the
X = Rx || 2.8k
where X represents the resistance of the parallel network.
feedback voltage drops below VBURL (typically 400mV).
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
10
Application Information
Methods of Reducing Audible Noise
Switching-mode power converters have electronic and
magnetic components, which generate audible noise
when the operating frequency is in the range of
20~20,000Hz. Even though they operate above 20KHz,
they can make noise, depending on the load condition.
The following sections discuss methods to reduce noise.
Glue or Varnish
The most common method of reducing noise involves
using glue or varnish to tighten magnetic components.
The motion of core, bobbin, and coil and the chattering
or magnetostriction of core can cause the transformer to
produce audible noise. The use of rigid glue and varnish
helps reduce the transformer noise. Glue or varnish can
also can crack the core because sudden changes in the
ambient temperature cause the core and the glue to
expand or shrink in a different ratio.
Figure 19. Equal Loudness Curves
Ceramic Capacitor
Using a film capacitor instead of a ceramic capacitor as a
snubber capacitor is another noise reduction solution.
Some dielectric materials show a piezoelectric effect,
depending on the electric field intensity. Hence, a
snubber capacitor becomes one of the most significant
sources of audible noise. Another possibility is to use a
Zener clamp circuit instead of an RCD snubber for
higher efficiency as well as lower audible noise.
Adjusting Sound Frequency
Moving the fundamental frequency of noise out of the
2~4kHz range is the third method. Generally, humans
are more sensitive to noise in the range of 2~4kHz.
When the fundamental frequency of noise is located in
this range, the noise sounds louder although the noise
intensity level is identical (see Figure 19).
Figure 20. Typical Feedback Network of FPS
Other Reference Materials
AN-4134: Design Guidelines for Off-line Forward
Converters Using Fairchild Power Switch (FPS™)
When the FPS acts in burst mode and the burst
operation is suspected to be a source of noise, this
method may be helpful. If the frequency of burst mode
operation lies in the range of 2~4kHz, adjusting the
feedback loop can shift the burst operation frequency. To
AN-4137: Design Guidelines for Off-line Flyback
Converters Using Fairchild Power Switch (FPS™)
AN-4140: Transformer Design Consideration for Off-line
Flyback Converters using Fairchild Power Switch (FPS™)
reduce the burst operation frequency, increase
a
feedback gain capacitor (CF), opto-coupler supply
resistor (RD); and feedback capacitor (CB), and decrease
a feedback gain resistor (RF), as shown in Figure 20.
AN-4141: Troubleshooting and Design Tips for Fairchild
Power Switch (FPS™) Flyback Applications
AN-4147: Design Guidelines for RCD Snubber of
Flyback
AN-4148: Audible Noise Reduction Techniques for
FPS™ Applications
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
11
Typical Application Circuit
Application
Output power
15W
Input Voltage
Output Voltage (Max. Current)
PC Auxiliary Power Supply
(Using FSQ0270RNA)
Universal input
5V (3A)
(85-265 VAC
)
Features
High efficiency (> 78% at 115 VAC and 230 VAC input)
Low standby mode power consumption (< 0.8W at 230 VAC input and 0.5W load)
Enhanced system reliability through various protection functions
Internal soft-start (10ms)
Line UVLO function can be achieved using external component
Key Design Notes
The delay time for overload protection is designed to be about 30ms with C8 of 47nF. If faster/slower triggering of
OLP is required, C8 can be changed to a smaller/larger value (e.g. 100nF for about 60ms).
ZP1, DL1, RL1, RL2, RL3, RL4, RL5, RL7, QL1, QL2, and CL9 build a Line Under-Voltage Lockout block (UVLO).
The Zener voltage of ZP1 determines the input voltage that makes FPS turn on. RL5 and DL1 provide a reference
voltage from VCC. If the input voltage divided by RL1, RL2, and RL4 is lower than the Zener voltage of DL1, QL1 and
QL2 turn on and pull down VFB to ground.
An evaluation board and corresponding test report can be provided.
1. Schematic
C1
2.2nF
AC250V
RS1
9
CS1
1.5nF
L1
330H
L2
1H
ZDS1
P6KE180A
T1
CON2
1
EE2229
1
6,7
D1
SB540
2
D2
D3
C10
1nF
250V
ZP1
Output
R3
R4
J4
0
R2
R6
2.4 1W
3
9, 10
1N4007 1N4007
CON1
560
100
4.7k
1
2
3
C2
22F
400V
C3
22F
400V
R14
30
1N4762
1
R5
1.25k
1%
U1A
FOD817A
Input
R8
C5
470F
10V
D4
D5
C4
1000F 1000F
16V
16V
C9
open
DS1
1N4007
1N4007 1N4007
2
3
L3
0
J1
R9
10k
C6
47nF
FB
R11
1.2k
1%
4
U2
TL431A
RL1 1M
1
U3
D6
1N4007 2
R10
2
FSQ0270RNA
RL5
30k
DL1
1N5233B
8
1
7
6
3
5
4
5
RL2
1M
QL1
KSP2907A
J3
open
C7
47F
25V
ZR1
80
2
R12
RL4
120k
open
J2
0
RL3
1k
4
ZD1
1N4745
CL9
10F
50V
ZD2 C8
open
RL7
40k
3
47nF
U1B
QL2
R13
open
FSQ0x70RNA Rev. 1.12
KSP2222A FOD817A
Figure 21. Demo Circuit
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
12
2. Transformer
EE2229
1
9, 10
6, 7
2
3
4
5
Np/2
Np/2
N5V
Na
FSQ0x70RNA Rev. 1.00
Figure 22. Transformer Schematic Diagram
3. Winding Specification
Pin (S F)
3 2
Insulation: Polyester Tape t = 0.025mm, 1 Layers
Na 4 5
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N5V 6, 7 9, 10
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Np/2 2 1
Wire
Turns
Winding Method
Np/2
0.31
72
22
8
Solenoid winding
0.252
0.652
0.31
Solenoid winding
Solenoid winding
Solenoid winding
72
Insulation: Polyester Tape t = 0.025mm, 2 Layers
4. Electrical Characteristics
Pin
Specification
1.20mH ± 5%
< 30µH Max
Remark
100kHz, 1V
Inductance
Leakage
1–3
1–3
Short all other pins
5. Core & Bobbin
Core: EE2229 (Material: PL-7, Ae = 35.7 mm2)
Bobbin: BE2229
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
13
6. Demo Circuit Part List
Part Number
Value
47nF
Quantity
Description (Manufacturer)
Ceramic Capacitor
C6, C8
2
1
1
1
2
2
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
6
1
1
1
1
1
C1
2.2nF (1KV)
1nF (200V)
1.5nF (50V)
22µF (400V)
1000µF (16V)
470µF (10V)
47µF (25V)
10µF (50V)
330µH
AC Ceramic Capacitor(X1 & Y1)
C10
Mylar Capacitor
CS1
Ceramic Capacitor
C2, C3
Low Impedance Electrolytic Capacitor KMX series
C4, C9
Low ESR Electrolytic Capacitor NXC series
C5
Low ESR Electrolytic Capacitor NXC series
C7
General Electrolytic Capacitor
CL9
General Electrolytic Capacitor
L1
Inductor
L2
1µH
Inductor
R6
2.4 (1W)
0
Fusible Resistor
J1, J2, J4, L3
Jumper
R2
4.7k
Resistor
R3
560
Resistor
R4
100
Resistor
R5
1.25k
1.2k
Resistor
R11
Resistor
R9
10k
Resistor
R10
2
Resistor
R14
30
Resistor
RL3
1k
Resistor
RL1, RL2
1M
Resistor
RL4
120k
Resistor
RL5
30k
Resistor
RL7
40k
Resistor
RS1
9
Resistor
ZR1
80
Resistor
U1
FOD817A
TL431
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
Diode (Fairchild Semiconductor)
Schottky Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
TVS (Fairchild Semiconductor)
U2
U3
FSQ0270RNA
2N2907
2N2222
1N4007
SB540
QL1
QL2
D2, D3, D4, D5, D6, DS1
D1
ZD1
DL1
ZP1
ZDS1
1N4745
1N5233
82V (1W)
P6KE180A
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
14
7. Layout
Figure 23. Top Image of PCB
Figure 24. Bottom Image of PCB
© 2006 Fairchild Semiconductor Corporation
FSQ0170RNA, FSQ0270RNA Rev. 1.0.5
www.fairchildsemi.com
15
0.400 10.16
0.373 9.47
A
C
0.036 0.9 TYP
8
5
8
1
R0.032 0.813
PIN #1
0.092 2.337
PIN #1
0.255 6.48
0.245 6.22
C
1
4
B
D
0.070 1.78
0.045 1.14
TOP VIEW, OPTION 1
TOP VIEW, OPTION 2
0.320 8.13
7° TYP
0.300 7.62
7° TYP
0.135 3.43
0.125 3.18
0.210 5.33 MAX
0.015 0.381
0.010 0.254
C
0.060 1.52
MAX
0.015 0.38 MIN
0.140 3.56
0.125 3.17
0.300 7.62
0.100 2.54
0.021 0.53
0.43 10.92 MAX
0.015 0.38
0.001 [0.025]
FRONT VIEW
M
C
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS-001, VARIATION BA
B. CONTROLLING DIMENSIONS ARE IN INCHES.
REFERENCE DIMENSIONS ARE IN MILLIMETERS.
C
D
DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
0.010 INCHES OR 0.25MM.
DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED 0.010
INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M-2009
F. DRAWING FILENAME: MKT-N08Erev8
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