FSQ0370RNA [ONSEMI]
700V 集成电源开关，100kHz，用于 19W 离线反激转换器;
| 型号： | FSQ0370RNA |
| 厂家： | 
ONSEMI |
| 描述： | 700V 集成电源开关，100kHz，用于 19W 离线反激转换器 开关 电源开关 光电二极管 转换器 |
| 文件： | 总19页 (文件大小：731K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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March 2012
FSQ0370RNA, FSQ0370RLA
Green Mode Fairchild Power Switch (FPS™)
Features
Description
The FSQ0370 consists of an integrated Current Mode
Pulse Width Modulator (PWM) and an avalanche rugged
700V SenseFET. It is specifically designed for high-
performance offline Switched Mode Power Supplies
(SMPS) with minimal external components. The
integrated PWM controller features include: a fixed-
frequency generating oscillator, Under-Voltage Lockout
(UVLO) protection, Leading-Edge Blanking (LEB), an
.
.
Internal Avalanche Rugged 700V SenseFET
Consumes Only 0.8W at 230VAC & 0.5W Load with
Burst-Mode Operation
.
.
.
.
Precision Fixed Operating Frequency: 100kHz
Internal Startup Circuit and Built-in Soft-Start
Pulse-by-Pulse Current Limiting, Auto-Restart Mode
optimized gate turn-on
/ turn-off driver, Thermal
Over-Voltage Protection (OVP), Overload
Protection (OLP), Internal Thermal Shutdown
Function (TSD)
Shutdown (TSD) protection, and temperature-
compensated precision current sources for loop
compensation and fault protection circuitry.
.
.
.
Under-Voltage Lockout (UVLO)
Low Operating Current: 3mA
Adjustable Peak Current Limit
Compared to a discrete MOSFET and controller or RCC
switching converter solution, the FSQ0370 reduces total
component count, design size, and weight while
increasing efficiency, productivity, and system reliability.
These devices provide a basic platform that is well
suited for the design of cost-effective flyback converters,
such as in PC auxiliary power supplies.
Applications
.
.
.
.
Auxiliary Power Supply for PC and Server
SMPS for VCR, SVR, STB, DVD, and DVCD Player
Printer, Facsimile, and Scanner
Related Application Notes
.
.
.
AN-4134 — Design Guidelines for Off-line Forward
Converters Using Fairchild Power Switch (FPS™)
Adapter for Camcorder
AN-4137 — Design Guidelines for Offline Flyback
Converters Using Fairchild Power Switch (FPS™)
AN-4141 — Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback
Applications
.
AN-4147 — Design Guidelines for RCD Snubber of
Flyback Converters
Ordering Information
Part Number
Package
Marking Code
BVDSS
fOSC
RDS(ON)(MAX)
FSQ0370RNA 8-Lead, Dual Inline Package (DIP)
FSQ0370RLA 8-Lead, LSOP
Q0370RA
700V
100KHz
4.75Ω
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
Application Circuit
AC
IN
DC
OUT
Vstr
PWM
Drain
Ipk
Vfb
Vcc
Source
Figure 1. Typical Flyback Application
230VAC ±15%(2)
Table 1. Output Power Table(1)
Product
85-265VAC
Adapter(3)
Open Frame(4)
Adapter(3)
Open Frame(4)
FSQ0370RNA
FSQ0370RLA
20W
27W
13W
19W
Notes:
1. The maximum output power can be limited by junction temperature.
2. 230VAC or 100/115VAC with doubler.
3. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sink at
50°C ambient.
4. Maximum practical continuous power in an open-frame design with sufficient drain pattern as a heat sink at
50°C ambient.
Internal Block Diagram
Figure 2. Functional Block Diagram
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
2
Pin Assignments
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin#
Name
Description
1
GND
SenseFET source terminal on the primary side and internal control ground.
Positive supply voltage input. Although connected to an auxiliary transformer winding,
current is supplied from pin 5 (Vstr) via an internal switch during startup (see Figure 2).
It is not until VCC reaches the UVLO upper threshold (12V) that the internal startup switch
opens and device power is supplied via the auxiliary transformer winding.
2
3
4
Vcc
Vfb
Ipk
The feedback voltage pin is the non-inverting input to the PWM comparator. It has a
0.9mA current source connected internally, while a capacitor and optocoupler are typically
connected externally. A feedback voltage of 6V triggers overload protection (OLP). There
is a delay while charging external capacitor Cfb from 3V to 6V using an internal 5µA
current source. This delay prevents false triggering under transient conditions, but allows
the protection mechanism to operate in true overload conditions.
This pin adjusts the peak current limit of the SenseFET. The 0.9mA feedback current
source is diverted to the parallel combination of an internal 2.8kΩ resistor and any
external resistor to GND on this pin. This determines the peak current limit. If this pin is
tied to Vcc or left floating, the typical peak current limit is 1.1A.
This pin is connected to the rectified AC line voltage source. At startup, the internal switch
supplies internal bias and charges an external storage capacitor placed between the Vcc
pin and ground. Once VCC reaches 12V, the internal switch is opened.
5
Vstr
The drain pins are designed to connect directly to the primary lead of the transformer and
are capable of switching a maximum of 700V. Minimizing the length of the trace
connecting these pins to the transformer decreases leakage inductance.
6, 7, 8
Drain
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
VDRAIN
VSTR
IDM
Parameter
Min.
700
Max.
Unit
V
Drain Pin Voltage
Vstr Pin Voltage
700
V
Drain Current Pulsed(5)
12
A
EAS
Single Pulsed Avalanche Energy(6)
230
mJ
V
VCC
Supply Voltage
20
VFB
Feedback Voltage Range
Total Power Dissipation
-0.3
VCC
V
PD
1.5
Internally Limited
+85
W
°C
°C
°C
TJ
Recommended Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
-40
-40
-55
TA
TSTG
+150
Notes:
5. Non-repetitive rating: pulse-width limited by maximum junction temperature.
6. L=51mH, starting TJ=25°C.
Thermal Impedance
Symbol
θJA
Parameter
Junction-to-Ambient Thermal Resistance(7)
Junction-to-Case Thermal Resistance(8)
Junction-to-Top Thermal Resistance(9)
Value
80
Unit
θJC
20
°C/W
35
ΨJT
Notes:
7. Free-standing with no heat-sink, without copper clad.
8. Measured on the drain pin, close to the plastic interface.
9. Measured on the package top surface.
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
4
Electrical Characteristics
TA=25°C unless otherwise specified.
Symbol
Parameter
Condition
Min. Typ. Max.
Unit
SenseFET Section(10)
VDS=700V, VGS=0V
50
IDSS
Zero-Gate-Voltage Drain Current
µA
VDS=560V, VGS=0V,
TC=125°C
200
Drain-Source On-State
Resistance(10)
RDS(ON)
VGS=10V, ID=0.5A
4.00
4.75
Ω
CISS
COSS
CRSS
td(on)
tr
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay
VGS=0V, VDS=25V, f=1MHz
VGS=0V, VDS=25V, f=1MHz
VGS=0V, VDS=25V, f=1MHz
VDD=350V, ID=1A
315
47
pF
pF
pF
ns
ns
ns
ns
9
11.2
34
Rise Time
VDD=350V, ID=1A
td(off)
tf
Turn-Off Delay
VDD=350V, ID=1A
28.2
32
Fall Time
VDD=350V, ID=1A
Control Section
fOSC
ΔfOSC
DMAX
DMIN
VSTART
VSTOP
IFB
Switching Frequency
Switching Frequency Variation(11)
92
100
±5
60
0
108
±10
650
0
kHZ
%
-25°C < TJ < 85°C
Maximum Duty Cycle
Measured at 0.1 x VDS
55
0
%
Minimum Duty Cycle
%
11
7
12
8
13
UVLO Threshold Voltage
VFB=GND
V
9
Feedback Source Current
Internal Soft-Start Time(11)
VFB=GND
VFB=4V
0.7
0.9
10
1.1
mA
ms
tS/S
Burst-Mode Section
VBURH
0.5
0.3
100
0.6
0.4
200
07
0.5
300
V
V
VBURL
Burst-Mode Voltage
TJ=25°C
VBUR(HYS)
mV
Protection Section
ILIM
tCLD
Peak Current Limit
Current Limit Delay(11)
Thermal Shutdown Temperature(11)
Shutdown Feedback Voltage
Over-Voltage Protection
di/dt=240mA/µs
0.97
1.10
500
140
6.0
1.23
A
ns
°C
V
TSD
125
5.5
18
VSD
6.5
6.5
VOVP
IDELAY
tLEB
19
V
Shutdown Delay Current
Leading-Edge Blanking Time(11)
VFB=4V
3.5
200
5.0
µA
ns
Total Device Section
Operating Supply Current
(Control Part Only)
IOP
VCC=14V
1
3
5
mA
ICH
Startup Charging Current
VSTR Supply Voltage
VCC=0V
VCC=0V
0.70
0.85
24
1.00
mA
V
VSTR
Notes:
10. Pulse test: Pulse width ≤ 300μs, duty ≤ 2%.
11. These parameters, although guaranteed, are not 100% tested in production.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
5
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.
Figure 4. Operating Frequency (fOSC) vs. TA
Figure 6. Maximum Duty Cycle (DMAX) vs. TA
Figure 8. Start Threshold Voltage (VSTART) vs. TA
Figure 5. Over-Voltage Protection (VOVP) vs. TA
Figure 7. Operating Supply Current (IOP) vs. TA
Figure 9. Stop Threshold Voltage(VSTOP) vs. TA
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
6
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.
Figure 10. Feedback Source Current (IFB) vs. TA
Figure 11. Startup Charging Current (ICH) vs. TA
Figure 12. Peak Current Limit (ILIM) vs. TA
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
7
Functional Description
1. Startup: In previous generations of Fairchild Power
Switches (FPS™), the Vstr pin required an external
resistor to the DC input voltage line. In this generation,
the startup resistor is replaced by an internal high-
voltage current source and a switch that shuts off 10ms
after the VCC supply voltage goes above 12V. The
source turns back on if VCC drops below 8V.
4. Protection Circuits: The FPS protective functions
include Overload Protection (OLP), Over-Voltage
Protection (OVP), Under-Voltage Lockout (UVLO), and
Thermal Shutdown (TSD). Because these protection
circuits are fully integrated inside the IC without external
components, reliability is improved without increasing
cost. Once a fault condition occurs, switching is
terminated and the SenseFET remains off. This causes
VCC to fall. When VCC reaches the UVLO stop voltage,
VSTOP (typically 8V); the protection is reset and the
internal high-voltage current source charges the VCC
capacitor via the Vstr pin. When VCC reaches the UVLO
start voltage, VSTART (typically 12V); the FPS resumes
normal operation. In this manner, the auto-restart can
alternately enable and disable the switching of the
power SenseFET until the fault condition is eliminated.
VIN,dc
ISTR
Vstr
VCC<8V
UVLO on
VCC
J-FET
ICH
10ms after
VCC
UVLO off
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding a pre-set level due to an
unexpected event. In this situation, the protection circuit
should be activated to protect the SMPS. However,
even when the SMPS is operating normally, the
Overload Protection (OLP) circuit can be activated
during the load transition. To avoid this undesired
operation, the OLP circuit is designed to be activated
after a specified time to determine whether it is a
transient situation or a true overload situation. In
conjunction with the Ipk current limit pin (if used), the
Current Mode feedback path would limit the current in
the SenseFET when the maximum PWM duty cycle is
attained. If the output consumes more than this
maximum power, the output voltage (VO) decreases
below its nominal voltage. This reduces the current
through the optocoupler LED, which also reduces the
optocoupler transistor current, thus increasing the
feedback voltage (VFB). If VFB exceeds 3V, the feedback
input diode is blocked and the 5µA current source
(IDELAY) starts to slowly charge Cfb up to VCC. In this
condition, VFB increases until it reaches 6V, when the
switching operation is terminated (as shown in Figure
15). The shutdown delay s the time required to charge
Cfb from 3V to 6V with 5µA current source.
12V
≥
Figure 13. Startup Circuit
2. Feedback Control: The 700V FPS series employs
Current Mode control, as shown in Figure 14. An
optocoupler (such as the H11A817A) and shunt
regulator (such as the KA431) are typically used to
implement the feedback network. Comparing the
feedback voltage with the voltage across the Rsense
resistor of SenseFET, plus an offset voltage, makes it
possible to control the switching duty cycle. When the
regulator reference pin voltage exceeds the internal
reference voltage of 2.5V; the optocoupler LED current
increases, feedback voltage Vfb is pulled down, and the
duty cycle is reduced. This typically occurs when the
input voltage increases or the output load decreases.
VCC
5µA
VCC
0.9mA
Vfb
VO
3
OSC
D1
D2
+
CFB
2.5R
R
VFB
V
FB,in
Gate
Driver
VFB
-
431
Overload Protection
6V
3V
OLP
VSD
Figure 14. Pulse Width Modulation (PWM) Circuit
3. Leading-Edge Blanking (LEB): When the internal
SenseFET is turned on; the primary-side capacitance
and secondary-side rectifier diode reverse recovery
t12= CFB (V(t )-V(t )) / I
DELAY
×
2
1
typically cause
a high current spike through the
SenseFET. Excessive voltage across the Rsense resistor
leads to incorrect feedback operation in the Current
Mode PWM control. To counter this effect, the FPS
employs a Leading-Edge Blanking (LEB) circuit to inhibit
the PWM comparator for a short time (tLEB) after the
SenseFET is turned on.
t1
t2
t
−
V (t2 ) V (t1)
=
= μ = =
; IDELAY 5 A, V (t1) 3V , V (t2 ) 6V
t12 CFB
IDELAY
Figure 15. Overload Protection (OLP)
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
8
4.2 Thermal Shutdown (TSD): The SenseFET and the
control IC are integrated, making it easier for the control
IC to detect the temperature of the SenseFET. If the
temperature exceeds approximately 140°C, thermal
shutdown is activated.
6. Burst Operation: To minimize power dissipation in
Standby Mode, the FPS enters Burst Mode. Feedback
voltage decreases as the load decreases and, as shown
in Figure 17, the device automatically enters Burst Mode
when the feedback voltage drops below VBURH (typically
600mV). Switching continues until the feedback voltage
drops below VBURL (typically 400mV). At this point,
switching stops and the output voltage starts to drop at a
rate dependent on the standby current load. This causes
4.3 Over-Voltage Protection (OVP): In the event of a
malfunction in the secondary-side feedback circuit or an
open feedback loop caused by a soldering defect, the
current through the optocoupler transistor becomes
almost zero (refer to Figure 14). Then, VFB climbs up in
a similar manner to the overload situation, forcing the
preset maximum current to be supplied to the SMPS
until the overload protection is activated. Because
excess energy is provided to the output, the output
voltage may exceed the rated voltage before the
overload protection is activated, resulting in the
breakdown of the devices in the secondary side. To
prevent this situation, an Over-Voltage Protection (OVP)
circuit is employed. In general, VCC is proportional to the
output voltage and the FPS uses VCC instead of directly
monitoring the output voltage. If VCC exceeds 19V, the
OVP circuit is activated, terminating switching. To avoid
undesired activation of OVP during normal operation,
the feedback voltage to rise. Once it passes VBURH
,
switching resumes. The feedback voltage then falls and
the process is repeated. Burst Mode alternately enables
and disables switching of the SenseFET and reduces
switching loss in Standby Mode.
Burst
Burst
Operation
Operation
Normal
Operation
VFB
VBURH
VBURL
Current
Waveform
VCC should be designed to be below 19V.
Switching
OFF
Switching
OFF
5. Soft-Start: The FPS internal soft-start circuit slowly
increases the SenseFET current after startup, as shown
in Figure 16. The typical soft-start time is 10ms, where
progressive increments of the SenseFET current are
allowed during the startup phase. The pulse width to the
power switching device is progressively increased to
Figure 17. Burst Operation Function
7. Adjusting Peak Current Limit: As shown in Figure
18, a combined 2.8kΩ internal resistance is connected
to the non-inverting lead on the PWM comparator. An
external resistance of Rx on the current limit pin forms a
parallel resistance with the 2.8kΩ when the internal
diodes are biased by the main current source of 900µA.
establish
the
correct
working
conditions
for
transformers, inductors, and capacitors. The voltage on
the output capacitors is progressively increased to
smoothly establish the required output voltage. This
helps to prevent transformer saturation and reduces the
stress on the secondary diode during startup.
VCC
VCC
PWM
Comparator
5µA
900µA
IDELAY
IFB
Vfb
Ω
2k
#6,7,8
5V
3
4
DRAIN
0.8kΩ
Ip
SenseFET
Current Sense
Rx
#1
Figure 18. Peak Current Limit Adjustment
GND
For example, FSQ0370 has a typical SenseFET peak
current limit (ILIM) of 1.1A. ILIM can be adjusted to 0.6A by
inserting Rx between the Ipk pin and the ground. The
value of the Rx can be estimated by:
ILIM
R
sense
(1)
(2)
1.1A: 0.6A = 2.8kΩ: XkΩ,
X = Rx || 2.8kΩ.
Figure 16. Soft-Start Function
where X represents the resistance of the parallel network.
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
9
Application Information
Reducing Audible Noise
Switching mode power converters have electronic and
magnetic components that generate audible noises
when the operating frequency is in the range of
20~20,000Hz. Even though they operate above 20KHz,
they can crease noise, depending on the load condition.
Three methods of reducing noise are discussed below:
Glue or Varnish
The most common method of reducing audible noise
includes using glue or varnish to tighten magnetic
components. The motion of core, bobbin, and coil as
well as the chattering or magnetostriction of core can
cause the transformer to produce audible noise. The
use of rigid glue and varnish reduces the transformer
noise. Glue or varnish can also crack the core because
sudden changes in the ambient temperature cause the
core and the glue to expand or shrink in a different ratio
according to the temperature.
Figure 19. Equal Loudness Curves
Ceramic Capacitor
Using a film capacitor instead of a ceramic capacitor as
a snubber capacitor is another noise reduction solution.
Some dielectric materials show a piezoelectric effect,
depending on the electric field intensity. A snubber
capacitor can become one of the most significant
sources of audible noise. Another possibility is to use a
Zener clamp circuit instead of an RCD snubber for
higher efficiency as well as lower audible noise.
Figure 20. Typical Feedback Network of FPS™
Adjusting Sound Frequency
Moving the fundamental frequency of noise out of
2~4KHz range is a third method. Generally, humans are
more sensitive to noise in the range of 2~4KHz. When
the fundamental frequency of noise is located in this
range, the noise sounds louder though the noise
intensity level is identical. Refer to Figure 19.
Reference Materials
AN-4134 — Design Guidelines for Offline Forward
Converters Using Fairchild Power Switch (FPS™)
AN-4137 — Design Guidelines for Offline Flyback
Converters Using Fairchild Power Switch (FPS™)
If Burst Mode is suspected as a source of noise, this
method may be helpful. If the frequency of Burst Mode
operation lies in the range of 2~4KHz, adjusting the
feedback loop can shift the burst operation frequency.
AN-4140 — Transformer Design Consideration for
Offline Flyback Converters Using Fairchild Power Switch
(FPS™)
To reduce burst operation frequency, increase
a
AN-4141 — Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
feedback gain capacitor (CF), optocoupler supply
resistor (RD), and feedback capacitor (CB) and decrease
a feedback gain resistor (RF) as shown in Figure 20.
AN-4147 — Design Guidelines for RCD Snubber of
Flyback Converters
AN-4148 — Audible Noise Reduction Techniques for
FPS Applications
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
10
Typical Application Circuit
Application
Output Power
Input Voltage
Output Voltage (Maximum Current)
PC Auxiliary Power Supply
(Using FSQ0270RNA)
Universal Input
15W
5V (3A)
(85-264VAC
)
Features
Key Design Notes
.
.
High efficiency (>78% at 115VAC and 230VAC input)
.
The delay for overload protection is designed to be
about 30ms with C8 of 47nF. If faster/slower
triggering of OLP is required, C8 can be changed to
a smaller or larger value (eg. 100nF for 60ms).
Low Standby Mode power consumption (<0.8W at
230VAC input and 0.5W load)
.
Enhanced system reliability through various
protection functions
.
ZP1, DL1, RL1, RL2, RL3, RL4, RL5, RL7, QL1,
QL2, and CL9 build a line Under-Voltage Lockout
block (UVLO). The Zener voltage of ZP1
determines the input voltage that turns the FPS on.
RL5 and DL1 provide a reference voltage from VCC
If the input voltage divided by RL1, RL2, and RL4 is
lower than the Zener voltage of DL1; QL1, and QL2
turn on and pull Vfb down to ground.
.
.
.
Low EMI through frequency modulation
Internal soft-start: 10ms
.
Line UVLO function can be achieved using external
components
.
An evaluation board and corresponding test report
can be provided. Contact a Fairchild representative.
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
11
Schematic
Figure 21. Demonstration Circuit
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
12
Transformer
EE2229
1
9, 10
2
3
4
5
Np/2
Np/2
6, 7
N5V
Na
Figure 22. Transformer Schematic Diagram
Table 2. Winding Specification
No.
Wire
0.3φ x 1
Turns
Winding Method
Pin (s→f)
3 → 2
Np/2
72
Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 1-Layer
Na
0.25φ x 2
22
8
Solenoid Winding
Solenoid Winding
Solenoid Winding
4 → 5
Insulation: Polyester Tape t = 0.0250mm, 2-Layer
N5V
6, 7 → 9, 10
0.65φ x 2
Insulation: Polyester Tape t = 0.025mm, 2-Layer
Np/2
0.3φ x 1
72
2 → 1
Insulation: Polyester Tape t = 0.025mm, 2-Layer
Table 3. Electrical Characteristics
Pin
Specification
1.20mH ± 5%
Remarks
100kHz, 1V
Inductance
Leakage
1 - 3
1 - 3
<30µH Maximum
Short All Other Pins
Core & Bobbin
. Core: EER2229 ( PL-7, 37.2mm2)
. Bobbin: BE2229
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
13
Table 4. Demonstration Board Part List
Part Number
Value
47nF
Quantity
Description (Manufacturer)
C6, C8
C1
2
1
1
1
Ceramic Capacitor
2.2nF (1KV)
1nF (200V)
1.5nF (50V)
AC Ceramic Capacitor(X1 & Y1)
Mylar Capacitor
C10
CS1
SMD Ceramic Capacitor
Low Impedance Electrolytic Capacitor KMX series (Samyoung
Electronics)
C2, C3
22µF (400V)
2
C4, C9
C5
1000µF (16V)
470µF (10V)
47µF (25V)
10µF (50V)
330µH
1µH
2
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
Low ESR Electrolytic Capacitor NXC series (Samyoung Electronics)
Low ESR Electrolytic Capacitor NXC series (Samyoung Electronics)
C7
General Electrolytic Capacitor
General Electrolytic Capacitor
Inductor
CL9
L1
L2
Inductor
R6
2.4 (1W)
0
Fusible Resistor
Jumper
J1, J2, J4, L3
R2
4.7kΩ
Resistor
R3
560Ω
Resistor
R4
100Ω
Resistor
R5
1.25kΩ
1.2kΩ
Resistor
R11
R9
Resistor
10kΩ
Resistor
R10
R14
RL3
RL1, RL2
RL4
RL5
RL7
RS1
ZR1
U1
2Ω
Resistor
30Ω
Resistor
1kΩ
Resistor
1MΩ
Resistor
120kΩ
30kΩ
Resistor
Resistor
40kΩ
Resistor
9Ω
Resistor
80Ω
SMD Resistor
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
IC (Fairchild Semiconductor)
FOD817A
TL431
FSQ0270RNA
2N2907
2N2222
U2
U3
QL1
QL2
D2, D3, D4, D5,
D6, DS1
1N4007
6
Diode (Fairchild Semiconductor)
D1
ZD1
DL1
ZP1
ZDS1
SB540
1N4745
1
1
1
1
1
Schottky Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
TVS (Fairchild Semiconductor)
1N5233
82V (1W)
P6KE180A
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
14
Layout
Figure 23. Top Image of PCB
Figure 24. Bottom of Image of PCB
© 2011 Fairchild Semiconductor Corporation
FSQ0370RNA / FSQ0370RLA • Rev. 1.0.2
www.fairchildsemi.com
15
10.00
9.10
A
B
7.62
0.56
0.36
2.54
2.00
8
5
6.60 9.90
6.20 9.30
6.70
10.70
4
1
1.09
0.94
0.56
0.10
1.252
1.784
1.62
1.47
M
0.10
C B A
0.56
0.36
M
C B A
LAND PATTERN RECOMMENDATION
TOP VIEW
7.62
A
3.60
3.20
3.70 MAX
0.10 C
2.54
7.62
0.35
0.20
C
0.10 MIN
SIDE VIEW
FRONT VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
A. NO INDUSTRY STANDARD APPLIES TO
THIS PACKAGE
9°
R0.20
R0.20
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-2009
GAGE PLANE
0.25
8°
0°
E. DRAWING FILENAME: MKT-MLSOP08Arev2
1.12
0.72
SEATING
PLANE
3°
1.60 REF
DETAIL A
SCALE 2:1
0.400 10.16
0.373 9.47
A
C
0.036 0.9 TYP
8
5
8
1
R0.032 0.813
PIN #1
0.092 2.337
PIN #1
0.255 6.48
0.245 6.22
C
1
4
B
D
0.070 1.78
0.045 1.14
TOP VIEW, OPTION 1
TOP VIEW, OPTION 2
0.320 8.13
7° TYP
0.300 7.62
7° TYP
0.135 3.43
0.125 3.18
0.210 5.33 MAX
0.015 0.381
0.010 0.254
C
0.060 1.52
MAX
0.015 0.38 MIN
0.140 3.56
0.125 3.17
0.300 7.62
0.100 2.54
0.021 0.53
0.43 10.92 MAX
0.015 0.38
0.001 [0.025]
FRONT VIEW
M
C
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS-001, VARIATION BA
B. CONTROLLING DIMENSIONS ARE IN INCHES.
REFERENCE DIMENSIONS ARE IN MILLIMETERS.
C
D
DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
0.010 INCHES OR 0.25MM.
DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED 0.010
INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M-2009
F. DRAWING FILENAME: MKT-N08Erev8
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