FSQ211 [ONSEMI]
用于 8W 离线反激转换器的 650V 集成电源开关;
| 型号： | FSQ211 |
| 厂家： | 
ONSEMI |
| 描述： | 用于 8W 离线反激转换器的 650V 集成电源开关 开关 电源开关 光电二极管 转换器 |
| 文件： | 总13页 (文件大小：834K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 2007
FSQ211
Green Mode Fairchild Power Switch (FPSTM)
Features
Description
The FSQ211 consists of an integrated Pulse Width
Modulator (PWM) and SenseFET, specifically designed
for high-performance, off-line Switch Mode Power
Supplies (SMPS) with minimal external components.
This device is an integrated high-voltage power
switching regulator that combines a VDMOS SenseFET
with a voltage mode PWM control block. The integrated
PWM controller features include a fixed oscillator, Under
Voltage Lockout (UVLO) protection, Leading Edge
Blanking (LEB), an optimized gate turn-on/turn-off
driver, Thermal Shutdown (TSD) protection, and
temperature compensated precision-current sources for
loop compensation and fault protection circuitry.
Internal Avalanche-Rugged SenseFET
Precision Fixed Operating Frequency (67KHz)
Burst-Mode Operation
Internal Start-up Circuit
Pulse-by-Pulse Current Limiting
Overload Protection (OLP)
Internal Thermal Shutdown Function (TSD)
Auto-Restart Mode
Under-Voltage Lockout (UVLO) with Hysteresis
Built-in Soft-Start
When compared to a discrete MOSFET and controller or
RCC switching converter solution, the FSQ211 device
reduces total component count and design size and
weight, while increasing efficiency, productivity, and
system reliability. This device provides a basic platform
well suited for cost-effective flyback converters.
Secondary-Side Regulation
Applications
Charger & Adapter for Mobile Phone, PDA, & MP3
Auxiliary Power for White Goods, PC, C-TV, &
Monitor
Related Application Notes
AN-4137 Design Guidelines for Off-line Flyback
Converters using FPS™
AN-4141 Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
AN-4147 Design Guidelines for RCD Snubber of
Flyback
AN-4134Design Guidelines for Off-line Forward
Converters using FPS™
AN-4138Design Considerations for Battery Charger
Using Green Mode Fairchild Power Switch (FPS™)
Ordering Information
Part Number
Package
Top Mark
Q211
BVDSS
650V
650V
fOSC
RDS(ON)
18Ω
FSQ211
FSQ211L
8DIP
8LSOP
67KHz
67KHz
Q211L
18Ω
FPSTM is a trademark of Fairchild Semiconductor Corporation
© 2007 Fairchild Semiconductor Corporation
FSQ211 Rev. 1.0.0
www.fairchildsemi.com
Typical Application
AC
IN
DC
OUT
Vstr
PWM
Vcc
Drain
Vfb
GND
Figure 1. Typical Flyback Application
Internal Block Diagram
Figure 2. Functional Block Diagram of FSQ211
© 2007 Fairchild Semiconductor Corporation
FSQ211 Rev. 1.0.0
www.fairchildsemi.com
2
Pin Assignments
Drain
Drain
Drain
Vstr
GND
Vcc
1
2
8
7
6
5
Vfb
NC
3
4
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin
Name
Description
1
GND
Ground. SenseFET source terminal on primary side and internal control ground.
Positive supply voltage input. Although connected to an auxiliary transformer winding,
current is supplied from pin 5 (Vstr) via an internal switch during startup (see Block Diagram). It
is not until VCC reaches the UVLO upper threshold (9V), that the internal start-up switch opens
and device power is supplied via the auxiliary transformer winding.
2
3
VCC
Feedback. Inverts input to the PWM comparator with its normal input level between 0.5V and
2.5V. It has a 0.4mA current source connected internally, while a capacitor and opto-coupler
are typically connected externally. A feedback voltage of 4.5V triggers overload protection
(OLP). There is a time delay while charging external capacitor CFB from 3V to 4.5V using an
internal 5µA current source. This time delay prevents false triggering under transient
conditions, but allows the protection mechanism to operate under true overload conditions.
VFB
4
5
NC
No Connection.
Start-up. This pin connects directly to the rectified AC line voltage source. At start-up, the
internal switch supplies internal bias and charges an external storage capacitor placed
between the VCC pin and ground. Once the VCC reaches 9V, the internal switch stops charging
the capacitor.
Vstr
SenseFET Drain. The drain pins are designed to connect directly to the primary lead of the
transformer and are capable of switching a maximum of 650V. Minimizing the length of the
trace connecting these pins to the transformer decreases leakage inductance.
6,7,8
Drain
© 2007 Fairchild Semiconductor Corporation
FSQ211 Rev. 1.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.
Symbol
VDRAIN
VSTR
VDG
Parameter
Value
650
Unit
V
Drain Pin Voltage
Vstr Pin Voltage
650
V
Drain-Gate Voltage
Gate-Source Voltage
Supply Voltage
650
V
VGS
±20
V
VCC
20
V
VFB
Feedback Voltage Range
Total Power Dissipation
-0.3 to VSTOP
1.40
V
PD
W
°C
°C
°C
TJ
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
Internally limited
-25 to +85
-55 to +150
TA
TSTG
Notes:
1. Repetitive rating: Pulse width is limited by maximum junction temperature.
2. L = 24mH, starting TJ = 25°C.
Thermal Impedance
TA=25°C unless otherwise specified.
Symbol
Parameter
Value
Unit
8DIP
θJA
θJC
Junction-to-Ambient Thermal Impedance(3)
Junction-to-Case Thermal Impedance(4)
89
14
°C/W
°C/W
Notes:
3. Free standing with no heatsink; without copper clad. Measurement condition – Just before junction temperature
TJ enters into OTP.
4. Measured on the DRAIN pin close to plastic interface.
5. All items are tested with the JEDEC standards: JESD 51-2 and 51-10 (DIP).
© 2007 Fairchild Semiconductor Corporation
FSQ211 Rev. 1.0.0
www.fairchildsemi.com
4
Electrical Characteristics
TA=25°C unless otherwise specified,
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
SENSEFET SECTION
VDS=650V, VGS=0V
25
IDSS
Zero-Gate-Voltage Drain Current
µA
VDS=520V, VGS=0V,
TC=125°C
200
RDS(ON)
gfs
Drain-Source On-State Resistance(6)
Forward Trans-Conductance
Input Capacitance
VGS=10V, ID=0.2A
VDS=50V, ID=0.2A
18
1.3
162
18
25
Ω
1.0
61
S
CISS
VGS=0V, VDS=25V,
f=1MHz
pF
COSS
CRSS
Output Capacitance
Reverse Transfer Capacitance
3.8
CONTROL SECTION
fOSC
ΔfOSC
DMAX
VSTART
VSTOP
IFB
Switching Frequency
Switching Frequency Variation(7)
67
±5
67
9
73
±10
74
KHz
%
-25°C ≤ TA ≤ 85°C
Maximum Duty Cycle
60
8
%
VFB=GND
10
V
UVLO Threshold Voltage
VFB=GND
6
7
8
V
Feedback Source Current
Internal Soft-Start Time
0V ≤ VFB ≤ 3V
0.35
10
0.40
15
0.45
20
mA
ms
tS/S
BURST-MODE SECTION
VBURH
0.6
0.7
0.55
150
0.8
V
V
TJ=25°C
Burst-Mode Voltage
VBURL
0.45
0.65
VBUR(HYS)
Hysteresis
mV
PROTECTION SECTION
ILIM
TSD
Peak Current Limit
di/dt= 65mA/µs
0.32
125
4.0
4
0.38
145
4.5
5
0.44
A
°C
V
Thermal Shutdown Temperature(8)
Shutdown Feedback Voltage
Shutdown Delay Current
VSD
5.0
6
IDELAY
3V ≤ VFB ≤ VSD
µA
TOTAL DEVICE SECTION
IOP Operating Supply Current (control part only) VCC ≤ 16V
ICH
Notes:
1.5
3.0
mA
µA
Start-Up Charging Current
VCC=0V , VSTR=50V
450
550
650
6. Pulse test: Pulse width ≤ 300us, duty ≤ 2%.
7. These parameters, although guaranteed, are tested in EDS (wafer test) process.
8. These parameters, although guaranteed, are not 100% tested in production.
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSQ211 Rev. 1.0.0
5
Typical Performance Characteristics
These characteristic graphs are normalized at TA = 25°C.
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-50
0
50
100
150
-50
0
50
100
150
Temperature [°C]
Temperature [°C]
Figure 4. Reference Voltage (VREF) vs. TA
Figure 5. Operating Supply Current (IOP) vs. TA
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-50
0
50
100
150
-50
0
50
100
150
Temperature [°C]
Temperature [°C]
Figure 6. Start Threshold Voltage (VSTART) vs. TA
Figure 7. Stop Threshold Voltage (VSTOP) vs. TA
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-50
0
50
100
150
-50
0
50
100
150
Temperature [°C]
Temperature [°C]
Figure 8. Operating Frequency (fOSC) vs. TA
Figure 9. Maximum Duty Cycle (DMAX) vs. TA
© 2007 Fairchild Semiconductor Corporation
FSQ211 Rev. 1.0.0
www.fairchildsemi.com
6
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA = 25°C.
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-50
0
50
100
150
-50
0
50
100
150
Temperature [°C]
Temperature [°C]
Figure 10. Peak Current Limit (ILIM) vs. TA
Figure 11. Feedback Source Current (IFB) vs. TA
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-50
0
50
100
150
-50
0
50
100
150
Temperature [°C]
Temperature [°C]
Figure 12. Shutdown Delay Current (IDELAY) vs. TA
Figure 13. Shutdown Feedback Voltage (VSD) vs. TA
© 2007 Fairchild Semiconductor Corporation
FSQ211 Rev. 1.0.0
www.fairchildsemi.com
7
2. Feedback Control: The FSQ211 is a voltage-mode
controlled device, as shown in Figure 16. Usually, an
opto-coupler and shunt regulator, like KA431, are used
to implement the feedback network. The feedback
voltage is compared with an internally generated
sawtooth waveform. This directly controls the duty cycle.
When the shunt regulator reference pin voltage exceeds
the internal reference voltage of 2.5V, the opto-coupler
LED current increases, the feedback voltage VFB is
pulled down, and it reduces the duty cycle. This
happens when the input voltage increases or the output
load decreases.
Functional Description
1. Start-up: At start-up, the internal high-voltage current
source supplies the internal bias and charges the
external VCC capacitor, as shown in Figure 14. In the
case of the FSQ211, when VCC reaches 9V, the device
starts switching and the internal high-voltage current
source stops charging the capacitor. The device is in
normal operation provided VCC does not drop below 7V.
After start-up, the bias is supplied from the auxiliary
transformer winding.
VIN,dc
ISTR
Vstr
OSC
Vcc
5µA
Vref
0.40mA
V
cc
L
Gate
driver
V
Vo
fb
4
+
C
H
fb
R
VFB
-
9V/7V
KA431
OLP
VSD
Figure 14. Internal Start-up Circuit
Figure 16. PWM and Feedback Circuit
Calculating the VCC capacitor is an important step in a
design with the FSQ211. At initial start-up, the maximum
value of start operating current ISTR is about 100µA,
which supplies current to UVLO and VREF blocks. The
charging current IVCC of the VCC capacitor is equal to ISTR
– 100µA. After VCC reaches the UVLO start voltage, only
the bias winding supplies VCC current to the device.
When the bias winding voltage is not sufficient, the VCC
level decreases to the UVLO stop voltage and the
internal current source is activated again to charge the
VCC capacitor. To prevent this VCC fluctuation
(charging/discharging), the VCC capacitor should be
chosen with a value between 10µF and 47µF.
3. Leading Edge Blanking (LEB): The instant the
internal SenseFET is turned on, the primary-side
capacitance and secondary-side rectifier diode reverse
recovery typically cause a high-current spike through the
SenseFET. Excessive voltage across the RSENSE resistor
leads to incorrect pulse-by-pulse current limit protection.
To avoid this, a leading edge blanking (LEB) circuit
disables the pulse-by-pulse current limit protection block
for a fixed time (tLEB) after the SenseFET turns on.
4. Protection Circuit: The FSQ211 has several
protective functions, such as overload protection (OLP),
under-voltage lockout (UVLO), and thermal shutdown
(TSD). Because these protection circuits are fully
integrated inside the IC without external components,
reliability is improved without increasing costs. Once a
fault condition occurs, switching is terminated and the
SenseFET remains off. This causes VCC to fall. When
VCC reaches the UVLO stop voltage VSTOP (7V), the
protection is reset and the internal high-voltage current
source charges the VCC capacitor via the Vstr pin. When
VCC reaches the UVLO start voltage VSTART (9V), the
device resumes normal operation. In this manner, the
auto-restart can alternately enable and disable the
switching of the power SenseFET until the fault
condition is eliminated.
V , dc
IN
ISTR
Vstr
IVcc = ISTR-ISTART
IVcc = ISTR-ISTART
J-FET
VCC
ISTART
UVLO
VREF
VCC
UVLO
VSTART
OSC
VCC must not drop
below VSTOP
VSTOP
S
R
Q
5µA
400µA
GATE
DRIVER
+
-
Bias winding
voltage
Vfb
4
R
Cfb
OLP
t
S
R
Q
Figure 15. Charging VCC Capacitor Through Vstr
4.5V
OLP, TSD
Protection Block
RESE T
TSD
A/R
Figure 17. Protection Block
© 2007 Fairchild Semiconductor Corporation
FSQ211 Rev. 1.0.0
www.fairchildsemi.com
8
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding a pre-set level due to an
unexpected event. In this situation, the protection circuit
should be activated to protect the SMPS. However,
even when the SMPS is operating normally, the over-
load protection (OLP) circuit can be activated during the
load transition. To avoid this undesired operation, the
OLP circuit is designed to be activated after a specified
time to determine whether it is a transient situation or an
overload situation. If the output consumes more than the
maximum power determined by ILIM, the output voltage
(VO) decreases below its rating voltage. This reduces
the current through the opto-coupler LED, which also
reduces the opto-coupler transistor current, thus
increasing the feedback voltage (VFB). If VFB exceeds
3V, the feedback input diode is blocked and the 5µA
current source (IDELAY) starts to charge CFB slowly up to
Drain current
ILIM
2.14ms
7steps
t
Figure 19. Internal Soft-Start
6. Burst Operation: To minimize the power dissipation
in standby mode, the FSQ211 enters burst mode
operation. As the load decreases, the feedback voltage
decreases. The device automatically enters burst mode
when the feedback voltage drops below VBURL (0.55V).
At this point, switching stops and the output voltages
start to drop. This causes the feedback voltage to rise.
Once is passes VBURH (0.70V), switching starts again.
The feedback voltage falls and the process repeats.
Burst mode operation alternately enables and disables
switching of the power MOSFET to reduce the switching
loss in the standby mode.
VCC. In this condition, VFB increases until it reaches
4.5V, when the switching operation is terminated, as
shown in Figure 18. Shutdown delay is the time required
to charge CFB from 3V to 4.5V with 5µA current source.
VFB
OverloadProtection
4.5V
OSC
GATE
DR IVER
S
R
Q
3V
5µA
400µA
4
on/off
Vfb
t12= CFB×(V(t2)-V(t1)) /IDELAY
0.70V
/0.55V
t1
t2
t
Burst Operation Block
V(t2)• V(t1)
IDELAY
Figure 20. Burst Operation Block
t12 =CFB
; IDELAY =5mA,V(t1) =3V,V(t2) =4.5V
V
Voset
o
Figure 18. Overload Protection (OLP)
4.2 Thermal Shutdown (TSD): The SenseFET and the
control IC are integrated, making it easier for the control
IC to detect the temperature of the SenseFET. When
the temperature exceeds approximately 145°C, thermal
shutdown is activated.
VFB
0.7V
0.55V
5. Soft-Start: The FPS has an internal soft-start circuit
that slowly increases the feedback voltage, together with
the SenseFET current, right after it starts up. The typical
soft-start time is 15ms, as shown in Figure 19, where
progressive increment of the SenseFET current is
allowed during the start-up phase. Soft-start circuit
progressively increases current limits to establish proper
working conditions for transformers, inductors,
capacitors, and switching device. It also helps prevent
transformer saturation and reduces the stress on the
secondary diode.
I
ds
V
ds
t
Figure 21. Burst Operation Function
© 2007 Fairchild Semiconductor Corporation
FSQ211 Rev. 1.0.0
www.fairchildsemi.com
9
Application Tips
Methods of Reducing Audible Noise
Switching mode power converters have electronic and
magnetic components that generate audible noises
when the operating frequency is in the range of
20~20,000Hz. Even though they operate above 20kHz,
they can make noise depending on the load condition.
Designers can employ several methods to reduce noise.
Glue or Varnish
The most common method involves using glue or
varnish to tighten magnetic components. The motion of
core, bobbin and coil, and the chattering or
magnetostriction of core, can cause the transformer to
produce audible noise. The use of rigid glue and varnish
helps reduce the transformer noise, but can crack the
core. This is because sudden changes in the ambient
temperature cause the core and the glue to expand or
shrink at a different rate.
Figure 22. Equal Loudness Curves
Ceramic Capacitor
Using a film capacitor instead of a ceramic capacitor as
a snubber capacitor is another noise-reduction option.
Some dielectric materials show a piezoelectric effect,
depending on the electric field intensity. Therefore, a
snubber capacitor becomes one of the most significant
sources of audible noise. It is possible to use a Zener
clamp circuit instead of an RCD snubber for higher
efficiency as well as lower audible noise.
Adjusting Sound Frequency
Moving the fundamental frequency of noise out of
2~4kHz range is the third method. Generally, humans
are more sensitive to noise in the range of 2~4kHz.
When the fundamental frequency of noise is located in
this range, the noise is perceived as louder, although
the noise intensity level is identical (refer to Figure 22
Equal Loudness Curves).
Figure 23. Typical Feedback Network of FPS™
Other Reference Materials
AN-4134: Design Guidelines for Off-line Forward
Converters Using Fairchild Power Switch
(FPS™)
When FPS acts in burst mode and the burst operation is
suspected to be a source of noise, this method may be
helpful. If the frequency of burst-mode operation lies in
the range of 2~4kHz, adjusting the feedback loop can
shift the burst operation frequency. To reduce the burst
operation frequency, increase a feedback gain capacitor
(CF), opto-coupler supply resistor (RD), and feedback
capacitor (CB), and decrease a feedback gain resistor
(RF), as shown in Figure 23.
AN-4137: Design Guidelines for Off-line Flyback
Converters Using Fairchild Power Switch
(FPS™)
AN-4138: Design Considerations for Battery Charger
Using Green Mode Fairchild Power Switch
(FPS™)
AN-4140: Transformer Design Consideration for Off-line
Flyback Converters Using Fairchild Power
Switch (FPS™)
AN-4141: Troubleshooting and Design Tips for Fairchild
Power Switch (FPS™) Flyback Applications
AN-4147: Design Guidelines for RCD Snubber of
Flyback
AN-4148: Audible Noise Reduction Techniques for
FPS™ Application
© 2007 Fairchild Semiconductor Corporation
FSQ211 Rev. 1.0.0
www.fairchildsemi.com
10
0.400 10.16
0.373 9.47
A
C
0.036 0.9 TYP
8
5
8
1
R0.032 0.813
PIN #1
0.092 2.337
PIN #1
0.255 6.48
0.245 6.22
C
1
4
B
D
0.070 1.78
0.045 1.14
TOP VIEW, OPTION 1
TOP VIEW, OPTION 2
0.320 8.13
7° TYP
0.300 7.62
7° TYP
0.135 3.43
0.125 3.18
0.210 5.33 MAX
0.015 0.381
0.010 0.254
C
0.060 1.52
MAX
0.015 0.38 MIN
0.140 3.56
0.125 3.17
0.300 7.62
0.100 2.54
0.021 0.53
0.43 10.92 MAX
0.015 0.38
0.001 [0.025]
FRONT VIEW
M
C
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS-001, VARIATION BA
B. CONTROLLING DIMENSIONS ARE IN INCHES.
REFERENCE DIMENSIONS ARE IN MILLIMETERS.
C
D
DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
0.010 INCHES OR 0.25MM.
DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED 0.010
INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M-2009
F. DRAWING FILENAME: MKT-N08Erev8
ON Semiconductor and
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