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March 2012

FSSD07

1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer

Features

Description

The FSSD07 is a 2:1 multiplexer that allows dual Secure

Digital (SD), Secure Digital I/O (SDIO), and Multimedia

Card (MMC) host controllers to share a common

peripheral. The host controllers can be equal to, greater

than, or less than peripheral card supply with minimal

power consumption. This configuration enables dual

host CMD, CLK, and D[3:0] signals to be multiplexed to

a common peripheral.

. On Resistance: 5Ω Typical, V_DDC=2.7V

. f_toggle: >75MHz

. Low On Capacitance: 6pF Typical

. Low Power Consumption: 2µA Maximum

. Supports Secure Digital (SD), Secure Digital I/O

(SDIO), and Multimedia Card (MMC) Specifications

The architecture includes the necessary bi-directional

data and command transfer capability for single high-

voltage cards or dual-voltage supply cards. The clock

path is a uni-directional buffer.

. Supports 1-Bit / 4-Bit Host Controllers (V_DDH1/H2=1.65V

to 3.6V) Communicating with

High-Voltage (2.7-3.6V) and Dual-Voltage Cards

(1.65-1.95V, 2.7-3.6V)

Typical applications involve switching in portables and

consumer applications: cell phones, digital cameras,

home theater monitors, set-top boxes, and notebooks.

-

V_DDC=1.65 to 3.6V, V_DDH1/H2=1.65 to 3.6V

.

24-Lead MLP and UMLP Packages

Applications

. Cell Phone, PDA, Digital Camera, Portable GPS, and

Notebook Computer

. LCD Monitor, TV, and Set-Top Box

Related Resources

.

FSSD07 Evaluation Board

Evaluation Board Users Guide

For samples, questions, or board requests; please

contact analogswitch@fairchildsemi.com

Figure 1. Analog Symbol Diagram

Ordering Information

Part

Number

Top

Operating

Packing

Package Description

Mark Temperature Range

Method

24-Lead Molded Leadless Package (MLP), JEDEC

MO-220, 3.5 x 4.5mm

Tape &

Reel

FSSD07BQX FSSD07

FSSD07UMX JK

-40°C to +85°C

24-Lead Ultra-thin Molded Leadless Package

(UMLP), 0.4mm pitch

Tape &

Reel

FSSD07 Rev. 1.0.2

www.fairchildsemi.com

Pin Configuration

2

1

24 23

24

23

22

21

20

19

DAT[2]

DAT[3]

22 VDDH1

21 1CLK

3

4

5

6

7

8

9

DAT[3]

CMD

18

1CLK

1

2

17

16

15

14

13

20

19

18

17

1DAT[0]

1DAT[1]

1DAT[0]

1DAT[1]

2DAT[2]

2DAT[3]

2CMD

CMD

VDDC

GND

VDDC

GND

3

4

2DAT[2]

CLK

5

6

2DAT[3]

2CMD

DAT[0]

16

15

DAT[0]

DAT[1] 10

VDDH2

11 12 13 14

11

7

9

12

10

8

Figure 2.

MLP Pin Assignments

Figure 3.

UMLP Pin Assignments

Description

Pin Definitions

Pin# MLP Pin# UMLP

Name

1

2

22

23

24

1

1DAT[2]

OE

SDIO Common Port

Output Enable (Active HIGH)

3

DAT[2]

DAT[3]

CMD

4

SDIO Common Port

5

2

6

3

VDDC

GND

Power Supply (SDIO Peripheral Card Port)

7

4

Ground

8

5

CLK

Clock Path Port

9

6

DAT[0]

DAT[1]

S

SDIO Common Port

Select Pin

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

7

8

9

2DAT[1]

2DAT[0]

2CLK

Host Common Port

10

11

12

13

14

15

16

17

18

19

20

21

Clock Path Port

VDDH2

2CMD

2DAT[3]

2DAT[2]

1DAT[1]

1DAT[0]

1CLK

Power Supply (Host Port)

Host Common Port

Clock Path Port

VDDH1

1CMD

1DAT[3]

Power Supply (SDIO Host Port)

Host Common Port

Truth Table

OE

S

Function

HIGH

LOW

LOW 1CMD, 1CLK, 1DAT[3:0] connected to CMD, CLK, DAT[3:0]

HIGH 2CMD, 2CLK,2DAT[3:0] connected to CMD, CLK, DAT[3:0]

X

CMD, DAT[3:0] ports high impedance; CLK is function of selected nCLK

FSSD07 Rev. 1.0.2

www.fairchildsemi.com

2

Typical Application

VDDC

VDDH1

1.65V to 3.6V

R_CMD, R_DAT[3:0]

FSSD07

1.65V to 3.6V

CMD, DAT[3:0]

5

1CMD, 1DAT[3:0]

5

WiFi,

Bluetooth,

MMC or SD

Peripheral

Processor #1

1CLK

CLK

Secure Data/

Multi Media Card

Dual Host Selector

VDDH2

1.65V to 3.6V

SD Card

R_{1CMD, 2CMD}= 10k to 100k ohm

R_{1DAT[3:0] 2DAT[3:0]}= 10k to 100k ohm

,

2CMD, 2DAT[3:0]

5

MMC Card

R_{1CMD, 2CMD}= 4.7k to 100k ohm

_{1DAT[3:0], 2DAT[3:0]}= 50k to 100k ohm

Processor #2

R

2CLK

OE

S

GND

Figure 4. Typical Application Diagram

FSSD07 Rev. 1.0.2

www.fairchildsemi.com

3

Functional Description

The FSSD07 enables the multiplexing of dual ASIC /

baseband processor hosts to a common peripheral card

or module, providing bi-directional support of the dual-

voltage SD/SDIO or MMC cards available in the

marketplace. Each host SDIO port has its own supply

rail, such that hosts with different supplies can be

interfaced to a common peripheral module or card. The

peripheral card supply must be equal to or greater than

the host(s) to minimize power consumption. The

independent V_DDC, V_DDH1, and V_DDH2are defined by the

supplies connected from the application Power

Management ICs (PMICs) to the FSSD07. The clock

path is a uni-directional buffered path rather than a bi-

directional switch port. The supplies (V_DDC, V_DDH1, and

IDLE State & Power-Up CMD/DAT Bus

“Parking”

The SD and MMC card specifications were written for a

direct point-to-point communication between host

controller and card. The introduction of the FSSD07 in

that path, as an expander, requires that the functional

operation and system latency not be impacted by the

switch characteristics. Since there are various card

formats, protocols, and configurable controllers, an OE

pin is available to facilitate a fast IDLE transition for the

CMD/DAT[3:0] outputs. Some controllers, rather than

placing CMD/DAT into high-impedance mode, pull the

outputs HIGH for a clock cycle prior to going into high-

impedance mode (referred to as “parking” the output).

Some legacy controllers pull their outputs HIGH versus

high impedance.

V_DDH2) have an internal termination resistor (typically

3M) to ensure the supply rails internally do not float if

the application turns off one or all of these sources.

If the OE pin is pulled HIGH and the controller places its

command and data outputs into high-impedance (driving

nCMD/nDAT[3:0]), the FSSD07 CMD/DAT[3:0] output

rise time is a function of the RC time constant through

the switch path. Pulling OE LOW puts the switches into

high impedance, disabling communication from the host

to card, and the CMD/DAT[3:0] outputs are pulled HIGH

by the system pull-up resistors chosen for the

application. This mechanism facilitates power-up

sequencing by holding OE LOW until supplies are stable

and communication between the host(s) and card is

enabled.

CMD, DAT Bus Pull-ups

The CMD and DAT[3:0] ports do not have, internally, the

system pull-up resistors as defined in the MMC or SD

card system bus specifications. The system bus pull-up

must be added external to the FSSD07. The value,

within the specific specification limits, is a function of the

individual application and type of card or peripheral

connected. For SD card applications, the R_CMDand R_DAT

pull-ups should be between 10kΩ and 100kΩ. For MMC

applications, the R_CMDpull-ups should be between

4.7kΩ and 100kΩ, and the R_DATpull-ups between 50kΩ

and 100kΩ. The card-side CMD and DAT[3:0] outputs

have a circuit that facilitates incident wave switching, so

the external pull-up resistors ensure retention of the

output high level.

Power Optimization

Since the FSSD07 has multiple supplies (V_DDC, V_DDH1

,

and V_DDH2), the control signals have been referenced to

the card peripheral side (V_DDC). To minimize power

consumption, current paths between supplies are

isolated when one or more supplies are not present.

This includes the configuration of the removal of V_DDC

with host controller supplies remaining present.

The OE pin can be used to place the CMD and DAT[3:0]

into high-impedance mode during power-up sequencing

or when the system enters IDLE state (see IDLE State

CMD/DAT Bus “Parking”).

CLK Bus

The 1CLK and 2CLK inputs are bi-state buffer

architectures, rather than a switch I/O, to ensure 52MHz

incident wave switching. Since most host controllers

also have a clock enable register bit to enable or disable

the system clock when in IDLE mode, the CLK output is

not disabled by the OE pin. Instead, the CLK output is a

function of whichever host controller clock is selected by

the S pin.

Consequently, there is always a clock path connected

between the selected host and the card. The state of the

CLK pin is a function of the selected host controller

nCLK output pin, which facilitates retaining clock duty

cycle in the system or performing read / wait operations.

FSSD07 Rev. 1.0.2

www.fairchildsemi.com

4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Card Supply Voltage

Conditions

Min.

-0.5

Max.

4.6

Unit

V

V_DDC

V_DDH1,V_DDH2Host Controller Supply Voltage

4.6

V

1DAT[3:0], 2DAT[3:0],

1CMD, 2CMD Pins

V_DDx⁽²⁾+ 0.3V

(4.6V maximum)

V_DDx⁽²⁾+ 0.3V

(4.6V maximum)

-0.5

V

V_SW

Switch I/O Voltage⁽¹⁾

DAT[3:0], CMD Pins

V_CNTRL

V_CLKI

Control Input Voltage⁽¹⁾

CLK Input Voltage ⁽¹⁾

S, OE

-0.5

4.6

V

1CLK, 2CLK

V_DDx⁽²⁾+ 0.3V

(4.6V maximum)

V_CLKO

CLK Output Voltage⁽¹⁾

CLK

-0.5

V

I_INDC

I_SW

Input Clamp Diode Current

Switch I/O Current

-50

50

mA

SDIO Continuous

SDIO Pulsed at 1ms

Duration, <10% Duty Cycle

I_SWPEAK

Peak Switch Current

100

mA

T_STG

T_J

Storage Temperature Range

Maximum Junction Temperature

Lead Temperature

-65

+150

+260

8

C

T_L

Soldering, 10 Seconds

I/O to GND

Human Body Model,

JEDEC: JESD22-A114

Supply to GND

All Other Pins

10

kV

ESD

5

Charged Device Model, JEDEC-JESD-C101

2

Notes:

1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed.

2. _DDxreferences the specific SDIO port V_DDrail (i.e. V_DDH1, V_DDH2, V_DDC).

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Supply Voltage - Card Side

Min.

1.65

0

Max.

3.60

Unit

V

V_DDC

V_DDH1,V_DDH2Supply Voltage - Dual Host Controller

3.60

V

V_CNTRL

V_CLKI

Control Input Voltage - V_S, V_OE

Clock Input Voltage - V_CLKI

V_DDC

V_DDH1/H2

V_DDC

V_DDH1

V_DDH2

+85

V

0

V

CMD, DAT[3:0]

0

V

V_SW

Switch I/O Voltage

1CMD, 1DAT[3:0]

2CMD, 2DAT[3:0]

0

V

0

V

T_A

Operating Temperature

-40

°C

°C/W

Thermal Resistance, Free Air

MLP Package

+50

_JA

FSSD07 Rev. 1.0.2

www.fairchildsemi.com

5

DC Electrical Characteristics at 1.8V V_DDC

All typical values are for V_DDC=1.8V at 25°C unless otherwise specified.

T_A=-40 to +85°C

V_DDC

(V)

V_DDH1/

V_DDH2(V)

Symbol

Parameter

Conditions

Unit

Min. Typ. Max.

Common Pins

V_IK

V_IH

Clamp Diode Voltage

1.80

I_IK=-18mA

-1.2

V

Control Input Voltage

High

1.3

Control Input Voltage

Low

V_IL

I_IN

1.80

1.95

1.65

1.80

1.95

1.65

0.5

V

µA

V

S, OE Input High

Current

V_CNTRL=0V to V_DDC

V_SW=0V to V_DDC

I_OH=-2mA

-1

1

Off Leakage, Current of

all ports

I_OZ

-1.0

1.6

0.5

1.0

CLK Output Voltage

High⁽³⁾

V_OHC

V_OLC

CLK Output Voltage

Low⁽³⁾

I_OL=-2mA

90

10

mV

V_{CMD, DAT[3:0]}=0V,

R_ON

Switch On Resistance⁽⁴⁾

Delta On Resistance^{(3, 5)}

1.65

I

_ON=-2mA

ꢀ

Figure 5

V_{CMD, DAT[3:0]}=0V,

∆R_ON

0.85

I

_ON=- 2mA

Power Supply

Quiescent Supply

Current (Card)

I_CC(VDDC)

1.95

0

V_SW=0 or V_DDC, I_OUT=0

V_SW=0 or V_DDx,I_OUT=0,

2

µA

Quiescent Supply

Current (Hosts)

I_CC(VDDH1/H2)

1.95

V_CLKI=V_DDHX,

V_CLKO=Open, OE=V_DDC

V

_SW=0 or V_DDx,I_OUT=0,

Delta I_{CC(VDDH1, VDDH2)}for

One Host Powered Off

1.95 / 0

0 / 1.95

∆I_HOST

1.95

_CLKI=V_DDHX

,

2

µA

_CLKO=Open, OE=V_DDC

Notes:

3. Guaranteed by characterization, not production tested.

4. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the

switch.

5. ∆ R_ON=R_{ON max}– R_{ON min}measured at identical V_CC, temperature, and voltage.

FSSD07 Rev. 1.0.2

www.fairchildsemi.com

6

DC Electrical Characteristics at 2.7V V_DDC

All typical values are for V_DDC=2.7V at 25°C unless otherwise specified.

T_A=-40 to +85°C

V_DDH1

V_DDH2(V)

/

Symbol

Parameter

V_DDC(V)

Conditions

Unit

Min.

Typ. Max.

Common Pins

V_IK

V_IH

Clamp Diode Voltage

2.7

I_IK=-18mA

-1.2

Control Input Voltage

High

1.8

V

Control Input Voltage

Low

V_IL

I_IN

2.7

3.6

2.7

3.6

0.8

1

S, OE Input High Current

V_CNTRL=0V to V_DDC

V_SW=0V to V_DDC

-1

µA

Off Leakage Current of

all Ports

I_OZ

-1.0

0.5

1.0

CLK Output Voltage

High⁽⁶⁾

V_OHC

V_OLC

2.7

3.6

2.7

3.6

I_OH=-2mA

2.4

V

CLK Output Voltage

Low⁽⁶⁾

I_OL=-2mA

90

mV

V_{CMD, DAT[3:0]}=0V,

R_ON

Switch On Resistance⁽⁷⁾

Delta On Resistance^{(6, 8)}

2.7

I

_ON=-2mA

5.0

0.8

8.0

ꢀ

Figure 5

V_{CMD, DAT[3:0]}=0V,

∆R_ON

I

_ON=- 2mA

Power Supply

Quiescent Supply Current

(Card)

I_CC(VDDC)

3.6

0

V_SW=0 or V_DDC, I_OUT=0

V_SW=0 or V_DDx,I_OUT=0,

2

µA

I_CC

(VDDH1/C2)

Quiescent Supply Current

(Hosts)

3.6

V_CLKI=V_DDHX, V_CLKO=Open,

OE=V_DDC

V

_SW=0 or V_DDx,I_OUT=0,

Delta I_{CC(VDDH1, VDDH2)}for

One Card Powered Off

3.6 / 0

0 / 3.6

∆I_HOST

3.6

V_CLKI=V_DDHX, V_CLKO=Open,

2

µA

OE=V_DDC

Notes:

6. Guaranteed by characterization, not production tested.

7. On resistance is determined by the voltage drop between the switch I/O pins at the indicated current through the

switch.

8. ∆ R_ON=R_{ON max}– R_{ON min}measured at identical V_CC, temperature, and voltage.

FSSD07 Rev. 1.0.2

www.fairchildsemi.com

7

AC Electrical Characteristics at 1.8V V_DDC

All typical values are for V_DDC=1.8V at 25°C unless otherwise specified.

T_A=-40 to +85°C

Min. Typ. Max.

V_DDH1

V_DDH2(V)

/

Symbol

Parameter

V_DDC(V)

Conditions

Unit

V_SW=0V, R_L=1kꢀ,

1.65 to 1.95 1.65 to 3.6 C_L=20pF

Figure 7, Figure 8

Turn-On Time,

S, OE to CMD, DAT[3:0]

t_ON

8

6

18

13

ns

V_SW=0V, R_L=1kꢀ,

1.65 to 1.95 1.65 to 3.6 C_L=20pF

Turn-Off Time,

S, OE to CMD, DAT[3:0]

t_OFF

ns

Figure 7, Figure 8

R_L=1kꢀ, C_L=20pF

1.65 to 1.95 1.65 to 3.6 (10-90%)

t_RISE1/

FALL1

CMD/DAT Output Edge Rates⁽⁹⁾

Switch Propagation Delay⁽⁹⁾

3

4.5

4

ns

Figure 7, Figure 8

R_L=1kꢀ, C_L=20pF

Figure 7, Figure 89

t_PD

1.65 to 1.95 1.65 to 3.6

9

6

C_L=20pF

LH Propagation Delay 1CLK, 2CLK

to CLK

t_pLH

1.65 to 1.95 1.65 to 3.6 Figure 10, Figure

11

C_L=20pF

HL Propagation Delay 1CLK, 2CLK

to CLK

t_pHL

1.65 to 1.95 1.65 to 3.6 Figure 10, Figure

11

4

3

6

ns

dB

t_RISE2/

FALL2

C_L=20pF (10-90%)

1.65 to 1.95 1.65 to 3.6

CLK Output Edge Rates⁽⁹⁾

Figure 7, Figure 8

f=10MHz, R_T=50ꢀ,

O_IRROff Isolation⁽⁹⁾

1.8

1.65 to 3.6 C_L=20pF,

Figure 12

-60

f=10MHz, R_T=50ꢀ,

1.65 to 3.6 C_L=20pF,

Figure 13

Xtalk Non-Adjacent Channel Crosstalk⁽⁹⁾

f_toggleClock Frequency⁽⁹⁾

1.8

-60

75

dB

1.65 to 3.6 C_L=20pF

MHz

Note:

9. Guaranteed by characterization, not production tested.

www.fairchildsemi.com

FSSD07 Rev. 1.0.2

8

AC Electrical Characteristics at 3.3V V_DDC

All typical values are for V_DDC=3.3V at 25°C unless otherwise specified.

T_A=-40 to +85°C

V_DDH1/ V_DDH2

Symbol

Parameter

V_DDC(V)

Conditions

Unit

(V)

Min. Typ. Max.

V_SW=0V, R_L=1kꢀ,

1.65 to 3.6 C_L=20pF

Figure 7, Figure 8

Turn-On Time,

S, OE to CMD, DAT[3:0]

t_ON

2.7 to 3.6

8

6

3

18

13

ns

V_SW=0V, R_L=1kꢀ,

1.65 to 3.6 C_L=20pF

Turn-Off Time,

S, OE to CMD, DAT[3:0]

t_OFF

2.7 to 3.6

ns

Figure 7, Figure 8

R_L=1kꢀ, C_L=20pF (10-

1.65 to 3.6 90%)

t_RISE1/

FALL1

CMD/DAT Output Edge

Rates⁽¹⁰⁾

Figure 7, Figure 8

Switch Propagation

Delay⁽¹⁰⁾

R_L=1kꢀ, C_L=20pF

Figure 7, Figure 8

t_PD

t_pLH

t_pHL

2.7 to 3.6

1.65 to 3.6

2.5

4

6

ns

LH Propagation Delay

1CLK, 2CLK to CLK

C_L=20pF

Figure 10, Figure 11

HL Propagation Delay

1CLK, 2CLK to CLK

C_L=20pF

Figure 10, Figure 11

4

t_RISE2/

FALL2

CLK Output Edge

Rates⁽¹⁰⁾

C_L=20pF (10-90%)

Figure 7, Figure 8

3

f=10MHz, R_T=50ꢀ,

1.65 to 3.6 C_L=20pF

Figure 12

O_IRR

Off Isolation⁽¹⁰⁾

2.7

-60

dB

f=10MHz, R_T=50ꢀ,

1.65 to 3.6 C_L=20pF,

Figure 13

Non-Adjacent Channel

Crosstalk⁽¹⁰⁾

Xtalk

2.7

-60

75

dB

f_toggle

Clock Frequency⁽¹⁰⁾

1.65 to 3.6 C_L=20pF

MHz

Note:

10. Guaranteed by characterization, not production tested.

Capacitance

T_A=-40 to +85°C

Min. Typ. Max.

V_DDCV_DDH1/H2

Symbol

Parameter

Conditions

Unit

(V)

C_{IN(S, OE,}Control and nCLK Pin

CLK)

0

2.7

V

_DDC=0V

2.5

7.5

4

pF

Input Capacitance⁽¹¹⁾

Common Port On

V_OE=V_DDC, V_bias=0.5V, f=1MHz

Figure 14

C_ON

Capacitance⁽¹¹⁾

2.7

pF

(C_{DAT[3:0], CMD}

)

Input Source Off

Capacitance⁽¹¹⁾

V_OE=0V, V_bias=0.5V, f=1MHz

Figure 15

C_OFF

Note:

11. Guaranteed by characterization, not production tested.

www.fairchildsemi.com

FSSD07 Rev. 1.0.2

9

Test Diagrams

V_ON

I_OZ

NC

nDAT[3:0],nCMD

A

DAT[3:0],CMD

V

IN

V

IN

Select

I_ON

GND

Select

V

= 0 or V

DDH

GND

S

V

DDH

_S= 0 or

Each switch port tested separately.

R

_ON= V_ON/ I_ON

Figure 5. On Resistance

Figure 6. Off Leakage

t_RISE= 2.5ns

t_FALL= 2.5ns

V_ddx

V

DDx

90%

Input - V_CNTRL

V_ddx/2

V

_ddx/2

DAT[3:0],

CMD

nDAT[3:0],nCMD

10%

50%

GND

R

L

V_OH

Output - V_OUT

V_OL

V

SW

V_OUT

C

L

R

GND

S

V_OL

+ 0.15V

t_ON

GND

t_OFF

V

S

GND

V_OH

R_L, R_S, and C_Lare functions of the application

environment (see AC tables for specific values).

C_Lincludes test fixture and stray capacitance.

Output - V_OUT

50%

t_ON

V

_OL+ 0.15V

V_OL

t_OFF

Figure 7. AC Test Circuit Load

Figure 8. Turn On/Off Time Waveforms

t_RISE= 2.5ns

t_FALL= 2.5ns

1CLK, 2CLK

CLK

V

ddx

V

90%

V_ddx/2

90%

CLKI

V_OUT

Input- V_SW

10%

V_ddx/2

C

L

R

GND

S

10%

50%

GND

V_OH

V

S

Output- V_OUT

V_OL

50%

t_pLH

GND

R_L, R and C_Lare function of application

S

environment (see AC Tables for specific

values)

t_pHL

C_Lincludes test fixture and stray capacitance

Figure 9. Switch Propagation Delay (t_PD) Waveform

Figure 10. AC Test Circuit Load (CLK)

FSSD07 Rev. 1.0.2

www.fairchildsemi.com

10

Test Diagrams (Continued)

t

_FALL= 2.5ns

_RISE= 2.5ns

Network Analyzer

V

R

S

ddx

90%

V_ddx/2

90%

_ddx/2

V

IN

Input- V

V

S

GND

CLKI

R

T

V

10%

50%

GND

V

GND

S

GND

V

OUT

GND

V_OHC

GND

R

T

R_Sand R_Tare functions of the application

environment (see AC tables for specific values).

GND

Output -V

OUT

50%

t_pLH

Off Isolation = 20 Log (V_OUT/ V_IN

)

V_OL

t_pHL

Figure 11. CLK Propagation Delay Waveforms

Figure 12. Channel Off Isolation

Network Analyzer

NC

R

S

V

IN

V

GND

S

GND

V

S

GND

R

T

GND

V

OUT

GND

R

T

R_Sand R_Tare functions of the application environment

(see AC tables for specific values).

GND

Crosstalk = 20 Log (V_OUT/ V_IN

)

Figure 13. Channel-to-Channel Crosstalk

nDAT[3:0], nCMD, nCLK

Capacitance

Meter

S

Capacitance

Meter

V

= 0 orV

ddh

S

V

_S= 0 orV_ddh

f = 1MHz

nDAT[3:0], nCMD, nCLK

f = 1MHz

nDAT[3:0], nCMD, nCLK

Figure 14. Channel On Capacitance

Figure 15. Channel Off Capacitance

FSSD07 Rev. 1.0.2

www.fairchildsemi.com

11

2.50±0.10

A

B

0.663

0.400

19

24

PIN#1

IDENT

0.563

1

18

2.225 3.700

13

3.40±0.10

6

0.225

7

12

TOP VIEW

2.225

2.800

0.025±0.025

0.50±0.05

LAND PATTERN RECOMMENDATION

0.50±0.05

SEATING PLANE

C

SIDE VIEW - OPTION A

0.10±0.05

0.50±0.05

SEATING PLANE

45°

0.20±0.05

C

0.025±0.025

SIDE VIEW - OPTION B

DETAIL A

0.05

SCALE 2:1

(0.15) 4X

POTENTIAL

PULL BACK

NOTES:

7

12

A. PACKAGE DOES NOT FULLY CONFORM

TO JEDEC STANDARD

B. ALL DIMENSIONS ARE IN MILLIMETERS

C. LAND PATTERN RECOMMENDATION IS

EXISTING INDUSTRY LAND PATTERN

D. DRAWING FILENAME: MKT-UMLP24ArevE

6

13

18

0.40

DETAIL A

1

PIN#1

IDENT

0.40±0.05 (23X)

24

19

0.20±0.05 (24X)

0.10 C A B

0.05 C

0.85

BOTTOM VIEW

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1


型号：	FSSD07UMX
厂家：	ONSEMI
描述：	1 位/4 位 SD/SDIO 和 MMC 双主机多路复用器复用器
文件：	总15页 (文件大小：488K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FSSD07UMX [ONSEMI]

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