FUSB3317F6AMNWTWG [ONSEMI]
Integrated Automotive USB Power Delivery Source Controller;
| 型号： | FUSB3317F6AMNWTWG |
| 厂家： | 
ONSEMI |
| 描述： | Integrated Automotive USB Power Delivery Source Controller |
| 文件： | 总16页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Automotive USB Power
Delivery Source Controller
for USB-Ct
QFNW20 4x4, 0.5P
CASE 484AT
FUSB3317
MARKING DIAGRAM
FUSB3317 is a highly integrated USB Power Delivery (PD) power
Source controller for USB−C that implements all functionality of USB
Power Delivery 3.1 (PD) and Type−Ct 2.0 including Programmable
Power Supplies (PPS). The FUSB3317 directly interfaces with a
DC−DC regulator saving the cost of a load switch FET.
1
3317
V6A
ALYWG
FUSB3317 supports various protections, adaptive Under Voltage
Protection (UVP), adaptive Over Voltage Protection (OVP), Over
Current Protection (OCP), CC1 and CC2 Over Voltage Protection
(CC_OVP), D+ and D− Over Voltage Protection (D_OVP), VCONN
Over Current Protection (VCONN_OCP), and internal and external
Over Temperature protection (I_TOP and E_OTP).
FUSB3317V6A = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
Features
ORDERING INFORMATION
See detailed ordering and shipping information on page 14 of
this data sheet.
• PD 3.1 v1.0 and Type−C 2.0 Compliant
• Constant Voltage (CV) and Constant Current Limit (CL) Regulation
• Small Current Sensing Resistor (5 mW) for High Efficiency
• Directly Off Automotive Battery 4 V to 45 V Operation, Iq < 100 mA
• CC1/CC2/D+/D− Pin Protection Up to 27 V
• Automatically Scales Power Based on VBAT & NTC Temperature
• Resistor Divider or Battery Charging (BC1.2) CDP Mode
• Internal VDD and VCONN Generation
• Adaptive UVP, Adaptive OVP, I_OTP, E_OTP, CC_OVP, D_OVP
and VCONN_OCP Fault Detection
• 20−pin 4 mm x 4 mm QFNW (Wettable Flanks) Package
• This is a Pb−Free Device
Typical Applications
• Power Delivery Source Controller
• DC−DC Controller Interface to USB−C Connector
End Products
• Automotive USB−C Charging Only Port
• Automotive USB−C Data and Charging Port
• Mobile and Computing Multi−Port Adapters
• Industrial Charging USB PD Ports
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
May, 2022 − Rev. 0
FUSB3317/D
FUSB3317
Figure 1. Application Schematic – Automotive DC/DC Reference Design Example
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2
FUSB3317
Block Diagram
VDD
DISC
D−
VBAT
DC_EN
VBUS
D+
vdd
vbus
GND
DON
Resistor Divider &
BC 1.2 DCP & CDP
Power Enable
vdd
vdd
GND
CC1
VIN−ON
VIN−OFF
/
9R
R
Discharge
FAULT
VCS−AMP
Trigger
_BLD
RESET
Protection
CC2
CVCC
_mode
vdd
BATUV
CC State Machine &
Comparators
vdd
1.1V REG
IFB
IS+
X AVCCR
R c v r
B M C
VCS−AMP
Cable Drop
Compensation
FAULT
VCOMR
IS−
Policy
Engine
(+Timers)
VCCR
vdd
BMC
DRIVER
Prote
ction
CRC32
Tx
VFB
vdd
BMC
Encode
S
4B5B
4B5B
CDR
Device
Policy
Manage
r (DPM)
State
Protocol
(+Timers)
Protection
Block
VCVR
PDIV1
PDIV0
VIN−1:10
OVP/UVP/
OCP
BMC
Decode
Mode_
change
FAULT Machine
CRC32
Rx
VUVP
V
vdd
OVP VCOMR
vbus
Optional
Polarity
Change
Protection
VCS−AMP
VIN−1:10
Internal temp.
Band
Gap
Analog to Digital
Converter
NTC
LF
Osc.
PD
Osc.
Trim
CATH
(FB)
Figure 2. Simplified Block Diagram
Pin Connections
20
19
18
17
16
16
17
18
19
20
D+
DC_EN
NTC
NTC DC_EN PDIV0 VDD
D+
D−
VDD PDIV0
1
2
3
4
5
1
2
3
4
5
D−
15
14
13
12
11
PDIV 1
PDIV 1 15
FUSB3317
FUSB3317
QFNW20
QFNW20
VBAT
VBAT
14
13
12
11
DISC
GND
DISC
CC1
CC1
GND
GND
GND
CATH
(FB)
CATH
(FB)
BATUV
BATUV
CC2
IS+
6
CC2
IS+
6
VBUS
DON
10
VBUS
VFB
8
IFB
9
VFB
8
IS−
IS−
IFB
9
DON
10
7
7
Top View
Bottom View
Figure 3. Pinout Diagrams
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3
FUSB3317
PIN FUNCTION DESCRIPTION
Pin No. Pin Name
I/O Type
Description
11
VBUS
VBAT
VDD
Input
Output VBUS voltage to the Type C connector (Input voltage to the FUSB3317 to check for
OVP and UVP)
2
Supply
Output
Ground
Input power for the FUSB3317 directly from a battery for automotive applications or from
a DC−DC supply for industrial
19
Supply voltage generated internally from VBAT (output from FUSB3317). This pin is
connected to a 1 mF external capacitor.
13
12
GND
Connect to board ground but not connector ground
CATH(FB) Open Drain Output Feedback to control the power supply. Typically connected to the error amplifier output of
a DC−DC regulator (often called the compensation pin). For a fuse option, connected to
the feedback pin at the resistor divider (FB) of the DC/DC.
8
VFB
Input
Output Voltage Sensing Signal. This pin is used for CV regulation, and it is tied to the
internal CV loop amplifier non−inverting input terminal. It is tied to the output voltage
resistor divider
9
6
IFB
IS+
Input
Input
Constant Current Amplifying Signal. The voltage level at this pin is the amplified current
sense signal.
Current sensing amplifier positive terminal. Connect this pin directly to the positive end of
the current sense resistor with a short PCB trace. This is usually the connector ground
terminal.
7
IS−
Input
Current sensing amplifier negative terminal. Connect this pin directly to the negative end
of the current sense resistor with a short PCB trace. This is usually the board ground.
17
14
DC_EN
DISC
Output
Active High output turns on the DC−DC controller when a Type C Sink is detected.
Open Drain Output Discharge pin. This pin is tied to VBUS with a discharge resistor in the path to discharge
VBUS at the connector.
3
5
CC1
CC2
I/O
Configuration Channel 1. This pin is used to detect USB Type−C devices and
communicate over USB PD.
I/O
Configuration Channel 2. This pin is used to detect USB Type−C devices and
communicate over USB PD.
20
1
D+
D−
D+: I/O
D−: I/O
Input
D+: Connected to D+
D−: Connected to D−
15
18
16
10
PDIV1
PDIV0
NTC
DON
Programmable pin to select different USB Power Delivery Power (PDP) value dynamically
Programmable pin to select different USB Power Delivery Power (PDP) value dynamically
Pin connected to external NTC resistor to sense PCB or connector temperature
Input
I/O
Output
For USB 2.0 data, this pin is tied to the Switch Control of the USB 2.0 data switch to turn
the switch on (5 V HIGH = Switch ON)
4
BATUV
Input
Determines a threshold at which FUSB3317 will scale down the advertised power since the
battery voltage is too low
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4
FUSB3317
MAXIMUM RATINGS
Rating
VBAT Battery Pin Voltage (Note 1)
Symbol
Value
Unit
V
V
−0.3 to 54
−0.3 to 27 V
−0.3 to 6 V
VBATMAX
HIGHMAX
Connector Pins Voltage: VBUS, DISC, CATH, CC1, CC2, D+ and D−
V
V
Low Voltage Pins: DC_EN, DON, IS−, VFB, IFG, BATUV, NTC, PDIV1 and
PDIV0
V
V
LOWMAX
Supply Output Range on Pin VDD
Current Sense Input on Pin IS+
V
−0.3 to 6 V
IS− + 0.1
150
V
V
VDDMAX
V
IS+MAX
Maximum Junction Temperature
T
°C
°C
kV
V
J(max)
Storage Temperature Range
T
STG
−65 to 150
2
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
ESD
ESD
HBM
750
CDM
Lead Temperature Soldering
T
SLD
260
°C
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
2
Thermal Characteristics, QFNW20, 4x4 mm (Note 1)
Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Case (Note 4)
°C/W
R
θJA
R
θJC
36.1
2.3
2
2
4. Values based on copper area of 645 mm (or 1 in ) of 1 oz copper thickness and FR4 PCB substrate.
RECOMMENDED OPERATING RANGES
Rating
Symbol
Min
4.5
3.13
4.75
0
Max
45
Unit
V
Input VBAT Voltage
V
VBAT
VBUS
I/O VBUS Voltage
V
22.05
5.5
5.5
3.6
5.5
5.5
5.5
5
V
Output VDD Supply Voltage
I/O CC1 and CC2 Voltage
I/O D+ and D− Voltage
I/O PDIV0 and PDIV1 Voltage
I/O NTC Voltage
V
VDD
V
V
V
CC1CC2
V
D+D−
0
V
V
0
V
PDIV0−1
V
NTC
0
V
Output DON and DC_EN Voltage
V
0
V
DONEN
Output Current as sensed by IS+ to IS− with 5 mΩ resistor
I
0
A
out
Ambient Temperature
T
A
−40
85 (Commercial)
105 (Automotive)
°C
Junction Temperature
T
J
−40
135
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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FUSB3317
ELECTRICAL CHARACTERISTICS
For typical values, V
noted.
= 12 V and TA = 25°C. For min/max values, V
= 5.5 V to 36 V and TJ = −40°C to 125°C; unless otherwise
VVBAT
VVBAT
Parameter
VBAT Input Supply Section
Turn−On Threshold Voltage
Turn−Off Threshold Voltage
Operating Supply Current at 5.5 V
Test Conditions
Symbol
Min
Typ
Max
Unit
V
V
V
rising
V
3.7
3.4
4.2
3.9
2.5
4.7
4.4
V
V
VBAT
VBAT
VBAT
BAT−ON
falling
= 5.5 V, VCS=15 mV,
Rcs = 5 mW
V
BAT−OFF
BAT−OP−5.5V
I
mA
Operating Supply Current at 36 V
V
= 36 V, VCS=15 mV,
I
4
mA
VBAT
BAT−OP−36V
Rcs = 5 mW
Standby Power Operating Supply Current
V
VBAT
= 12 V, VIS+ = VIS− = 0 V
I
Q
100
mA
VBAT Under Voltage Protection (UVP) Section
VBAT Under Voltage Threshold
BATUV pin is floating
V
3.8
5.9
V
V
BAT−UVP
BATUV Pin Voltage Threshold to Trigger
Battery UVP
BATUV pin with resistor divider to
VBAT pin
V
0.56
0.6
5.0
65
0.64
BAT−TH
UVP Detection Debounce Timing (Note 8)
VDD Output Supply Section
VDD Output Voltage
V
VBAT
falling
t
0
2
ms
VBATUV−DEB
V
range 5.5 to 36 V
V
DD
4.5
10
5.5
V
VBAT
VBAT
VDD Source Current
V
V
= 12 V, current when
= 4.5 V
I
mA
DD
DD
VBUS Under Voltage Protection (UVP) Section
Ratio V
Under−Voltage−Protection
CC
V
VBUS
falling
V
61
69
%
VBUS
BUS−UVP−65
(UVP) to V
Turn−Off Threshold Voltage
UVP Debounce Time
UVP Blanking Time
V
V
falling in a PPS contract
falling
V
2.805
45
2.97
60
3.135
75
V
VBUS
BUS−UVP−PPS
t
ms
ms
VBUS
D−VBUS−UVP
Whenever a voltage change occurs
from lower V to a higher V
t
160
200
240
BNK−UVP
VBUS
VBUS
VBUS Over Voltage Protection (OVP) Section
VBUS Over Voltage Protection Threshold
VBUS OVP Debounce Time
VBUS rising
VBUS rising
V
116
35
120
75
7
127
115
8.5
%
ms
BUS−OVP−120
t
D−VBUS−OVP
VBUS OVP Blanking Time (Note 5)
During VBUS voltage transition of
t
5.5
ms
BNK−OVP−11
BNK−OVP−10
BNK−OVP−01
BNK−OVP−00
voltage step v 0.5V,
final V
w 13V
VBUS
VBUS OVP Blanking Time (Note 5)
VBUS OVP Blanking Time (Note 5)
VBUS OVP Blanking Time (Note 5)
During VBUS voltage transition of
t
51
55
19
60
ms
ms
ms
voltage step v 0.5V,
final V
< 13V
VBUS
During VBUS voltage transition of
voltage step > 0.5V,
t
t
16.5
205
21.5
236
final V
w 13V
VBUS
During VBUS voltage transition of
voltage step > 0.5V,
221
final V
< 13V
VBUS
Constant Current Limit (CC or CL) Sensing Section
Current−Sense Amplifier Gain
Current sense resistor, Rcs = 5 mW
Current range when controlling current limit PPS constant current limit mode at
A
40
V/V
A
V−CCR
I
I
I
I
I
0.85
1.85
2.85
3.80
4.75
1.00
1.15
2.15
3.15
4.20
5.25
.00
CS−1
A
A
A
A
A
at I = 1.00 A
1 A
OUT
Current range when controlling current limit PPS constant current limit mode at
at I = 2.00 A
2 A
2.00
3.00
4.00
5.00
A
A
A
A
00
CS−2.
CS−3.
OUT
Current range when controlling current limit PPS constant current limit mode at
at I = 3.00 A
3 A
00
OUT
Current range when controlling current limit PPS constant current limit mode at
at I = 4.00 A
4 A
.00
CS−4
OUT
Current range when controlling current limit PPS constant current limit mode at
at I = 5.00 A
5 A
00
CS−5.
OUT
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FUSB3317
ELECTRICAL CHARACTERISTICS (continued)
For typical values, V
noted.
= 12 V and TA = 25°C. For min/max values, V
= 5.5 V to 36 V and TJ = −40°C to 125°C; unless otherwise
VVBAT
VVBAT
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Over Current Protection (OCP) Sensing Section
Over Current Protection (OCP) threshold
percentage of maximum current
PD request for constant voltage
mode with VBUS at 5.2 V and 3 A
maximum current
IOCP*PER
109
120
124
%
OCP debounce time
Constant current exceeding
tOCP*DEB
ICS*DSCG
50
60
70
ms
IOCP*PER
Current threshold on sensing resistor for
enabling discharge on DISC pin during a
voltage transition
VBUS is decreasing
430
mA
Debounce time for enabling discharge on
DISC pin during a voltage transition
VBUS is decreasing
tCS*DSCG
0.6
1.0
ms
Constant Voltage Sensing Section
VFB Reference Voltage at 3.3 V
VBUS = 3.3 V, current sense resistor
voltage, Vcs = 0 V
V
0.32
0.33
0.34
V
V
V
V
V
CVR−3.3V
VFB Reference Voltage at 5.2 V nominal
output voltage
VBUS = 5.2 V, current sense resistor
voltage, Vcs = 0 V
V
0.504
0.873
1.455
1.940
0.520
0.900
1.500
2.000
0.536
0.927
1.545
2.060
CVR−5V
CVR−9V
CVR−15V
CVR−20V
VFB Reference Voltage at 9 V nominal
output voltage
VBUS = 9 V, current sense resistor
voltage, Vcs = 0 V
V
VFB Reference Voltage at 15 V nominal
output voltage
VBUS = 15 V, current sense resistor
voltage, Vcs = 0 V
V
V
VFB Reference Voltage at 20 V nominal
output voltage
VBUS = 20 V, current sense resistor
voltage, Vcs = 0 V
Feedback Section
CATH(FB) pin sink/source current (Note 5) CATH(FB) as a sink (Note 6)
CATH(FB) pin sink/source current (Note 5) CATH(FB) as a source (Note 6)
Discharge Section
I
2
mA
mA
CATH−SNK
I
−2
FB−SRC
VBUS to GND Leakage Resistance
VBUS Pin Sink Current
Discharge Time
DC_EN = 0 V, VBUS not sourced
VBUS = 20 V and being discharged
R
72.4
250
5.5
155
7
kW
mA
ms
DISC−VBUS
I
DISC−SNK
During VBUS voltage transition of
t
8.5
60
DISC−11
DISC−10
DISC−01
DISC−00
voltage step v 0.5 V,
final V
> 13 V
VBUS
Discharge Time
Discharge Time
Discharge Time
During VBUS voltage transition of
t
t
t
51
55
19
ms
ms
ms
voltage step v 0.5 V,
final V
< 13 V
VBUS
During VBUS voltage transition of
voltage step > 0.5 V,
16.5
205.5
21.5
236.5
final V
> 13 V
VBUS
During VBUS voltage transition of
voltage step > 0.5 V,
221
final V
< 13 V
VBUS
Over Temperature Protection (OTP) Section
Current Source on NTC Pin
Resistance to ground on NTC =
I
55
60
90
65
mA
ms
V
NTC
3.293 kW
Debounce Time for External Over Temper- Over temperature event
ature Protection (E_OTP)
t
NTC−DEB
Over Temperature Warning Threshold on
NTC pin at 100°C (Note 8)
Resistance to ground on NTC =
4.247 kW
V
0.234
0.181
0.256
0.198
135
0.276
0.214
NTC−WARN
Over Temperature Protection Threshold on Resistance to ground on NTC =
NTC pin at 100°C (Note 8)
3.293 kW
V
V
NTC−OTP
Internal Over Temperature Protection
(I_OTP) Threshold (Note 8)
T
I_OTP
°C
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FUSB3317
ELECTRICAL CHARACTERISTICS (continued)
For typical values, V
noted.
= 12 V and TA = 25°C. For min/max values, V
= 5.5 V to 36 V and TJ = −40°C to 125°C; unless otherwise
VVBAT
VVBAT
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Protection Recovery Section
Duration after Fault Removed before
Normal Operation Resumes (Note 5)
Any fault applied and then removed
and not in debug accessory
operation
t
t
1.8
2.0
2.2
s
2S−AR−NM
Duration after Fault Removed before
Normal Operation Resumes (Note 5)
Any fault applied and then removed
and debug accessory has been
detected
100
60
ms
ms
2S−AR−DM
OCP debounce time used for both
detecting an OCP or Current limit condition
t
50
70
OCP_Debounce
Inputs and Outputs Section
Input LOW Voltage for PDIV1 and PDIV0
PDIVx voltage swept from 0 V to
5.5 V
V
0.4
V
V
IL−PDIVx
Input HIGH Voltage for PDIV1 and PDIV0
PDIVx voltage swept from 0 V to
5.5 V
V
V
VDD
0.4
−
IH−PDIVx
Output LOW Voltage for DON and DC_EN Sink current = 1 mA
Output HIGH Voltage for DON and DC_EN Source current = −1 mA
Type C USB Section
V
V
0.4
V
V
OH
2.0
OH
CC1 or CC2 Pull−Up Current for 3A
Open Circuit Impedance on CC1 or CC2
Ra Detection Voltage Threshold
V
V
= 12 V, CC1 and CC2 floating
= 12 V, disabled state
I
304
126
0.75
330
356
mA
kW
V
VBAT
VBAT
CCx−3A
Z
OPEN−CCx
Ra−CCx−3A
CCx swept from 5.5 V to 0 V, I
applied
V
V
0.8
2.60
150
0.85
2.75
CCx-3A
Rd Disconnect Detection Voltage
Threshold
CCx swept from 5.5 V to 0 V, I
applied
2.45
V
CCx-3A
Rd−CCx−3A
Debounce Time before SRC Detection
Rd connected to CC1 or CC2
t
100
3.0
34
200
5.5
ms
V
CCx−DEB
V
CONN
V
CONN
V
CONN
Voltage Range
When eMarker being discovered
When eMarker being discovered
When eMarker being discovered
V
VCONN
VCONN
Current Supplied
I
mA
mA
V
Over Current Protection Threshold
I
t
50
VCONN−OCP
CC1 or CC2 Over Voltage Protection
CC1 or CC2 OVP Debounce Time
D+ or D− Over Voltage Protection
D+ or D− OVP Debounce Time
USB Power Delivery BMC Section
BMC Period
V
5.5
5.75
4.35
6.0
100
4.6
4.5
CC−OVP
CCOVP−DEB
ms
V
V
4.1
DPDM−OVP
DPDM−OVP−DEB
T
ms
t
UI
3.03
300
300
33
3.7
75
ms
ns
ns
W
BMC Transmitter Rise Time
t
t
RISE−BMC
FALL−BMC
BMC Transmitter Fall Time
BMC Transmitter Driver Impedance
BMC Receiver Bandwidth Limiting Filter
BMC Receiver Capacitance (Note 5)
z
DRIVER
t
100
ns
pF
RX−FILTER
BMC driver is not turned on
c
15
RECEIVER
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25_C
J
A
6. Refer to the APPLICATION INFORMATION section.
7. Values based on design and/or characterization.
8. Guaranteed by design/characterization.
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8
FUSB3317
APPLICATIONS INFORMATION
Type C Attach
FUSB3317 has the entire Power Delivery (PD)
communication stack within hardware including the
optional Programmable Power Supply (PPS). No external
processor is needed. This enables turnkey solutions for PD
with PPS and makes this solution tamper proof unlike other
firmware−based solutions.
VBAT Supply Input
Connect the automotive battery supply directly to the
VBAT pin of the FUSB3317. The battery voltage can vary
from 5.5 V to 36 V in normal operation but can be up to 45 V
for short periods of time when an automotive load dump
event occurs. Similarly, the battery voltage could dip to
4.5 V momentarily. If there is significant dropout of VBAT
for tens of microseconds or milliseconds, an input holdup
capacitor is needed to stabilize VBAT to be within the above
voltage range.
Figure 5. Type C Source
Low Standby Current
With the FUSB3317 connected directly to the battery,
there is no need to turn on the DC/DC unless there is
something attached to the USB−C port. The FUSB3317 will
consume very low current (I ) while looking for a Sink
Q
attach allowing for a very low system standby current.
Local Power Generated
FUSB3317 generates its own power from VBAT via an
integrated LDO. The total current generated can be
consumed by the FUSB3317 and by external low−power
electronics as long as the combined current is less than I
.
DD
The recommended external decoupling capacitor on V is
DD
2.2 mF or greater. The value of V is typically 5.2 V.
DD
VDD
VBAT
Figure 6. Type C Sink
The FUSB3317 implements the Rp pull up resistors in
Figure 5 as current sources (I ) that advertise 3A
CCx−3A
default current capability. When the Sink’s CC1 or CC2 pins
as shown in Figure 6 with Rd as 5.1 kW resistor connect with
either with CC1 or CC2 of the FUSB3317 in a flipped or
straight connection, an attach occurs when the voltage on the
CC1 or CC2 pin (only one CCx connects through the cable)
V BAT−ON / V BAT−OFF
is in the V
range. Once this attach is detected,
Rd−CCx−3A
Figure 4. VDD LDO Supply Generation
FUSB3317 enables a DC/DC controller via DC_EN pin to
source VBUS provided the connector VBUS pin is initially
discharged to ground (VBUS not source if VBUS already
present).
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9
FUSB3317
USB Power Delivery Support
Provider
FUSB3317 consists of all four PHY, Protocol, PE and
DPM layers to fully implement a compliant PD Source fully
in hardware.
Consumer
Device Policy
Device Policy
Manager
USB PD Power Advertisement
Manager
Policy Engine
Protocol
The USB PD specification defines Power Data Objects
(PDO) and Augmented Power Data Objects (APDO) as a
way for the Source device to advertise it’s power
capabilities. PDO’s describe well*regulated fixed voltage
supplies while APDO Programmable Power Supply (PPS)
describe a power supply whose output voltage can be
adjusted over the advertised voltage range. A Source can
advertise a combination of PDOs and APDOs, up to a
maximum of 7 total Data Objects for SPR. In order to
provide a consistent experience across the Source devices
with the same PD Power (PDP) rating, a set of power rules
are contained within the PD specification. The power rules
provide a set of minimum requirements (PDOs and APDOs)
that must be met for a Source device based on the advertised
PDP.
Policy Engine
Protocol
Physical Layer
Physical Layer
CC
The FUSB3317 can be configured to meet a variety of
different PDP power advertisements, depending on the
application requirements. The default power for the
FUSB3317 is the standard 60 W option as shown in Table 1.
Figure 7. USB−PD Communication Stack
USB Power Delivery (PD) provides a way for a Source
and Sink to negotiate output power settings, allowing for
increased power delivery up to 100 W for Standard Power
Range (SPR). USB PD uses the CC signal that is passed
through the cable to provide the link between the Source and
the Sink to send messages and commands. The
communications stack consists of Physical, Protocol, Policy
Engine and Device Policy Manager layers as shown in
Figure 7 where each layer in the FUSB3317 talks to its
corresponding layer in the Sink device.
The Physical (PHY) Layer handles both the transmission
and reception of the bits on the CC signal. All data is first
encoded using a 4b5b line code and then transmitted across
the CC signal using Biphase Mark Coding (BMC). A
32*bit CRC is also used to protect the data integrity of the
data payload.
The Protocol Layer defines how USB PD messages are
constructed and used between a Source device and a Sink
device. All USB PD messages must follow a strict packet
definition and may also include timing requirements based
on the type of message. The Protocol Layer is responsible
for verifying the timing parameters and handling any
communication errors as they arise.
The Policy Engine (PE) is responsible for executing the
device Local Policy to control its power delivery behavior.
The Policy Engine defines a set of message sequences that
must be followed for proper operation. All power
negotiations are handled by the Policy Engine.
Table 1. FUSB3317 DEFAULT PDOs AND APDOs
[A]PDO Power
Data Object
Output
Voltage
Max Current
w/3 A Cable
Current
Mode
PDO1
PDO2
PDO3
PDO4
APDO1
5 V
9 V
3.6 A
3.6 A
3.6 A
3.6 A
3 A
OCP
OCP
15 V
OCP
20 V
OCP
3.3 V ~ 21 V
CL or CC
Constant Voltage Control
In order to regulate adaptive output voltages, the constant
voltage control (CV) is implemented. The output voltage is
sensed through an external resistor divider. The sensed
output voltage is connected to the VFB pin, and it is input the
non*inverting input terminal of the internal operational
amplifier. The inverting input terminal is connected to the
internal voltage reference (VCVR) which can be adjusted
according to the requested output voltage. The amplifier and
an internal switch operate as a shunt regulator, and the output
of the shunt regulator is connected to the CATH pin. To
compensate output voltage regulation, typically, two
capacitors and one resistor are connected between CATH
and VFB pins as Figure 8. The output voltage can be derived
as calculated by the Equation 1, and the ratio of the resistor
divider is 10. The reference (VCVR) for the output voltage
is generated by a 10*bit DAC. The minimum resolution is
20 mV to meet PD compliance for PPS.
The Device Policy Manager (DPM) is responsible for
overseeing the power supply and managing changes to the
Local Policy, including handling of alert and fault
conditions. It is also responsible for managing VCONN and
the Discover Identity messaging to determine the full
capabilities of the cabling.
R
F1 ) RF2
RF2
ǒ Ǔ
V
VBUS + VCVR
(eq. 1)
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10
FUSB3317
VBAT
from the CATH signal. When the load current exceeds the
+
VBUS
−
V1
PWM
OCP threshold for longer than tOCP−DEB, OCP is triggered
and the FUSB3317 enters Auto Restart Mode after OCP is
not detected.
Buck or Buck−Boost
PWM Control
RCS
COMP
IS−
IS+
Discharge Functionality
Discharge circuits are implemented on the DISC pin to
discharge the output capacitors quickly during voltage
and/or current transitions and to fully discharge VBUS when
required. The discharge circuits in the FUSB3317 are sized
to meet the timing requirements in the USB PD
specification. Since the output load can discharge the load
sufficiently during heavy loads, the discharge circuits are
only enabled during light load conditions (ICS< ICS-DSCG).
The operation of the discharge circuits is shown in Table 2
and Table 3.
VDD
VDD
IFB
VCCR
CATH
RF1
VFB
RF2
VCVR
Figure 8. Voltage and Current Sensing Circuits
Constant Current Control
Table 2. DISCHARGE DURING VOLTAGE
TRANSITIONS
Constant Current Limit (CL or CC) or control is enabled
during USB PD explicit contracts with a PPS APDO. When
CL (or CC) mode is enabled, the supply will decrease the
output voltage as the load increases in order to maintain a
fixed output current. Output current is sensed via a
Step Size
New VBUS
>13 V
tBDISC−xx (typ)
7 ms
DC_EN
Enabled
Enabled
Enabled
Enabled
v0.5 V
<13 V
19 ms
current*sense resistor R , which is connected between
>0.5 V
>13 V
55 ms
CS
the IS+ and IS− pins. The sensed signal is internally
amplified, and this amplified voltage is connected to the
non*inverting input of the internal operational amplifier.
Similar to the constant voltage amplifier circuit, it also plays
a role as a shunt regulator to regulate the constant output
current. In order to compensate output current regulation,
one capacitor and one resistor are connected between the
IFB and CATH pins as shown in Figure 8. The constant
output current can be calculated using Equation 2. 5 mΩ is
typically used for the sense resistor.
<13 V
221 ms
Table 3. DISCHARGE UPON DETACH, PROTECTION
MODE OPERATION OR HARD RESET
Initial VBUS
Final VBUS
tBDISC−xx (typ)
DC_EN
3.3 V ~ 21 V
vSafe0V
(<0.8 V)
221 ms
Enabled
Protection Mode and Auto Restart Operation
The FUSB3317 provides Output Over Voltage Protection
(OVP), Under Voltage Protection (UVP), Output Over
Current Protection (OCP), External Over Temperature
Protection via NTC (E_OTP), Internal Over Temperature
Protection (I_OTP), D+/D− line Over Voltage Protection
(D_OVP) and CC line Over Voltage Protection (CC_OVP).
When a protection mode is triggered, the DC/DC is disabled
and the discharge circuits are enabled to protect the Sink
device. During this time, the CC pull−up currents (ICCx−3A)
are disabled to indicate to the Sink device that the Source is
not ready to provide power. The functionality described is
shown in Figure 9. Once the fault conditions are removed,
the FUSB3317 will re−enable the DISC discharge circuit
and begin the auto*restart timer (t2S−AR−NM). After the
auto*restart timer expires, the CC pull*up currents will be
enabled to allow a Sink device to attach.
VCCR
ǒ Ǔ
RCS
1
40
ICS
+
(eq. 2)
Since the voltage across the IS+ and IS− pins is small, the
sensing resistor should be positioned as close as possible to
the pins. An RC filter can be added to the pins to reduce the
noise seen on the circuit.
Output Over Current Protection
Over Current Protection (OCP) is enabled during USB PD
explicit contracts with PDOs (i.e. not PPS APDOs). When
OCP mode is enabled, the supply will regulate the output
voltage until the load current exceeds the OCP threshold, at
which point it will cause a fault condition and disable the
output voltage and disconnects from the attached Sink.
Similar to Constant Current Control, the FUSB3317 detects
the output current via the current sense resistor RCS, with the
difference being the output of the CC amplifier disconnected
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11
FUSB3317
VBAT
+
VBUS
−
V1
PWM
Buck or Buck−Boost
PWM Control
EN
DC_EN
DISC
VBUS
VDD
VDD
Enable Block
Figure 10. DON Pin Connection to NIV1241
CC1
Discharge
9RVIN
OVP/UVP
E_OTP/I_OTP/OCP
CC_OVP/D_OVP
With sink attach, the FUSB3317 controls the DON pin
High to close the USB D+/D− signals between head unit and
the attached sink. DON pin is controlled to High about
900 ms after CC debounce and stayed high until sink device
is plugged out. DON pin controls to Low with sink detach
or device reset by POR or protection mode from
OVP/OCP/OTP.
Protection Block
RVIN
CC2
Figure 9. Protection Block Diagram
DC_EN
DC_EN pin is to disable/enable the external VBUS supply
IC like DC−DC converter. So, DC_EN connects to Enable
pin of DC−DC converter. To minimize the current
consumption of DC−DC converter while Sink is not plugged
in, FUSB3317 turns off the DC−DC until sink device
attaches. Once Sink attaches, FUSB3317 detects the CC
attach and enables DC_EN to High after 100msec of CC
debounce to supply VBUS. Also the CATH pin controls the
VBUS to 5 V default along with the DC_EN The initial
VBUS will be 5 Volt by default feedback and the voltage can
be changed following PD contract over CATH. DC_EN is
controlled to Low with sink detach or device reset by POR
or protection mode from OVP/OCP/OTP.
BATUV
BATUV pin monitors VBAT, battery voltage, to know if
the voltage is low enough to send a new PD message to scale
down the negotiated source power data object. The pin can
be left float or either resistor divide input of VBAT. When
the BATUV is float, if VBAT is below V
or when the BATUV is resistor divide of VBAT and then if
the BATUV drops below, V , 0.6 Volt, the new PD
, max 5.9 V,
BAT_UVP
BAT_TH
message will be sent to sink to renegotiate. In both cases, the
2 ms debounce time, t , is applied before
VBATUV_DEB
sending scale down message. The scaled down PDP(Power
Delivery Power) by VBAT UVP will be 75% of the max
PDP. For example, at 60 W PDP default, it will change to
45 W by VBAT UVP. Once VBAT UVP is recovered, it will
come back to 60 W.
DON and USB2.0 Data Lines
The USB 2.0 Data Lines, D+ and D−, can be externally
connected together via a 100 ohms resistor to provide the
maximum power, a legacy USB device can take, which is
1.5 A per USB Battery Charging v1.2 (BC1.2) specification.
This will usually be the case when a USB−C to micro−B
cable is plugged into this design where this adapter cable has
the required Sink Rd resistors within it to allow the
FUSB3317 to recognize a Type C attach and to source 5 V
on VBUS. The Sink will go through BC1.2 steps of primary
and secondary detection to detect a Dedicated Charging Port
(DCP) via this resistor connection of D+ and D− and takes
1.5 A maximum from VBUS.
Internally, FUSB3317 presents BC1.2 Charging
Downstream Port(CDP) mode in default to provide the
1.5 A of power as well as to make USB signal path
connection between USB PHY, Head unit in automotive
application and sink device. Since USB data, D+, D−, path
have to connect from Sink to FUSB3317 as well as head unit,
there should be 2:1 switch mux externally. DON pin of
FUSB3317 can control the external switch enable or switch
direction control. Below diagram is the example of using
external switch, NIV1241, which has signal switch and TVS
diodes on D+ and D− for ESD protection.
NTC
NTC pin is to detect external temperature on the board.
NTC will connect to a thermistor which can be placed in the
hottest place on the PCB, it could be next to NFET or close
to the USB−C connector. Once NTC temperature rises to
warning range which is 90°C, the scale down PDP will be
sent to sink so that the sink will pull less current/power. The
scale is the same as VBAT UVP, 75%. If the NTC detects
above shut down temperature, 100°C, FUSB3317 enters
fault protection mode and VBUS FET will be shut off and
Sink will be disconnected.
The new PDP table is below in case of either VBAT UVP
or NTC. The PDP scaling minimum is 25% of PDP and PDP
scaling default is 75%.
VBAT−UVP NTC Warning
Resultant_PDP
Yes
No
No
PDP_scaling*Current_PDP
PDP_scaling*Current_PDP
Yes
PDP_scaling minimum
*Current_PDP
Yes
No
Yes
No
Current_PDP
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12
FUSB3317
PDIV0, PDIV1
CC1 and CC2 Over Voltage Protection (CC_OVP)
FUSB3317 protects against the CC1 and CC2 connector
pins being shorted to VBUS up to 27 V and it has the ability
to start protecting the system when the CC voltage is beyond
it normal operating range. If either CC1 or CC2 voltage is
These pins are prepared in addition to the fuse bits to
provide a PDP range of 7.5W to 100W. FUSB3317 changes
PDP dynamically once either PDV1 or PDIV0 is changed so
the new PD message will be sent by the voltage change of
PDIVx. The table below is PDP setting logic by PDIVx.
above, V
OVP threshold for t
, then the
CC−OVP,
CC−OVP−DEB
FUSB3317 protects the system by triggering this fault and
executing protection as described in Protection Operation
section above.
PDIV1:PDIV0
Current_PDP of FUSB3317
100%*max_power_PDP
75%*max_power_PDP
50%*max_power_PDP
25%*max_power_PDP
11
10
01
00
D+/D− Lines Over Voltage Protection
In order to protect the FUSB3317 when D+ or D− are
short−circuited with small impedance to VBUS, OVP is
incorporated on D+ and D− pin. If voltage on D+ and/or D−
VDD
is greater than V
and the OVP is longer than,
DPDM−OVP
VDD is 5 V regulator output, please add 2.2 mF capacitor
on the pin. Detail description and block diagram are
mentioned above.
t ,OVP debounce, D+/D− line Over−Voltage
DPDM−OVP−DEV
Protection is triggered. D+/D− OVP is always enabled in
default. D+ and D− lines have absolute voltage up to 27 V
so that any short to VBUS when VBUS is at its OVP limit
will not destroy the D+ and D− pins since it takes a finite
amount of time after recognizing an OVP on VBUS or
D+/D− before the DC/DC controller is shut off and VBUS
capacitance is discharged.
Vconn Over current protection (Vconn OCP)
FUSB3317 will turn on VCONN whenever it needs to
read the eMarker in the cable only if 5 A capability is
supported by trim option. When VCONN is sourced, per
USB PD specification only 100 mW maximum (5 V with
20 mA for the FUSB3317) needs to be supplied for a USB
2.0 source application. If the VCONN current exceeds
ICONN_OCP (typical 50 mA) for tVCONN_OCP then the
FUSB3317 will disable the VCONN supply and abort the
eMarker discovery process. The default maximum current
of 3 A will be used for all source capabilities for USB PD
messages in the latter case and the normal PD messaging
will occurs without interruption. No Alert messages will be
sent but the PD Status message will have a bit to indicate that
the cable limited the FUSB3317 from advertising 5 A source
capabilities.
DISC
DISC pin connects to VBUS path between NFET source
pin and VBUS pin of USB−C connector through about 40 W
series resistor to discharge VBUS capacitor when VBUS
changes from high to low, like 15 V to 5 V. The force
discharge can make the VBUS transition fast enough to meet
the USB PD spec even with large bulk capacitor. DISC
discharge only occurs when VBUS load current is less than
about 250 mA, if the load current is larger than that, the
DISC discharge doesn’t occur. DISC discharge also occurs
at fault conditions such as, OVP, UVP, OCP and OTP on
VBUS or CCx OVP or DP/DM OVP conditions.
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13
FUSB3317
REFERENCES AND DEFINITIONS
Specifications Used in this Datasheet
• Universal Serial Bus Power Delivery specification revision 3.1 version 1.0
• Universal Serial Bus Type C Cable and Connection Specification release 2.0, dated August, 2019
• USB Battery Charging Specification, revision 1.2, dated December 7, 2010
• Universal Serial Bus Power Delivery specification revision 2.0 version 1.3, dated 12 January, 2017
Current Limit and Short Circuit Current Limit
PSRR
Current Limit is value of output current by which output
voltage drops by 10 % with respect to its nominal value.
Short Circuit Current Limit is output current value
measured with output of the regulator shorted to ground.
Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).
ORDERING INFORMATION
†
Device Order Number
Specific Device Marking
Package Type
Shipping
FUSB3317V6AMNWTWG
3317V6A
QFNW20 4x4, 0.5P
4000 / Tape & Reel
(Pb−Free)
FUSB3317F6AMNWTWG
3317F6A
QFNW20 4x4, 0.5P
4000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
USB−C, USB Type−C and the USB logos are trademarks or registered trademarks of USB Implementers Forum, Inc.
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFNW20 4x4, 0.5P
CASE 484AT
ISSUE O
DATE 06 AUG 2019
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
ALYWG
G
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10684H
QFNW20 4x4, 0.5P
PAGE 1 OF 1
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