FXLP4555MPX_技术文档

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May 2011

FXLP4555

1.8V / 3.0V SIM Card Power Supply and Level Shifter

Features

Description

.

Supports 1.8V or 3.0V SIM Cards

The FXLP4555 is a level-shifter analog circuit designed

to translate the voltages between a SIM card and an

LDO Supplies >50mA Under 1.8V and 3.0V

external baseband.

A

built-in LDO-type DC-DC

Built-in Pull-up Resistor for I/O Pin in Both

Directions

converter allows the FXLP4555 to drive 1.8V and 3.0V

SIM cards. The device fulfills the ISO7816-3 smart-card

interface standard as well as GSM 11.11 (11.12 and

11.18) and 3G mobile requirements (IMT-2000/3G UICC

standard). The EN pin enables a low-current Shutdown

Mode that extends battery life. The card power supply

voltage (VCC_C) is selected using a single pin (VSEL).

.

ESD Protection: 8kV (Human Body Model,

According to ISO-7816 Specifications)

.

Supports Clock  5MHz

Supports “Clock Stop” Power Management per

ISO7816-3 Specifications

.

Low-Profile 3x3mm MLP-16 Package

Applications

.

SIM Card Interface Circuit for 2G, 2.5G, and 3G

Mobile Phones

.

Identification Module

Smart Card Readers

Wireless PC Cards

Ordering Information

Operating

Temperature Range

Top

Mark

Part Number

Package

Packing Method

FXLP

4555

16-Lead,MLP,Quad,JEDEC

MO-220,3MM Square

3000 Units

on Tape & Reel

FXLP4555MPX

-40 to +85°C

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

Application Diagram

Figure 1. Typical Application

Functional Block Diagram

VBAT

5

LDO:

1.8V/3V

EN

1

VCC_C

7

at 50mA

GND

VSEL

VCCA

2

VCCA

VCC_C

3

Unidirectional

Driver

RST_C

CLK_C

I/O_C

RST_H

CLK_H

I/O_H

14

9

11

8

GND

Unidirectional

Driver

13

15

GND

18K

14K

Bidirectional NpassGate

With Edge Rate

Accelerators

10

GND

Figure 2. Block Diagram

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

2

Pin Configuration

16

15

14

13

1

2

3

4

12

11

10

9

EN

VSEL

VCCA

NC

CLK_C

GND

FXLP4555

Exposed DAP

(GND)

RST_C

5

6

7

8

Figure 3. Pin Assignments (Top View)

Pin Definitions

Name

Type

Description

Power-Down Mode. EN=LOW → low-current Shutdown Mode activated. EN=HIGH →

1

EN

INPUT

normal operation. A LOW level on this pin resets the SIM interface, switching off the

V_{CC_C}

.

The signal present on this pin programs the SIM_V_CCvalue:

VSEL=LOW → SIM_V_CC=1.8V; VSEL=HIGH → SIM_V_CC=3V.

2

3

VSEL

VCCA

INPUT

Connected to the baseband power supply; this pin configures the level shifter input

stage to accept signals from the baseband. A 0.1µF capacitor is used to bypass the

power supply voltage. When V_CCAis below 1.1V (typical), the V_{CC_C}(SIM Card V_CC) is

disabled and FXLP4555 enters Shutdown Mode.

POWER

4

5

6

NC

VBAT

NC

No connect. It is recommended to solder to PCB GND.

LDO converter supply input. The input voltage ranges from 2.7V to 5.5V. This pin

needs to be bypassed by a 0.1µF capacitor.

POWER

No connect. It is recommended to solder to PCB GND.

Connected to the SIM card power supply pin. An internal LDO converter is

programmable by the external baseband to supply either 1.8V or 3.0V output voltage.

7

8

VCC_C

I/O_C

POWER An external 1.0µF minimum ceramic capacitor must be connected across V_{CC_C}and

GND. During a normal operation, the V_{CC_C}voltage can be set to 1.8V, followed by a

3.0V value, or can start directly at either of these values.

Handles the connection to the serial I/O of the card connector. A bi-directional level

translator adapts the serial I/O signal between the card and the baseband. A 14kΩ

INPUT/

OUTPUT

(typical) pull-up resistor provides a high-impedance state for the SIM card I/O link.

Connected to the RESET pin of the card connector. A level translator adapts the

external reset (RST) signal to the SIM card.

9

RST_C

GND

OUTPUT

Ground reference for the integrated circuit and associated signals. Care must be

GROUND

10

taken to avoid voltage spikes when the device operates in normal operation.

Connected to the CLOCK pin of the card connector. The CLOCK (CLK) signal comes

11

12

13

CLK_C

NC

OUTPUT from the external clock generator; the internal level shifter adapts the voltage defined

for the V_{CC_C}

.

No connect. It is recommended to solder to PCB GND.

The clock signal, coming from the external controller, must have a duty cycle within

the range defined by the specification (typically 50%). The built-in level shifter

translates the input signal to the external SIM card CLK input.

CLK_H

INPUT

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

3

Pin Definitions (Continued)

Name

Type

Description

The RESET signal present at this pin is connected to the SIM card through the

internal level shifter, which translates the level according to the V_{CC_C}programmed

value.

14

RST_H

INPUT

This pin is connected to the baseband. A bidirectional level translator adapts the serial

I/O signal between the smart card and the baseband. A built-in constant 18kΩ (typical)

resistor provides a high-impedance state when not activated.

INPUT/

OUTPUT

15

I/O_H

NC

16

17

No connect. It is recommended to solder to pcb GND.

Exposed

DAP

Ground Must be soldered to PCB ground plane.

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only. T_A=+25°C.

Symbol

V_BAT

Parameter

Min.

-0.5

Typ.

V_BAT

Max.

6.0

Unit

V

LDO Power Supply Voltage

V_CCA

Power Supply from Baseband Side

External Card Power Supply

V_CCA

V_{CC_C}

6.0

V

V_{CC_C}

6.0

V

V_CCA+0.5,

but <6.0

V_IN

I_IN

Digital Input Pin Voltage

Digital Input Pin Current

Digital Output Pin Voltage

Digital Output Pin Current

SIM Card Output Pin Voltage

-0.5

-5

V_IN

V

mA

V

+5

V_CCA+0.5,

V_OUT

I_OUT

-0.5

-10

-0.5

V_OUT

but <6.0

+10

mA

V

SIM_V_CC

+

V_{OUT_SIM}

V_OUT

0.5<6.0

I_{OUT_SIM}

P_D

SIM Card Output Pin Current⁽¹⁾

15

440

mA

mW

°C/W

°C

Power Dissipation at T_A=+85°C

Thermal Resistance, Junction-to-Air

Operating Ambient Temperature Range

Operating Junction Temperature Range

Maximum Junction Temperature

Storage Temperature Range

Θ_JA

72

T_A

-40

+85

+125

+150

T_J

°C

T_JMAX

T_STG

°C

-65

°C

SIM Card Pins

(7,8,9,10,11)

8000

2000

Human Body

Model,

JESD22-A114

R=1500Ω,

C=100pF

Electrostatic

Discharge

Capability

All Other Pins

ESD

V

SIM Card Pins

(7,8,9,10,11)

Charged

Device Model,

JESD22-C101

All Other Pins

600

1

Moisture Sensitivity Level

Level

Notes:

1. Internally limited.

2. Meets or exceeds JEDEC specification EIA/JESD78 IC latchup test.

www.fairchildsemi.com

FXLP4555 • Rev. 1.0.0

5

Electrical Characteristics

T_A=-40°C to +85°C. Device meets the specifications after thermal equilibrium has been established when mounted in

a test socket or printed circuit board with maintained transverse airflow greater than 500lfpm. Electrical parameters

are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding

these conditions is not implied. Device specification limit values are applied individually under normal operating

conditions and not valid simultaneously.

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

Power Supply Section

V_BAT

Power Supply

2.7

5.5

25

V

I_CC=0mA, V_BAT> 3.0V if V_SEL=1 or

I V_BAT

Operating Current

16

µA

V_BAT> 2.7V if V_SEL=0

EN=Low

I V_{BAT_SD}

V_CCA

Shutdown Current

Operating Voltage

Operating Current⁽³⁾

Shutdown Current

3

5.50

12

1

µA

V

1.65

0.6

fCLK=1MHz

EN=Low

I_VCCA

7

µA

IV_{CCA_SD}

Under-Voltage

Lockout

V_CCA

1.5

V

V_SEL=High, V_BAT=3.0V,

IV_{CC_C}=50mA

2.8

3.0

1.8

SIM Card Supply

Voltage

V_SEL=High, V_BAT=3.3V – 5.5V,

IV_{CC_C}=0mA - 50mA

V_{CC_C}

2.8

1.7

3.2

V

VSEL=Low, V_BAT=2.7V – 5.5V,

IV_{CC_C}=0mA - 50mA

1.9

I_{VCC_C_SC}

Short-Circuit Current

V_{CC_C}Shorted to Ground, T_A=25°C

175

mA

Digital Input / Output Section (CLK, RST, I/O, EN, VSEL)

V_IN

Input Voltage Range

Input Current

EN, VSEL, RST_H, CLK_H, I/O_H

EN, VSEL, RST_H, CLK_H

0

V_CCA

100

V

I_IH, I_IL

-100

nA

High Level Input

Voltage

0.7 •

V_CCA

V_IH

RST_H, CLK_H, EN, VSEL

V_CCA

V

0.2 *

V_CCA

RST_H, CLK_H

Low Level Input

Voltage

V_IL

V

EN, VSEL

0

0.4

High Level Output

Voltage

0.7 •

V_CCA

V_{OH_I/O}

V_{OL_I/O}

I_IH

I/O_C=V_{CC_C}, I_{OH_I/O}=-20µA

V_CCA

V

Low Level Output

Voltage

I/O_C=0 V, I_{OL_I/O}=200µA

0

0.4

High Level Input

Current

I/O

-20

20

µA

Low Level Input

Current

1.0

mA

I_IL

R_{pu_I/O_H}

I/O Pull-Up Resistor

12

18

24

kΩ

Continued on the following page…

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

6

Electrical Characteristics (Continued)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

SIM Interface Section⁽⁴⁾

0.9 •

V_{CC_C}

Output RST_C V_OHat I_{RST_C}=-20µA

V_{CC_C}

0.4

1

V

Output RST_C V_OLat I_{RST_C}=+200µA

Output RST_C Rise Time at

0

V_{CC_C}=+3.0V

(V_SEL=HIGH)

µs

C

_OUT=30pF (10% - 90%)⁽³⁾

Output RST_C Fall Time at

_OUT=30pF (90% - 10%)⁽³⁾

1

µs

C

RST_C

0.9 •

V_{CC_C}

Output RST_C V_OHat I_{RST_C}=-20µA

V_{CC_C}

0.4

1

V

Output RST_C V_OLat I_{RST_C}=+200µA

0

V_{CC_C}=+1.8V

(V_SEL=LOW)

Output RST_C Rise Time at

C_OUT=30pF (10% - 90%)⁽³⁾

µs

Output RST_C Fall Time at

C_OUT=30pF (90% - 10%)⁽³⁾

1

µs

Output Duty Cycle

40

5

60

%

Maximum Output Frequency

MHz

0.9 •

V_{CC_C}

Output V_OHat I_{CLK_C}=-20µA

V_{CC_C}

0.4

V

V_{CC_C}=+3.0V

(V_SEL=HIGH)

Output V_OLat I_{CLK_C}=+200µA

Output CLK_C Rise Time at

0

18

ns

C

_OUT=30pF (10% - 90%)⁽³⁾

Output CLK_C Fall Time at

_OUT=30pF (90% - 10%)⁽³⁾

18

60

ns

C

CLK_C

Output Duty Cycle

40

5

%

Maximum Output Frequency

MHz

0.9 •

V_{CC_C}

Output V_OHat I_{CLK_C}=-20µA

V_{CC_C}

0.4

V

V_{CC_C}=+1.8V

(V_SEL=LOW)

Output V_OLat I_{CLK_C}=+200µA

Output CLK _C Rise Time at

0

18

Ns

C

_OUT=30pF (10% - 90%)⁽³⁾

Output CLK_C Fall Time at

C

18

ns

_OUT=30pF (90% - 10%)⁽³⁾

Continued on the following page…

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

7

Electrical Characteristics (Continued)

Symbol

Parameter

Condition

Min.

Typ.

Max.

V_{CC_C}

0.4

Unit

V

0.8 •

V_{CC_C}

Output V_OHat I_{I/O_C}=-20µA, V_I/O=V_DD

Output V_OLat I_{I/O_C}=+1mA, V_I/O=0V

0

V

_{CC_C}=+3.0V

(V_SEL=HIGH)

I/O_C Rise Time at C_OUT=30pF

(10% - 90%)⁽³⁾

1

µs

I/O_C Fall Time at C_OUT=30pF

(90% - 10%)⁽³⁾

1

µs

I/O_C

0.8 •

V_{CC_C}

Output V_OHat I_{I/O_C}=-20µA, V_I/O=V_DD

Output V_OLat I_{I/O_C}=+1mA, V_I/O=0V

V_{CC_C}

0.3

1

V

0

V_{CC_C}=+1.8V

(V_SEL=LOW)

I/O_C Rise Time at C_OUT=30Pf

(10% - 90%)⁽³⁾

µs

I/O_C Fall Time at C_OUT=30pF

(90% - 10%)⁽³⁾

1

µs

Card I/O Pull-Up

Resistor

R_{pu_I/O_C}

10

14

18

kΩ

Notes:

3. Guaranteed by design over the specified operating temperature range.

4. All the dynamic specifications (AC specifications) are guaranteed by characterization over the specified operating

temperature range, unless otherwise indicated.

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

8

Typical Performance Characteristics

150

V_BAT= 5.5V

130

V_BAT= 2.7V

110

90

70

50

‐50

‐30

‐10

10

30

50

70

90

Temperature (°C)

Figure 4. Short-Circuit Current ,(I_{VCC_C_SC}) vs.

Temperature V_{CC_C}=1.8V (V_SEL=LOW)

Figure 5. Short-Circuit Current, (I_{VCC_C_SC}) vs.

Temperature V_{CC_C}=3.0V (V_SEL=HIGH)

25

20

25

20

15

10

5

V_BAT= 5.5V

15

V_BAT= 5.5V

V_BAT= 3.1V

V_BAT= 2.7V

10

5

‐50

‐30

‐10

10

30

50

70

90

‐50

0

50

TEMPERATURE ( °C)

Figure 6. IV_BATvs. Temperature at V_{CC_C}=3.0V

(V_SEL=HIGH)

Figure 7. IV_BATvs. Temperature at V_{CC_C}=1.8V

(V_SEL=LOW)

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

9

Application Information

Card Supply Converter

Level Shifters

The FXLP4555 interface DC-DC converter is a Low

Dropout (LDO) voltage regulator capable of supplying a

current in excess of 50mA under 1.8V or 3.0V.

Quiescent current is typically lower than 20µA (see

Figure 6 and Figure 7). VSEL is a select input, allowing

a logic level signal to select a regulated voltage of 1.8V

(VSEL = LOW) or 3.0V (VSEL = HIGH).

The level shifters accommodate any voltage difference

between the Baseband (BB) Processor (1.65V – 5.5V)

and the SIM card (1.8V or 3V). The RESET and CLOCK

level shifters are uni-directional (from BB to SIM).

The bidirectional I/O line automatically adapts the

voltage difference between the baseband and the SIM

card in both directions. In addition, with the pull-up

resistor, an active edge rate accelerator circuit (see

FXLP4555 has a shutdown input (EN) that allows it to

turn off or turn on the regulator output. Figure 8 shows a

simplified view of the voltage regulator. The V_{CC_C}output

is internally current limited and protected against short

circuits. The short-circuit current (I_{VCC_C_SC}) is constant

over the SIM Card V_CCand V_BAT,while it varies with

operating temperature, typically in the range of 90mA to

140mA (Figure 4 and Figure 5).

Figure 9) provides

a fast charge of the stray

capacitance, yielding a rise time within the ISO7816-3

specifications.

The typical waveform provided in Figure 10 shows how

the accelerator operates. Two distinct slew rates are

observed. From 0V to approximately VCC/2, the slew

rate is the RC time constant of the pull-up resistor and

the stray capacitance. When the input slope crosses the

VCC/2 threshold, the edge rate accelerator is activated,

resulting in the faster slew rate from approximately

VCC/2 to V_CCas depicted in Figure 10.

To guarantee a stable LDO, the VCC_C output is

connected to a 1.0µF bypass ceramic capacitor to

ground. At the input, V_BATis bypassed to ground with a

0.1µF ceramic capacitor.

VBAT

VCC_C

EN

VSEL

Figure 8. Simplified Block Diagram of the LDO

Voltage Regulator

Figure 9. Basic I/O Line Interface

Figure 10. SIM_IO Typical Rise and Fall Times with Figure 11. Typical Schmitt Trigger Characteristics

Stray Capacitance > 30pF

(33pF Capacitor Connected on the Board)

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

10

Applications Information (Continued)

Input Schmitt Triggers

Printed Circuit Board (PCB) Layout

All the logic input pins (except I/O_H and I/O_C) have

built-in Schmitt trigger circuits to prevent uncontrolled

operation. Typical dynamic characteristics of the related

pins are depicted in Figure 11.

Careful layout routing should be applied to achieve

efficient operating of the device in its mobile or portable

environment and to fully exploit its performance.

The bypass capacitors must be connected as close as

possible to the device pins (VCC_C, VCCA, or VBAT) to

reduce possible parasitic behaviors (ripple and noise). It

is recommended to use ceramic capacitors.

The output signal is guaranteed to go HIGH when the

input voltage is above 0.7 x V_DDand go LOW when the

input voltage is below 0.4V. See Electrical

Characteristics section.

The exposed pad should be connected to ground as

well as the unconnected pins (NC). A relatively large

ground plane is recommended.

Shutdown Operating

To save power, it is possible to put the FXLP4555 in

Shutdown Mode by setting the pin EN LOW. The device

enters Shutdown Mode automatically when V_CCAgoes

lower than 1.1V typically.

Clock Stop

Section 6.3.2 of ISO7816-3 identifies the “Power

Management” feature of Clock Stop. For cards

supporting Clock Stop, when the interface device

expects no transmission from the card and when I/O

has remained at state H for at least 1,860 clock cycles

(delay t_g), then according to Figure 13, the interface

device may stop the clock on CLK (at time t_e) while the

SIM card V_CCremains powered and RST at state H.

ESD Protection

The FXLP4555 SIM interface features an HBM ESD

voltage protection in excess of 7kV for all the SIM pins

(IO_C, CLK_C, RST_C, VCC_C and GND). All the other

pins (Host side) sustain at least 2kV. The HBM ESD

voltage required by the ISO7816 standard is 4kV.

Figure 12.

Clock Stop

When the clock is stopped (from time t_eto time t_f), CLK

shall be maintained either at state H or at state L,

according to the clock stop indicator X defined in section

8.3 of the ISO7816-3 specification.

The FXLP4555 supports the above description of Clock

Stop per ISO7816-3 specifications.

At time t_f, the interface device restarts the clock and the

information exchange on I/O may continue after at least

700 clock cycles (at time t_f+ t_h).

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

11

Physical Dimensions

Figure 13.

16-Lead, Molded Leadless Package (MLP), QUAD, JEDEC MO-220, 3mm Square

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/MLP16B.html.

For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:

http://www.fairchildsemi.com/packaging/3x3MLP16_Pack_TNR.pdf.

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

12

FXLP4555 • Rev. 1.0.0

www.fairchildsemi.com

13

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

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1


型号：	FXLP4555MPX
厂家：	ONSEMI
描述：	SIM 卡电源电平转换器转换器电平转换器
文件：	总15页 (文件大小：1112K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FXLP4555MPX [ONSEMI]

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